\r
#include "CpuCommonFeatures.h"\r
\r
-#define MAX_TOPA_ENTRY_COUNT 2\r
-\r
///\r
-/// Processor trace buffer size selection.\r
+/// This macro define the max entries in the Topa table.\r
+/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region. \r
+/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the \r
+/// current table (for circular array) or to the base of another table. \r
+/// At least 2 entries are needed because the list of entries must \r
+/// be terminated by an entry with the END bit set to 1, so 2 \r
+/// entries are required to use a single valid entry.\r
///\r
-typedef enum {\r
- Enum4K = 0,\r
- Enum8K,\r
- Enum16K,\r
- Enum32K,\r
- Enum64K,\r
- Enum128K,\r
- Enum256K,\r
- Enum512K,\r
- Enum1M,\r
- Enum2M,\r
- Enum4M,\r
- Enum8M,\r
- Enum16M,\r
- Enum32M,\r
- Enum64M,\r
- Enum128M,\r
- EnumProcTraceMemDisable\r
-} PROC_TRACE_MEM_SIZE;\r
+#define MAX_TOPA_ENTRY_COUNT 2\r
+\r
\r
///\r
/// Processor trace output scheme selection.\r
///\r
typedef enum {\r
- OutputSchemeSingleRange = 0,\r
- OutputSchemeToPA,\r
- OutputSchemeInvalid\r
-} PROC_TRACE_OUTPUT_SCHEME;\r
+ RtitOutputSchemeSingleRange = 0,\r
+ RtitOutputSchemeToPA\r
+} RTIT_OUTPUT_SCHEME;\r
\r
typedef struct {\r
BOOLEAN ProcTraceSupported;\r
} PROC_TRACE_DATA;\r
\r
typedef struct {\r
- UINT64 TopaEntry[MAX_TOPA_ENTRY_COUNT];\r
+ RTIT_TOPA_TABLE_ENTRY TopaEntry[MAX_TOPA_ENTRY_COUNT];\r
} PROC_TRACE_TOPA_TABLE;\r
\r
/**\r
// Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)\r
//\r
ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
- if ((ProcTraceData->ProcTraceMemSize >= EnumProcTraceMemDisable) ||\r
- (ProcTraceData->ProcTraceOutputScheme >= OutputSchemeInvalid)) {\r
+ ASSERT (ProcTraceData != NULL);\r
+ if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||\r
+ (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {\r
return FALSE;\r
}\r
\r
AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);\r
ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);\r
ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);\r
- if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported || \r
- ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported) {\r
+ if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||\r
+ (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {\r
return TRUE;\r
}\r
\r
IN BOOLEAN State\r
)\r
{\r
- UINT64 MsrValue;\r
UINT32 MemRegionSize;\r
UINTN Pages;\r
UINTN Alignment;\r
PROC_TRACE_TOPA_TABLE *TopaTable;\r
PROC_TRACE_DATA *ProcTraceData;\r
BOOLEAN FirstIn;\r
+ MSR_IA32_RTIT_CTL_REGISTER CtrlReg;\r
+ MSR_IA32_RTIT_STATUS_REGISTER StatusReg;\r
+ MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;\r
+ MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;\r
+ RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;\r
\r
ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
+ ASSERT (ProcTraceData != NULL);\r
\r
MemRegionBaseAddr = 0;\r
FirstIn = FALSE;\r
//\r
// Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CTL[0]==1b\r
//\r
- MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
- if ((MsrValue & BIT0) != 0) {\r
+ CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
+ if (CtrlReg.Bits.TraceEn != 0) {\r
///\r
/// Clear bit 0 in MSR IA32_RTIT_CTL (570)\r
///\r
- MsrValue &= (UINT64) ~BIT0;\r
+ CtrlReg.Bits.TraceEn = 0;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
MSR_IA32_RTIT_CTL,\r
- MsrValue\r
+ CtrlReg.Uint64\r
);\r
\r
///\r
/// Clear MSR IA32_RTIT_STS (571h) to all zeros\r
///\r
- MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r
- MsrValue &= 0x0;\r
+ StatusReg.Uint64 = 0x0;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
MSR_IA32_RTIT_STATUS,\r
- MsrValue\r
+ StatusReg.Uint64\r
);\r
}\r
\r
// Single Range output scheme\r
//\r
if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && \r
- (ProcTraceData->ProcTraceOutputScheme == OutputSchemeSingleRange)) {\r
+ (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {\r
if (FirstIn) {\r
DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));\r
}\r
//\r
// Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)\r
//\r
- MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
- MsrValue &= (UINT64) ~BIT8;\r
+ CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
+ CtrlReg.Bits.ToPA = 0;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
MSR_IA32_RTIT_CTL,\r
- MsrValue\r
+ CtrlReg.Uint64\r
);\r
\r
//\r
- // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with the allocated Memory Region\r
+ // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region\r
//\r
- MsrValue = (UINT64) MemRegionBaseAddr;\r
+ OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;\r
+ OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
MSR_IA32_RTIT_OUTPUT_BASE,\r
- MsrValue\r
+ OutputBaseReg.Uint64\r
);\r
\r
//\r
// Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)\r
//\r
- MsrValue = (UINT64) MemRegionSize - 1;\r
+ OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;\r
+ OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
MSR_IA32_RTIT_OUTPUT_MASK_PTRS,\r
- MsrValue\r
+ OutputMaskPtrsReg.Uint64\r
);\r
-\r
}\r
\r
//\r
// ToPA(Table of physical address) scheme\r
//\r
if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && \r
- (ProcTraceData->ProcTraceOutputScheme == OutputSchemeToPA)) {\r
+ (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {\r
//\r
// Create ToPA structure aligned at 4KB for each logical thread\r
// with at least 2 entries by 8 bytes size each. The first entry\r
}\r
\r
TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr;\r
- TopaTable->TopaEntry[0] = (UINT64) (MemRegionBaseAddr | ((ProcTraceData->ProcTraceMemSize) << 6)) & ~BIT0;\r
- TopaTable->TopaEntry[1] = (UINT64) TopaTableBaseAddr | BIT0;\r
+ TopaEntryPtr = &TopaTable->TopaEntry[0];\r
+ TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;\r
+ TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;\r
+ TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;\r
+ TopaEntryPtr->Bits.END = 0;\r
+\r
+ TopaEntryPtr = &TopaTable->TopaEntry[1];\r
+ TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;\r
+ TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;\r
+ TopaEntryPtr->Bits.END = 1;\r
\r
//\r
- // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with ToPA base\r
+ // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base\r
//\r
- MsrValue = (UINT64) TopaTableBaseAddr;\r
+ OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;\r
+ OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
MSR_IA32_RTIT_OUTPUT_BASE,\r
- MsrValue\r
+ OutputBaseReg.Uint64\r
);\r
\r
//\r
// Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0\r
//\r
+ OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;\r
+ OutputMaskPtrsReg.Bits.OutputOffset = 0;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
MSR_IA32_RTIT_OUTPUT_MASK_PTRS,\r
- 0x7F\r
+ OutputMaskPtrsReg.Uint64\r
);\r
//\r
// Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)\r
//\r
- MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
- MsrValue |= BIT8;\r
+ CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
+ CtrlReg.Bits.ToPA = 1;\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
MSR_IA32_RTIT_CTL,\r
- MsrValue\r
+ CtrlReg.Uint64\r
);\r
}\r
\r
///\r
/// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)\r
///\r
- MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
- MsrValue |= (UINT64) BIT0 + BIT2 + BIT3 + BIT13;\r
+ CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
+ CtrlReg.Bits.OS = 1;\r
+ CtrlReg.Bits.User = 1;\r
+ CtrlReg.Bits.BranchEn = 1;\r
if (!State) {\r
- MsrValue &= (UINT64) ~BIT0;\r
+ CtrlReg.Bits.TraceEn = 0;\r
+ } else {\r
+ CtrlReg.Bits.TraceEn = 1;\r
}\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
MSR_IA32_RTIT_CTL,\r
- MsrValue\r
+ CtrlReg.Uint64\r
);\r
\r
return RETURN_SUCCESS;\r
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