UefiCpuPkg: Enhance feature dependency check

[mirror_edk2.git] / UefiCpuPkg / Library / CpuCommonFeaturesLib / ProcTrace.c

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
index e4636b20db56d733d9d72e479afc46c7692ab389..b42f5de2e307c46ea2c51ebcd92b86afd7a4b528 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
@@ -30,10 +30,9 @@
 /// Processor trace output scheme selection.\r
 ///\r
 typedef enum {\r
-  OutputSchemeSingleRange = 0,\r
-  OutputSchemeToPA,\r
-  OutputSchemeInvalid\r
-} PROC_TRACE_OUTPUT_SCHEME;\r
+  RtitOutputSchemeSingleRange = 0,\r
+  RtitOutputSchemeToPA\r
+} RTIT_OUTPUT_SCHEME;\r
 \r
 typedef struct  {\r
   BOOLEAN  ProcTraceSupported;\r
@@ -121,8 +120,9 @@ ProcTraceSupport (
   // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)\r
   //\r
   ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
+  ASSERT (ProcTraceData != NULL);\r
   if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||\r
-      (ProcTraceData->ProcTraceOutputScheme > ProcTraceOutputSchemeToPA)) {\r
+      (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {\r
     return FALSE;\r
   }\r
 \r
@@ -138,8 +138,8 @@ ProcTraceSupport (
   AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);\r
   ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);\r
   ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);\r
-  if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported || \r
-      ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported) {\r
+  if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||\r
+      (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {\r
     return TRUE;\r
   }\r
 \r
@@ -192,6 +192,7 @@ ProcTraceInitialize (
   RTIT_TOPA_TABLE_ENTRY                *TopaEntryPtr;\r
 \r
   ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
+  ASSERT (ProcTraceData != NULL);\r
 \r
   MemRegionBaseAddr = 0;\r
   FirstIn = FALSE;\r
@@ -291,7 +292,7 @@ ProcTraceInitialize (
   //  Single Range output scheme\r
   //\r
   if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && \r
-      (ProcTraceData->ProcTraceOutputScheme == OutputSchemeSingleRange)) {\r
+      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {\r
     if (FirstIn) {\r
       DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));\r
     }\r
@@ -324,7 +325,7 @@ ProcTraceInitialize (
     // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)\r
     //\r
     OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;\r
-    OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 ((UINT64) (MemRegionSize - 1), 32) & 0xFFFFFFFF;\r
+    OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;\r
     CPU_REGISTER_TABLE_WRITE64 (\r
       ProcessorNumber,\r
       Msr,\r
@@ -337,7 +338,7 @@ ProcTraceInitialize (
   //  ToPA(Table of physical address) scheme\r
   //\r
   if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && \r
-      (ProcTraceData->ProcTraceOutputScheme == OutputSchemeToPA)) {\r
+      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {\r
     //\r
     //  Create ToPA structure aligned at 4KB for each logical thread\r
     //  with at least 2 entries by 8 bytes size each. The first entry\r