/** @file\r
SMM CPU misc functions for x64 arch specific.\r
- \r
-Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
/**\r
Initialize Gdt for all processors.\r
- \r
+\r
@param[in] Cr3 CR3 value.\r
@param[out] GdtStepSize The step size for GDT table.\r
\r
return GdtTssTables;\r
}\r
\r
-/**\r
- This function sets GDT/IDT buffer to be RO and XP.\r
-**/\r
-VOID\r
-PatchGdtIdtMap (\r
- VOID\r
- )\r
-{\r
- EFI_PHYSICAL_ADDRESS BaseAddress;\r
- UINTN Size;\r
-\r
- //\r
- // GDT\r
- //\r
- DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - GDT:\n"));\r
-\r
- BaseAddress = mGdtBuffer;\r
- Size = ALIGN_VALUE(mGdtBufferSize, SIZE_4KB);\r
- SmmSetMemoryAttributes (\r
- BaseAddress,\r
- Size,\r
- EFI_MEMORY_RO\r
- );\r
- SmmSetMemoryAttributes (\r
- BaseAddress,\r
- Size,\r
- EFI_MEMORY_XP\r
- );\r
-\r
- //\r
- // IDT\r
- //\r
- DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - IDT:\n"));\r
-\r
- BaseAddress = gcSmiIdtr.Base;\r
- Size = ALIGN_VALUE(gcSmiIdtr.Limit + 1, SIZE_4KB);\r
- SmmSetMemoryAttributes (\r
- BaseAddress,\r
- Size,\r
- EFI_MEMORY_RO\r
- );\r
- SmmSetMemoryAttributes (\r
- BaseAddress,\r
- Size,\r
- EFI_MEMORY_XP\r
- );\r
-}\r
-\r
/**\r
Get Protected mode code segment from current GDT table.\r
\r
UINTN GdtEntryCount;\r
UINT16 Index;\r
\r
- Index = (UINT16) -1;\r
AsmReadGdtr (&GdtrDesc);\r
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);\r
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;\r
}\r
GdtEntry++;\r
}\r
- ASSERT (Index != -1);\r
+ ASSERT (Index != GdtEntryCount);\r
return Index * 8;\r
}\r
\r