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UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add support for PCD PcdPteMemoryEncryptionAdd...
[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformDxe / PciDevice.c
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c b/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
index 16aaa1856307f548421cdc21f76dba2b73e1fb53..8c2bfff3c432e996340ff15566c032c9ae400a65 100644 (file)
--- a/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
+++ b/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
@@ -102,8 +102,6 @@ InitBadBars(
   )\r
 {\r
 \r
-  EFI_STATUS                          Status;\r
-  PCI_IO_DEVICE                       *PciIoDevice;\r
   UINT64                              BaseAddress = 0;\r
   UINT64                              TempBaseAddress = 0;\r
   UINT8                               RevId = 0;\r
@@ -112,8 +110,6 @@ InitBadBars(
   UINT64                              MemSize;\r
   UINTN                               MemSizeBits;\r
 \r
-\r
-  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
   switch ( VendorId) {\r
     case ATI_VENDOR_ID:\r
       //\r
@@ -124,31 +120,31 @@ InitBadBars(
       //\r
       // Get original BAR address\r
       //\r
-      Status = PciIo->Pci.Read (\r
-                            PciIo,\r
-                            EfiPciIoWidthUint32,\r
-                            Bar,\r
-                            1,\r
-                                (VOID *) &BaseAddress\r
-                            );\r
+      PciIo->Pci.Read (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   Bar,\r
+                   1,\r
+                       (VOID *) &BaseAddress\r
+                   );\r
       //\r
       // Find BAR size\r
       //\r
       TempBaseAddress = 0xffffffff;\r
-      Status = PciIo->Pci.Write (\r
-                            PciIo,\r
-                            EfiPciIoWidthUint32,\r
-                            Bar,\r
-                            1,\r
-                                 (VOID *) &TempBaseAddress\r
-                            );\r
-      Status = PciIo->Pci.Read (\r
-                            PciIo,\r
-                            EfiPciIoWidthUint32,\r
-                            Bar,\r
-                            1,\r
-                                (VOID *) &TempBaseAddress\r
-                            );\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   Bar,\r
+                   1,\r
+                        (VOID *) &TempBaseAddress\r
+                   );\r
+      PciIo->Pci.Read (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   Bar,\r
+                   1,\r
+                       (VOID *) &TempBaseAddress\r
+                   );\r
       TempBaseAddress &= 0xfffffffe;\r
       MemSize = 1;\r
       while ((TempBaseAddress & 0x01) == 0) {\r
@@ -159,32 +155,32 @@ InitBadBars(
       //\r
       // Free up allocated memory memory and re-allocate with increased size.\r
       //\r
-      Status = gDS->FreeMemorySpace (\r
-                      BaseAddress,\r
-                      MemSize\r
-                      );\r
+      gDS->FreeMemorySpace (\r
+             BaseAddress,\r
+             MemSize\r
+             );\r
       //\r
       // Force new alignment\r
       //\r
       MemSize = 0x8000000;\r
       MemSizeBits = 28;\r
 \r
-      Status = gDS->AllocateMemorySpace (\r
-                      EfiGcdAllocateAnySearchBottomUp,\r
-                      EfiGcdMemoryTypeMemoryMappedIo,\r
-                      MemSizeBits,           // Alignment\r
-                      MemSize,\r
-                      &BaseAddress,\r
-                      mImageHandle,\r
-                      NULL\r
-                      );\r
-      Status = PciIo->Pci.Write (\r
-                            PciIo,\r
-                            EfiPciIoWidthUint32,\r
-                            Bar,\r
-                            1,\r
-                                 (VOID *) &BaseAddress\r
-                            );\r
+      gDS->AllocateMemorySpace (\r
+             EfiGcdAllocateAnySearchBottomUp,\r
+             EfiGcdMemoryTypeMemoryMappedIo,\r
+             MemSizeBits,           // Alignment\r
+             MemSize,\r
+             &BaseAddress,\r
+             mImageHandle,\r
+             NULL\r
+             );\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   Bar,\r
+                   1,\r
+                        (VOID *) &BaseAddress\r
+                   );\r
 \r
       break;\r
     case    NCR_VENDOR_ID:\r
@@ -195,22 +191,22 @@ InitBadBars(
   //\r
   for (Bar = 0x10; Bar < 0x28; Bar+= 4) {\r
 \r
-    Status = PciIo->Pci.Read (\r
-                          PciIo,\r
-                          EfiPciIoWidthUint32,\r
-                          Bar,\r
-                          1,\r
-                              (VOID *) &BaseAddress\r
-                          );\r
+    PciIo->Pci.Read (\r
+                 PciIo,\r
+                 EfiPciIoWidthUint32,\r
+                 Bar,\r
+                 1,\r
+                     (VOID *) &BaseAddress\r
+                 );\r
     if (BaseAddress && 0x01) {\r
       TempBaseAddress = 0xffffffff;\r
-      Status = PciIo->Pci.Write (\r
-                            PciIo,\r
-                            EfiPciIoWidthUint32,\r
-                            Bar,\r
-                            1,\r
-                                 (VOID *) &TempBaseAddress\r
-                            );\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   Bar,\r
+                   1,\r
+                        (VOID *) &TempBaseAddress\r
+                   );\r
       TempBaseAddress &= 0xfffffffc;\r
       IoSize = 1;\r
       while ((TempBaseAddress & 0x01) == 0) {\r
@@ -218,28 +214,28 @@ InitBadBars(
         IoSize = IoSize << 1;\r
       }\r
       if (IoSize < MIN_NCR_IO_SIZE) {\r
-        Status = gDS->FreeIoSpace (\r
-                        BaseAddress,\r
-                        IoSize\r
-                        );\r
-\r
-        Status = gDS->AllocateIoSpace (\r
-                        EfiGcdAllocateAnySearchTopDown,\r
-                        EfiGcdIoTypeIo,\r
-                        NCR_GRAN,           // Alignment\r
-                        MIN_NCR_IO_SIZE,\r
-                        &BaseAddress,\r
-                        mImageHandle,\r
-                        NULL\r
-                        );\r
+        gDS->FreeIoSpace (\r
+               BaseAddress,\r
+               IoSize\r
+               );\r
+\r
+        gDS->AllocateIoSpace (\r
+               EfiGcdAllocateAnySearchTopDown,\r
+               EfiGcdIoTypeIo,\r
+               NCR_GRAN,           // Alignment\r
+               MIN_NCR_IO_SIZE,\r
+               &BaseAddress,\r
+               mImageHandle,\r
+               NULL\r
+               );\r
         TempBaseAddress = BaseAddress + 1;\r
-        Status = PciIo->Pci.Write (\r
-                              PciIo,\r
-                              EfiPciIoWidthUint32,\r
-                              Bar,\r
-                              1,\r
-                                   (VOID *) &TempBaseAddress\r
-                              );\r
+        PciIo->Pci.Write (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     Bar,\r
+                     1,\r
+                          (VOID *) &TempBaseAddress\r
+                     );\r
       }\r
     }\r
   }\r
@@ -255,13 +251,13 @@ InitBadBars(
         //  Controller.\r
         //  All Tekoa A2 or earlier step chips for now.\r
         //\r
-        Status = PciIo->Pci.Read (\r
-                              PciIo,\r
-                              EfiPciIoWidthUint8,\r
-                              PCI_REVISION_ID_OFFSET,\r
-                              1,\r
-                              &RevId\r
-                              );\r
+        PciIo->Pci.Read (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint8,\r
+                     PCI_REVISION_ID_OFFSET,\r
+                     1,\r
+                     &RevId\r
+                     );\r
         if (RevId <= 0x02) {\r
           for (Bar = 0x14; Bar < 0x24; Bar+= 4) {\r
             //\r
@@ -269,13 +265,13 @@ InitBadBars(
             // Bars don't worry aboyut freeing up thge allocs.\r
             //\r
             TempBaseAddress = 0x0;\r
-            Status = PciIo->Pci.Write (\r
-                                  PciIo,\r
-                                  EfiPciIoWidthUint32,\r
-                                  Bar,\r
-                                  1,\r
-                                       (VOID *) &TempBaseAddress\r
-                                  );\r
+            PciIo->Pci.Write (\r
+                         PciIo,\r
+                         EfiPciIoWidthUint32,\r
+                         Bar,\r
+                         1,\r
+                              (VOID *) &TempBaseAddress\r
+                         );\r
           } // end for\r
         }\r
         else\r
@@ -286,13 +282,13 @@ InitBadBars(
           //since Tekoa does not fully support IDE Bus Mastering\r
           //\r
           TempBaseAddress = 0x0;\r
-          Status = PciIo->Pci.Write (\r
-                                PciIo,\r
-                                EfiPciIoWidthUint32,\r
-                                0x20,\r
-                                1,\r
-                                     (VOID *) &TempBaseAddress\r
-                                );\r
+          PciIo->Pci.Write (\r
+                       PciIo,\r
+                       EfiPciIoWidthUint32,\r
+                       0x20,\r
+                       1,\r
+                            (VOID *) &TempBaseAddress\r
+                       );\r
         }\r
       }\r
       break;\r
@@ -308,19 +304,17 @@ ProgramPciLatency(
   IN    EFI_PCI_IO_PROTOCOL           *PciIo\r
   )\r
 {\r
-  EFI_STATUS                          Status;\r
-\r
   //\r
   // Program Master Latency Timer\r
   //\r
   if (mSystemConfiguration.PciLatency != 0) {\r
-     Status = PciIo->Pci.Write (\r
-                           PciIo,\r
-                           EfiPciIoWidthUint8,\r
-                           PCI_LATENCY_TIMER_OFFSET,\r
-                           1,\r
-                           &mSystemConfiguration.PciLatency\r
-                           );\r
+     PciIo->Pci.Write (\r
+                  PciIo,\r
+                  EfiPciIoWidthUint8,\r
+                  PCI_LATENCY_TIMER_OFFSET,\r
+                  1,\r
+                  &mSystemConfiguration.PciLatency\r
+                  );\r
   }\r
   return;\r
 }\r
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