The GICD_IGROUPR0 is banked for each connected processor. It means the
Non-Secure bits for the PPIs (Private Peripheral Interrupts) must be
configured for every processor.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13135
6f19259b-4bc3-4df7-8a09-
765794883524
12 files changed:
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
**/\r
\r
#include <Base.h>\r
**/\r
\r
#include <Base.h>\r
+#include <Library/ArmLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
IN INTN GicDistributorBase,\r
IN INTN GicInterruptInterfaceBase\r
)\r
IN INTN GicDistributorBase,\r
IN INTN GicInterruptInterfaceBase\r
)\r
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
}\r
\r
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
}\r
\r
- // Ensure all GIC interrupts are Non-Secure\r
- for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+ // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
+ if (IS_PRIMARY_CORE(MpId)) {\r
+ // Ensure all GIC interrupts are Non-Secure\r
+ for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+ }\r
+ } else {\r
+ // The secondary cores only set the Non Secure bit to their banked PPIs\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
}\r
\r
// Ensure all interrupts can get through the priority mask\r
}\r
\r
// Ensure all interrupts can get through the priority mask\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
MdePkg/MdePkg.dec\r
\r
[LibraryClasses]\r
MdePkg/MdePkg.dec\r
\r
[LibraryClasses]\r
DebugLib\r
IoLib\r
PcdLib\r
DebugLib\r
IoLib\r
PcdLib\r
[FixedPcd.common]\r
gArmTokenSpaceGuid.PcdGicNumInterrupts\r
gArmTokenSpaceGuid.PcdGicSgiIntId\r
[FixedPcd.common]\r
gArmTokenSpaceGuid.PcdGicNumInterrupts\r
gArmTokenSpaceGuid.PcdGicSgiIntId\r
+\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
IN INTN GicDistributorBase,\r
IN INTN GicInterruptInterfaceBase\r
);\r
IN INTN GicDistributorBase,\r
IN INTN GicInterruptInterfaceBase\r
);\r
**/
VOID
ArmPlatformTrustzoneInit (
**/
VOID
ArmPlatformTrustzoneInit (
gArmTokenSpaceGuid.PcdTrustzoneSupport\r
\r
gArmTokenSpaceGuid.PcdL2x0ControllerBase\r
gArmTokenSpaceGuid.PcdTrustzoneSupport\r
\r
gArmTokenSpaceGuid.PcdL2x0ControllerBase\r
+\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
**/
VOID
ArmPlatformTrustzoneInit (
**/
VOID
ArmPlatformTrustzoneInit (
+ // Nothing to do
+ if (!IS_PRIMARY_CORE(MpId)) {
+ return;
+ }
+
//
// Setup TZ Protection Controller
//
//
// Setup TZ Protection Controller
//
**/
VOID
ArmPlatformTrustzoneInit (
**/
VOID
ArmPlatformTrustzoneInit (
)
{
// No TZPC or TZASC on RTSM to initialize
)
{
// No TZPC or TZASC on RTSM to initialize
**/
VOID
ArmPlatformTrustzoneInit (
**/
VOID
ArmPlatformTrustzoneInit (
**/
VOID
ArmPlatformTrustzoneInit (
**/
VOID
ArmPlatformTrustzoneInit (
+ // Secondary cores might have to set the Secure SGIs into the GICD_IGROUPR0
+ if (!IS_PRIMARY_CORE(MpId)) {
+ return;
+ }
+
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
+\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
// Set up Monitor World (Vector Table, etc)
ArmSecureMonitorWorldInitialize ();
// Set up Monitor World (Vector Table, etc)
ArmSecureMonitorWorldInitialize ();
- // Setup the Trustzone Chipsets
- if (IS_PRIMARY_CORE(MpId)) {
- // Transfer the interrupt to Non-secure World
- ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
+ // Transfer the interrupt to Non-secure World
+ ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
- // Initialize platform specific security policy
- ArmPlatformTrustzoneInit ();
+ // Initialize platform specific security policy
+ ArmPlatformTrustzoneInit (MpId);
+ // Setup the Trustzone Chipsets
+ if (IS_PRIMARY_CORE(MpId)) {
if (ArmIsMpCore()) {
// Waiting for the Primary Core to have finished to initialize the Secure World
ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
if (ArmIsMpCore()) {
// Waiting for the Primary Core to have finished to initialize the Secure World
ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
-/**
- Initialize the Secure peripherals and memory regions
-
- If Trustzone is supported by your platform then this function makes the required initialization
- of the secure peripherals and memory regions.
-
-**/
-VOID
-ArmPlatformTrustzoneInit (
- VOID
- )
-{
- ASSERT(FALSE);
-}
-
/**
Remap the memory at 0x0
/**
Remap the memory at 0x0