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2019-06-27 | Alistair Francis | hw/riscv: Extend the kernel loading support Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-27 | Alistair Francis | hw/riscv: Add support for loading a firmware Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-27 | Alistair Francis | hw/riscv: Split out the boot functions Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-27 | Bin Meng | riscv: sifive_u: Update the plic hart config to support... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-27 | Bin Meng | riscv: sifive_u: Do not create hard-coded phandles... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-27 | Wladimir J. van... | disas/riscv: Fix `rdinstreth` constraint Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-27 | Michael Clark | disas/riscv: Disassemble reserved compressed encodings... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-26 | Atish Patra | riscv: virt: Add cpu-topology DT node. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-26 | Jim Wilson | RISC-V: Update syscall list for 32-bit support. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-26 | Joel Sing | RISC-V: Clear load reservations on context switch and SC Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-26 | Palmer Dabbelt | RISC-V: Add support for the Zicsr extension Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-26 | Palmer Dabbelt | RISC-V: Add support for the Zifencei extension Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-25 | Alistair Francis | target/riscv: Add support for disabling/enabling Counters Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-25 | Alistair Francis | target/riscv: Remove user version information Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-25 | Alistair Francis | target/riscv: Require either I or E base extension Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-25 | Alistair Francis | qemu-deprecated.texi: Deprecate the RISC-V privledge... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-25 | Alistair Francis | target/riscv: Set privledge spec 1.11.0 as default Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-25 | Alistair Francis | target/riscv: Add the mcountinhibit CSR Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Alistair Francis | target/riscv: Add the privledge spec version 1.11.0 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Alistair Francis | target/riscv: Restructure deprecatd CPUs Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Palmer Dabbelt | RISC-V: Fix a memory leak when realizing a sifive_e Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Bin Meng | riscv: virt: Correct pci "bus-range" encoding Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Hesham Almatary | RISC-V: Fix a PMP check with the correct access size Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Hesham Almatary | RISC-V: Fix a PMP bug where it succeeds even if PMP... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Hesham Almatary | RISC-V: Check PMP during Page Table Walks Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Hesham Almatary | RISC-V: Check for the effective memory privilege mode... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Hesham Almatary | RISC-V: Raise access fault exceptions on PMP violations Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Hesham Almatary | RISC-V: Only Check PMP if MMU translation succeeds Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Michael Clark | target/riscv: Implement riscv_cpu_unassigned_access Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Dayeol Lee | target/riscv: Fix PMP range boundary address bug Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Nathaniel Graff | sifive_prci: Read and write PRCI registers Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-06-24 | Alistair Francis | target/riscv: Allow setting ISA extensions via CPU... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Jonathan Behrens | target/riscv: Only flush TLB if SATP.ASID changes Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Jonathan Behrens | target/riscv: More accurate handling of `sip` CSR Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Richard Henderson | target/riscv: Add checks for several RVC reserved operands Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Add the HGATP register masks Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Add the HSTATUS register masks Reviwed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Add Hypervisor CSR macros Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Allow setting mstatus virtulisation bits Revieweb-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Add the MPV and MTL mstatus bits Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Improve the scause logic Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Trigger interrupt on MIP update asynchronously Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Mark privilege level 2 as reserved Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | riscv: spike: Add a generic spike machine Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Deprecate the generic no MMU CPUs Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Add a base 32 and 64 bit CPU Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | target/riscv: Create settable CPU properties Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | riscv: virt: Allow specifying a CPU via commandline Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Alistair Francis | linux-user/riscv: Add the CPU type as a comment Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Jonathan Behrens | target/riscv: Remove unused include of riscv_htif.h... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Richard Henderson | target/riscv: Remove spaces from register names Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Richard Henderson | target/riscv: Split gen_arith_imm into functional and... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Richard Henderson | target/riscv: Split RVC32 and RVC64 insns into separate... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Richard Henderson | target/riscv: Use pattern groups in insn16.decode Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Richard Henderson | target/riscv: Merge argument decode for RVC shifti Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Richard Henderson | target/riscv: Merge argument sets for insn32 and insn16 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Richard Henderson | target/riscv: Use --static-decode for decodetree Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Richard Henderson | target/riscv: Name the argument sets for all of insn32... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Fabien Chouteau | RISC-V: fix single stepping over ret and other branching... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Jonathan Behrens | target/riscv: Do not allow sfence.vma from user mode Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-05-24 | Fabien Chouteau | SiFive RISC-V GPIO Device Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-04-04 | Alistair Francis | riscv: plic: Log guest errors Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-04-04 | Alistair Francis | riscv: plic: Fix incorrect irq calculation Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-26 | Kito Cheng | target/riscv: Fix wrong expanding for c.fswsp Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-22 | Palmer Dabbelt | target/riscv: Zero extend the inputs of divuw and remuw Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Bin Meng | riscv: sifive_u: Correct UART0's IRQ in the device... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Bin Meng | riscv: sifive_uart: Generate TX interrupt Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Alistair Francis | target/riscv: Remove unused struct Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Alistair Francis | riscv: sifive_u: Allow up to 4 CPUs to be created Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Michael Clark | RISC-V: Update load reservation comment in do_interrupt Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Michael Clark | RISC-V: Convert trap debugging to trace events Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Michael Clark | RISC-V: Add support for vectored interrupts Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Michael Clark | RISC-V: Change local interrupts from edge to level Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Kito Cheng | RISC-V: linux-user support for RVE ABI Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Michael Clark | elf: Add RISC-V PSABI ELF header defines Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Michael Clark | RISC-V: Remove unnecessary disassembler constraints Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Michael Clark | RISC-V: Allow interrupt controllers to claim interrupts Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Michael Clark | RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Alistair Francis | riscv: pmp: Log pmp access errors as guest errors Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Jim Wilson | RISC-V: Add hooks to use the gdb xml files. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Jim Wilson | RISC-V: Add debug support for accessing CSRs. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Jim Wilson | RISC-V: Fixes to CSR_* register macros. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Jim Wilson | RISC-V: Add 64-bit gdb xml files. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-19 | Jim Wilson | RISC-V: Add 32-bit gdb xml files. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-03-18 | Bastian Koppelmann | target/riscv: Fix manually parsed 16 bit insn Tested-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Alistair Francis | riscv: Ensure the kernel start address is correctly... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Xi Wang | target/riscv: fix counter-enable checks in ctr() Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Palmer Dabbelt | MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Michael Clark | RISC-V: Add misa runtime write support Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Michael Clark | RISC-V: Add misa.MAFD checks to translate Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Michael Clark | RISC-V: Add misa to DisasContext Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Alistair Francis | RISC-V: Add priv_ver to DisasContext Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Michael Clark | RISC-V: Use riscv prefix consistently on cpu helpers Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Michael Clark | RISC-V: Implement mstatus.TSR/TW/TVM Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Richard Henderson | RISC-V: Mark mstatus.fs dirty Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-02-11 | Richard Henderson | RISC-V: Split out mstatus_fs from tb_flags Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-01-10 | Alistair Francis | default-configs: Enable USB support for RISC-V machines Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-01-09 | Michael Clark | RISC-V: Implement existential predicates for CSRs Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-01-09 | Michael Clark | RISC-V: Implement atomic mip/sip CSR updates Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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2019-01-08 | Michael Clark | RISC-V: Implement modular CSR helper interface Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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