ArmPlatformPkg/ArmPlatformLib.h: Removed non-required header file

[mirror_edk2.git] / ArmPkg / Drivers / ArmCpuLib / ArmCortexA9Lib / ArmCortexA9Lib.c

/** @file\r
\r
  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
#include <Library/ArmCpuLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
\r
#include <Chipset/ArmCortexA9.h>\r
\r
VOID\r
ArmEnableScu (\r
  VOID\r
  )\r
{\r
  INTN          ScuBase;\r
\r
  ScuBase = ArmGetScuBaseAddress();\r
\r
  // Invalidate all: write -1 to SCU Invalidate All register\r
  MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);\r
  // Enable SCU\r
  MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);\r
}\r
\r
VOID\r
ArmCpuSetup (\r
  IN  UINTN         MpId\r
  )\r
{\r
  // Enable SWP instructions\r
  ArmEnableSWPInstruction ();\r
\r
  // Enable program flow prediction, if supported.\r
  ArmEnableBranchPrediction ();\r
\r
  // If MPCore then Enable the SCU\r
  if (ArmIsMpCore()) {\r
    // Signals the Cortex-A9 processor is taking part in coherency\r
    ArmSetAuxCrBit (A9_FEATURE_SMP);\r
\r
    ArmEnableScu ();\r
  }\r
}\r
\r
\r
VOID\r
ArmCpuSetupSmpNonSecure (\r
  IN  UINTN         MpId\r
  )\r
{\r
  INTN          ScuBase;\r
\r
  // Make the SCU accessible in Non Secure world\r
  if (IS_PRIMARY_CORE(MpId)) {\r
    ScuBase = ArmGetScuBaseAddress();\r
\r
    // Allow NS access to SCU register\r
    MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r
    // Allow NS access to Private Peripherals\r
    MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r
  }\r
}\r