ArmPkg/ArmGic: Added GICv3 specific definitions

[mirror_edk2.git] / ArmPkg / Drivers / ArmGic / ArmGicLib.c

/** @file\r
*\r
*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Base.h>\r
#include <Library/ArmGicLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
\r
#include "GicV2/ArmGicV2Lib.h"\r
#include "GicV3/ArmGicV3Lib.h"\r
\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  // Read the GIC Identification Register\r
  return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);\r
}\r
\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
  IN  INTN          GicDistributorBase\r
  )\r
{\r
  return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicSendSgiTo (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          TargetListFilter,\r
  IN  INTN          CPUTargetList,\r
  IN  INTN          SgiId\r
  )\r
{\r
  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r
}\r
\r
/*\r
 * Acknowledge and return the value of the Interrupt Acknowledge Register\r
 *\r
 * InterruptId is returned separately from the register value because in\r
 * the GICv2 the register value contains the CpuId and InterruptId while\r
 * in the GICv3 the register value is only the InterruptId.\r
 *\r
 * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface\r
 * @param InterruptId                 InterruptId read from the Interrupt Acknowledge Register\r
 *\r
 * @retval value returned by the Interrupt Acknowledge Register\r
 *\r
 */\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
  IN  UINTN          GicInterruptInterfaceBase,\r
  OUT UINTN          *InterruptId\r
  )\r
{\r
  UINTN Value;\r
  ARM_GIC_ARCH_REVISION Revision;\r
\r
  Revision = ArmGicGetSupportedArchRevision ();\r
  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
    Value = ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);\r
    // InterruptId is required for the caller to know if a valid or spurious\r
    // interrupt has been read\r
    ASSERT (InterruptId != NULL);\r
    if (InterruptId != NULL) {\r
      *InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID;\r
    }\r
  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {\r
    Value = ArmGicV3AcknowledgeInterrupt ();\r
  } else {\r
    ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
    // Report Spurious interrupt which is what the above controllers would\r
    // return if no interrupt was available\r
    Value = 1023;\r
  }\r
\r
  return Value;\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicEndOfInterrupt (\r
  IN  UINTN                 GicInterruptInterfaceBase,\r
  IN UINTN                  Source\r
  )\r
{\r
  ARM_GIC_ARCH_REVISION Revision;\r
\r
  Revision = ArmGicGetSupportedArchRevision ();\r
  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
    ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);\r
  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {\r
    ArmGicV3EndOfInterrupt (Source);\r
  } else {\r
    ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
  }\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  Source\r
  )\r
{\r
  UINT32    RegOffset;\r
  UINTN     RegShift;\r
\r
  // Calculate enable register offset and bit position\r
  RegOffset = Source / 32;\r
  RegShift = Source % 32;\r
\r
  // Write set-enable register\r
  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  Source\r
  )\r
{\r
  UINT32    RegOffset;\r
  UINTN     RegShift;\r
\r
  // Calculate enable register offset and bit position\r
  RegOffset = Source / 32;\r
  RegShift = Source % 32;\r
\r
  // Write clear-enable register\r
  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);\r
}\r
\r
BOOLEAN\r
EFIAPI\r
ArmGicIsInterruptEnabled (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  Source\r
  )\r
{\r
  UINT32    RegOffset;\r
  UINTN     RegShift;\r
\r
  // Calculate enable register offset and bit position\r
  RegOffset = Source / 32;\r
  RegShift = Source % 32;\r
\r
  return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicDisableDistributor (\r
  IN  INTN          GicDistributorBase\r
  )\r
{\r
  // Disable Gic Distributor\r
  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  ARM_GIC_ARCH_REVISION Revision;\r
\r
  Revision = ArmGicGetSupportedArchRevision ();\r
  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
    ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);\r
  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {\r
    ArmGicV3EnableInterruptInterface ();\r
  } else {\r
    ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
  }\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  ARM_GIC_ARCH_REVISION Revision;\r
\r
  Revision = ArmGicGetSupportedArchRevision ();\r
  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
    ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);\r
  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {\r
    ArmGicV3DisableInterruptInterface ();\r
  } else {\r
    ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
  }\r
}\r