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2ef2b01e A |
1 | /** @file\r |
2 | \r | |
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
8513037f | 4 | Copyright (c) 2011, ARM Limited. All rights reserved.\r |
3402aac7 | 5 | \r |
d6ebcab7 | 6 | This program and the accompanying materials\r |
2ef2b01e A |
7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "CpuDxe.h"\r | |
17 | \r | |
8513037f | 18 | #include <Guid/IdleLoopEvent.h>\r |
19 | \r | |
3b44bb55 | 20 | BOOLEAN mIsFlushingGCD;\r |
f659880b A |
21 | \r |
22 | /**\r | |
3402aac7 RC |
23 | This function flushes the range of addresses from Start to Start+Length\r |
24 | from the processor's data cache. If Start is not aligned to a cache line\r | |
25 | boundary, then the bytes before Start to the preceding cache line boundary\r | |
26 | are also flushed. If Start+Length is not aligned to a cache line boundary,\r | |
27 | then the bytes past Start+Length to the end of the next cache line boundary\r | |
28 | are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r | |
29 | supported. If the data cache is fully coherent with all DMA operations, then\r | |
30 | this function can just return EFI_SUCCESS. If the processor does not support\r | |
f659880b A |
31 | flushing a range of the data cache, then the entire data cache can be flushed.\r |
32 | \r | |
33 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
34 | @param Start The beginning physical address to flush from the processor's data\r | |
35 | cache.\r | |
36 | @param Length The number of bytes to flush from the processor's data cache. This\r | |
37 | function may flush more bytes than Length specifies depending upon\r | |
38 | the granularity of the flush operation that the processor supports.\r | |
39 | @param FlushType Specifies the type of flush operation to perform.\r | |
40 | \r | |
41 | @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r | |
42 | the processor's data cache.\r | |
fcb880ec | 43 | @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r |
f659880b A |
44 | by FlushType.\r |
45 | @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r | |
46 | from the processor's data cache.\r | |
47 | \r | |
48 | **/\r | |
2ef2b01e A |
49 | EFI_STATUS\r |
50 | EFIAPI\r | |
51 | CpuFlushCpuDataCache (\r | |
52 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
53 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
54 | IN UINT64 Length,\r | |
55 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
56 | )\r | |
57 | {\r | |
f659880b | 58 | \r |
2ef2b01e A |
59 | switch (FlushType) {\r |
60 | case EfiCpuFlushTypeWriteBack:\r | |
8a4d81e6 | 61 | WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
62 | break;\r |
63 | case EfiCpuFlushTypeInvalidate:\r | |
8a4d81e6 | 64 | InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
65 | break;\r |
66 | case EfiCpuFlushTypeWriteBackInvalidate:\r | |
8a4d81e6 | 67 | WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
68 | break;\r |
69 | default:\r | |
70 | return EFI_INVALID_PARAMETER;\r | |
71 | }\r | |
3402aac7 | 72 | \r |
2ef2b01e A |
73 | return EFI_SUCCESS;\r |
74 | }\r | |
75 | \r | |
f659880b A |
76 | \r |
77 | /**\r | |
3402aac7 | 78 | This function enables interrupt processing by the processor.\r |
f659880b A |
79 | \r |
80 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
81 | \r | |
82 | @retval EFI_SUCCESS Interrupts are enabled on the processor.\r | |
83 | @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r | |
84 | \r | |
85 | **/\r | |
2ef2b01e A |
86 | EFI_STATUS\r |
87 | EFIAPI\r | |
88 | CpuEnableInterrupt (\r | |
89 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
90 | )\r | |
91 | {\r | |
d213712d | 92 | ArmEnableInterrupts ();\r |
8a4d81e6 | 93 | \r |
2ef2b01e A |
94 | return EFI_SUCCESS;\r |
95 | }\r | |
96 | \r | |
97 | \r | |
f659880b A |
98 | /**\r |
99 | This function disables interrupt processing by the processor.\r | |
100 | \r | |
101 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
102 | \r | |
103 | @retval EFI_SUCCESS Interrupts are disabled on the processor.\r | |
104 | @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r | |
105 | \r | |
106 | **/\r | |
2ef2b01e A |
107 | EFI_STATUS\r |
108 | EFIAPI\r | |
109 | CpuDisableInterrupt (\r | |
110 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
111 | )\r | |
112 | {\r | |
d213712d | 113 | ArmDisableInterrupts ();\r |
8a4d81e6 | 114 | \r |
2ef2b01e A |
115 | return EFI_SUCCESS;\r |
116 | }\r | |
117 | \r | |
f659880b A |
118 | \r |
119 | /**\r | |
3402aac7 RC |
120 | This function retrieves the processor's current interrupt state a returns it in\r |
121 | State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r | |
f659880b A |
122 | are currently disabled, then FALSE is returned.\r |
123 | \r | |
124 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
125 | @param State A pointer to the processor's current interrupt state. Set to TRUE if\r | |
126 | interrupts are enabled and FALSE if interrupts are disabled.\r | |
127 | \r | |
128 | @retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r | |
129 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
130 | \r | |
131 | **/\r | |
2ef2b01e A |
132 | EFI_STATUS\r |
133 | EFIAPI\r | |
134 | CpuGetInterruptState (\r | |
135 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
136 | OUT BOOLEAN *State\r | |
137 | )\r | |
138 | {\r | |
139 | if (State == NULL) {\r | |
140 | return EFI_INVALID_PARAMETER;\r | |
141 | }\r | |
142 | \r | |
e3aa7252 | 143 | *State = ArmGetInterruptState();\r |
2ef2b01e A |
144 | return EFI_SUCCESS;\r |
145 | }\r | |
146 | \r | |
f659880b A |
147 | \r |
148 | /**\r | |
149 | This function generates an INIT on the processor. If this function succeeds, then the\r | |
3402aac7 RC |
150 | processor will be reset, and control will not be returned to the caller. If InitType is\r |
151 | not supported by this processor, or the processor cannot programmatically generate an\r | |
152 | INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r | |
f659880b A |
153 | occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r |
154 | \r | |
155 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
156 | @param InitType The type of processor INIT to perform.\r | |
157 | \r | |
158 | @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r | |
159 | @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r | |
160 | by this processor.\r | |
161 | @retval EFI_DEVICE_ERROR The processor INIT failed.\r | |
162 | \r | |
163 | **/\r | |
2ef2b01e A |
164 | EFI_STATUS\r |
165 | EFIAPI\r | |
166 | CpuInit (\r | |
167 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
168 | IN EFI_CPU_INIT_TYPE InitType\r | |
169 | )\r | |
170 | {\r | |
171 | return EFI_UNSUPPORTED;\r | |
172 | }\r | |
173 | \r | |
174 | EFI_STATUS\r | |
175 | EFIAPI\r | |
176 | CpuRegisterInterruptHandler (\r | |
177 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
178 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
179 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
180 | )\r | |
181 | {\r | |
8a4d81e6 | 182 | return RegisterInterruptHandler (InterruptType, InterruptHandler);\r |
2ef2b01e A |
183 | }\r |
184 | \r | |
185 | EFI_STATUS\r | |
186 | EFIAPI\r | |
187 | CpuGetTimerValue (\r | |
188 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
189 | IN UINT32 TimerIndex,\r | |
190 | OUT UINT64 *TimerValue,\r | |
191 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
192 | )\r | |
193 | {\r | |
194 | return EFI_UNSUPPORTED;\r | |
195 | }\r | |
196 | \r | |
8513037f | 197 | /**\r |
198 | Callback function for idle events.\r | |
3402aac7 | 199 | \r |
8513037f | 200 | @param Event Event whose notification function is being invoked.\r |
201 | @param Context The pointer to the notification function's context,\r | |
202 | which is implementation-dependent.\r | |
203 | \r | |
204 | **/\r | |
205 | VOID\r | |
206 | EFIAPI\r | |
207 | IdleLoopEventCallback (\r | |
208 | IN EFI_EVENT Event,\r | |
209 | IN VOID *Context\r | |
210 | )\r | |
211 | {\r | |
212 | CpuSleep ();\r | |
213 | }\r | |
2ef2b01e A |
214 | \r |
215 | //\r | |
216 | // Globals used to initialize the protocol\r | |
217 | //\r | |
218 | EFI_HANDLE mCpuHandle = NULL;\r | |
219 | EFI_CPU_ARCH_PROTOCOL mCpu = {\r | |
220 | CpuFlushCpuDataCache,\r | |
221 | CpuEnableInterrupt,\r | |
222 | CpuDisableInterrupt,\r | |
223 | CpuGetInterruptState,\r | |
224 | CpuInit,\r | |
225 | CpuRegisterInterruptHandler,\r | |
226 | CpuGetTimerValue,\r | |
227 | CpuSetMemoryAttributes,\r | |
228 | 0, // NumberOfTimers\r | |
756a514a | 229 | 2048, // DmaBufferAlignment\r |
2ef2b01e A |
230 | };\r |
231 | \r | |
756a514a AB |
232 | STATIC\r |
233 | VOID\r | |
234 | InitializeDma (\r | |
235 | IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol\r | |
236 | )\r | |
237 | {\r | |
238 | CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r | |
239 | }\r | |
240 | \r | |
2ef2b01e A |
241 | EFI_STATUS\r |
242 | CpuDxeInitialize (\r | |
243 | IN EFI_HANDLE ImageHandle,\r | |
244 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
245 | )\r | |
f659880b A |
246 | {\r |
247 | EFI_STATUS Status;\r | |
8513037f | 248 | EFI_EVENT IdleLoopEvent;\r |
f659880b | 249 | \r |
3402aac7 RC |
250 | InitializeExceptions (&mCpu);\r |
251 | \r | |
756a514a AB |
252 | InitializeDma (&mCpu);\r |
253 | \r | |
f659880b | 254 | Status = gBS->InstallMultipleProtocolInterfaces (\r |
3402aac7 RC |
255 | &mCpuHandle,\r |
256 | &gEfiCpuArchProtocolGuid, &mCpu,\r | |
f659880b A |
257 | NULL\r |
258 | );\r | |
3402aac7 | 259 | \r |
f659880b A |
260 | //\r |
261 | // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r | |
262 | // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r | |
263 | // after the protocol is installed\r | |
264 | //\r | |
3b44bb55 | 265 | mIsFlushingGCD = TRUE;\r |
f659880b | 266 | SyncCacheConfig (&mCpu);\r |
3b44bb55 | 267 | mIsFlushingGCD = FALSE;\r |
3402aac7 | 268 | \r |
44788bae | 269 | // If the platform is a MPCore system then install the Configuration Table describing the\r |
270 | // secondary core states\r | |
886f97c8 | 271 | if (ArmIsMpCore()) {\r |
44788bae | 272 | PublishArmProcessorTable();\r |
273 | }\r | |
274 | \r | |
8513037f | 275 | //\r |
276 | // Setup a callback for idle events\r | |
277 | //\r | |
278 | Status = gBS->CreateEventEx (\r | |
279 | EVT_NOTIFY_SIGNAL,\r | |
280 | TPL_NOTIFY,\r | |
281 | IdleLoopEventCallback,\r | |
282 | NULL,\r | |
283 | &gIdleLoopEventGuid,\r | |
284 | &IdleLoopEvent\r | |
285 | );\r | |
286 | ASSERT_EFI_ERROR (Status);\r | |
287 | \r | |
f659880b | 288 | return Status;\r |
2ef2b01e | 289 | }\r |