ArmPkg/Drivers/CpuDxe/CpuDxe.c

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011, ARM Limited. All rights reserved.
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include "CpuDxe.h"
  17
  18 #include <Guid/IdleLoopEvent.h>
  19
  20 BOOLEAN                   mIsFlushingGCD;
  21
  22 /**
  23   This function flushes the range of addresses from Start to Start+Length
  24   from the processor's data cache. If Start is not aligned to a cache line
  25   boundary, then the bytes before Start to the preceding cache line boundary
  26   are also flushed. If Start+Length is not aligned to a cache line boundary,
  27   then the bytes past Start+Length to the end of the next cache line boundary
  28   are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
  29   supported. If the data cache is fully coherent with all DMA operations, then
  30   this function can just return EFI_SUCCESS. If the processor does not support
  31   flushing a range of the data cache, then the entire data cache can be flushed.
  32
  33   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
  34   @param  Start            The beginning physical address to flush from the processor's data
  35                            cache.
  36   @param  Length           The number of bytes to flush from the processor's data cache. This
  37                            function may flush more bytes than Length specifies depending upon
  38                            the granularity of the flush operation that the processor supports.
  39   @param  FlushType        Specifies the type of flush operation to perform.
  40
  41   @retval EFI_SUCCESS           The address range from Start to Start+Length was flushed from
  42                                 the processor's data cache.
  43   @retval EFI_UNSUPPORTED       The processor does not support the cache flush type specified
  44                                 by FlushType.
  45   @retval EFI_DEVICE_ERROR      The address range from Start to Start+Length could not be flushed
  46                                 from the processor's data cache.
  47
  48 **/
  49 EFI_STATUS
  50 EFIAPI
  51 CpuFlushCpuDataCache (
  52   IN EFI_CPU_ARCH_PROTOCOL           *This,
  53   IN EFI_PHYSICAL_ADDRESS            Start,
  54   IN UINT64                          Length,
  55   IN EFI_CPU_FLUSH_TYPE              FlushType
  56   )
  57 {
  58
  59   switch (FlushType) {
  60     case EfiCpuFlushTypeWriteBack:
  61       WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
  62       break;
  63     case EfiCpuFlushTypeInvalidate:
  64       InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
  65       break;
  66     case EfiCpuFlushTypeWriteBackInvalidate:
  67       WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
  68       break;
  69     default:
  70       return EFI_INVALID_PARAMETER;
  71   }
  72
  73   return EFI_SUCCESS;
  74 }
  75
  76
  77 /**
  78   This function enables interrupt processing by the processor.
  79
  80   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
  81
  82   @retval EFI_SUCCESS           Interrupts are enabled on the processor.
  83   @retval EFI_DEVICE_ERROR      Interrupts could not be enabled on the processor.
  84
  85 **/
  86 EFI_STATUS
  87 EFIAPI
  88 CpuEnableInterrupt (
  89   IN EFI_CPU_ARCH_PROTOCOL          *This
  90   )
  91 {
  92   ArmEnableInterrupts ();
  93
  94   return EFI_SUCCESS;
  95 }
  96
  97
  98 /**
  99   This function disables interrupt processing by the processor.
 100
 101   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 102
 103   @retval EFI_SUCCESS           Interrupts are disabled on the processor.
 104   @retval EFI_DEVICE_ERROR      Interrupts could not be disabled on the processor.
 105
 106 **/
 107 EFI_STATUS
 108 EFIAPI
 109 CpuDisableInterrupt (
 110   IN EFI_CPU_ARCH_PROTOCOL          *This
 111   )
 112 {
 113   ArmDisableInterrupts ();
 114
 115   return EFI_SUCCESS;
 116 }
 117
 118
 119 /**
 120   This function retrieves the processor's current interrupt state a returns it in
 121   State. If interrupts are currently enabled, then TRUE is returned. If interrupts
 122   are currently disabled, then FALSE is returned.
 123
 124   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 125   @param  State            A pointer to the processor's current interrupt state. Set to TRUE if
 126                            interrupts are enabled and FALSE if interrupts are disabled.
 127
 128   @retval EFI_SUCCESS           The processor's current interrupt state was returned in State.
 129   @retval EFI_INVALID_PARAMETER State is NULL.
 130
 131 **/
 132 EFI_STATUS
 133 EFIAPI
 134 CpuGetInterruptState (
 135   IN  EFI_CPU_ARCH_PROTOCOL         *This,
 136   OUT BOOLEAN                       *State
 137   )
 138 {
 139   if (State == NULL) {
 140     return EFI_INVALID_PARAMETER;
 141   }
 142
 143   *State = ArmGetInterruptState();
 144   return EFI_SUCCESS;
 145 }
 146
 147
 148 /**
 149   This function generates an INIT on the processor. If this function succeeds, then the
 150   processor will be reset, and control will not be returned to the caller. If InitType is
 151   not supported by this processor, or the processor cannot programmatically generate an
 152   INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
 153   occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
 154
 155   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 156   @param  InitType         The type of processor INIT to perform.
 157
 158   @retval EFI_SUCCESS           The processor INIT was performed. This return code should never be seen.
 159   @retval EFI_UNSUPPORTED       The processor INIT operation specified by InitType is not supported
 160                                 by this processor.
 161   @retval EFI_DEVICE_ERROR      The processor INIT failed.
 162
 163 **/
 164 EFI_STATUS
 165 EFIAPI
 166 CpuInit (
 167   IN EFI_CPU_ARCH_PROTOCOL           *This,
 168   IN EFI_CPU_INIT_TYPE               InitType
 169   )
 170 {
 171   return EFI_UNSUPPORTED;
 172 }
 173
 174 EFI_STATUS
 175 EFIAPI
 176 CpuRegisterInterruptHandler (
 177   IN EFI_CPU_ARCH_PROTOCOL          *This,
 178   IN EFI_EXCEPTION_TYPE             InterruptType,
 179   IN EFI_CPU_INTERRUPT_HANDLER      InterruptHandler
 180   )
 181 {
 182   return RegisterInterruptHandler (InterruptType, InterruptHandler);
 183 }
 184
 185 EFI_STATUS
 186 EFIAPI
 187 CpuGetTimerValue (
 188   IN  EFI_CPU_ARCH_PROTOCOL          *This,
 189   IN  UINT32                         TimerIndex,
 190   OUT UINT64                         *TimerValue,
 191   OUT UINT64                         *TimerPeriod   OPTIONAL
 192   )
 193 {
 194   return EFI_UNSUPPORTED;
 195 }
 196
 197 /**
 198   Callback function for idle events.
 199
 200   @param  Event                 Event whose notification function is being invoked.
 201   @param  Context               The pointer to the notification function's context,
 202                                 which is implementation-dependent.
 203
 204 **/
 205 VOID
 206 EFIAPI
 207 IdleLoopEventCallback (
 208   IN EFI_EVENT                Event,
 209   IN VOID                     *Context
 210   )
 211 {
 212   CpuSleep ();
 213 }
 214
 215 //
 216 // Globals used to initialize the protocol
 217 //
 218 EFI_HANDLE            mCpuHandle = NULL;
 219 EFI_CPU_ARCH_PROTOCOL mCpu = {
 220   CpuFlushCpuDataCache,
 221   CpuEnableInterrupt,
 222   CpuDisableInterrupt,
 223   CpuGetInterruptState,
 224   CpuInit,
 225   CpuRegisterInterruptHandler,
 226   CpuGetTimerValue,
 227   CpuSetMemoryAttributes,
 228   0,          // NumberOfTimers
 229   2048,       // DmaBufferAlignment
 230 };
 231
 232 STATIC
 233 VOID
 234 InitializeDma (
 235   IN OUT  EFI_CPU_ARCH_PROTOCOL   *CpuArchProtocol
 236   )
 237 {
 238   CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();
 239 }
 240
 241 EFI_STATUS
 242 CpuDxeInitialize (
 243   IN EFI_HANDLE         ImageHandle,
 244   IN EFI_SYSTEM_TABLE   *SystemTable
 245   )
 246 {
 247   EFI_STATUS  Status;
 248   EFI_EVENT    IdleLoopEvent;
 249
 250   InitializeExceptions (&mCpu);
 251
 252   InitializeDma (&mCpu);
 253
 254   Status = gBS->InstallMultipleProtocolInterfaces (
 255                 &mCpuHandle,
 256                 &gEfiCpuArchProtocolGuid,           &mCpu,
 257                 NULL
 258                 );
 259
 260   //
 261   // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
 262   // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
 263   // after the protocol is installed
 264   //
 265   mIsFlushingGCD = TRUE;
 266   SyncCacheConfig (&mCpu);
 267   mIsFlushingGCD = FALSE;
 268
 269   // If the platform is a MPCore system then install the Configuration Table describing the
 270   // secondary core states
 271   if (ArmIsMpCore()) {
 272     PublishArmProcessorTable();
 273   }
 274
 275   //
 276   // Setup a callback for idle events
 277   //
 278   Status = gBS->CreateEventEx (
 279                   EVT_NOTIFY_SIGNAL,
 280                   TPL_NOTIFY,
 281                   IdleLoopEventCallback,
 282                   NULL,
 283                   &gIdleLoopEventGuid,
 284                   &IdleLoopEvent
 285                   );
 286   ASSERT_EFI_ERROR (Status);
 287
 288   return Status;
 289 }