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25402f5d HL |
1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
b7dd4dbd | 4 | Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r |
25402f5d HL |
5 | \r |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __AARCH64_H__\r | |
17 | #define __AARCH64_H__\r | |
18 | \r | |
19 | #include <Chipset/AArch64Mmu.h>\r | |
20 | #include <Chipset/ArmArchTimer.h>\r | |
21 | \r | |
22 | // ARM Interrupt ID in Exception Table\r | |
23 | #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ\r | |
24 | \r | |
25 | // CPACR - Coprocessor Access Control Register definitions\r | |
26 | #define CPACR_TTA_EN (1UL << 28)\r | |
27 | #define CPACR_FPEN_EL1 (1UL << 20)\r | |
28 | #define CPACR_FPEN_FULL (3UL << 20)\r | |
29 | #define CPACR_CP_FULL_ACCESS 0x300000\r | |
30 | \r | |
31 | // Coprocessor Trap Register (CPTR)\r | |
32 | #define AARCH64_CPTR_TFP (1 << 10)\r | |
33 | \r | |
34 | // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions\r | |
35 | #define AARCH64_PFR0_FP (0xF << 16)\r | |
27331bff | 36 | #define AARCH64_PFR0_GIC (0xF << 24)\r |
25402f5d | 37 | \r |
25402f5d HL |
38 | // SCR - Secure Configuration Register definitions\r |
39 | #define SCR_NS (1 << 0)\r | |
40 | #define SCR_IRQ (1 << 1)\r | |
41 | #define SCR_FIQ (1 << 2)\r | |
42 | #define SCR_EA (1 << 3)\r | |
43 | #define SCR_FW (1 << 4)\r | |
44 | #define SCR_AW (1 << 5)\r | |
45 | \r | |
46 | // MIDR - Main ID Register definitions\r | |
47 | #define ARM_CPU_TYPE_MASK 0xFFF\r | |
48 | #define ARM_CPU_TYPE_AEMv8 0xD0F\r | |
b7dd4dbd OM |
49 | #define ARM_CPU_TYPE_A53 0xD03\r |
50 | #define ARM_CPU_TYPE_A57 0xD07\r | |
25402f5d HL |
51 | #define ARM_CPU_TYPE_A15 0xC0F\r |
52 | #define ARM_CPU_TYPE_A9 0xC09\r | |
53 | #define ARM_CPU_TYPE_A5 0xC05\r | |
54 | \r | |
b7dd4dbd OM |
55 | #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r |
56 | #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r | |
57 | \r | |
25402f5d HL |
58 | // Hypervisor Configuration Register\r |
59 | #define ARM_HCR_FMO BIT3\r | |
60 | #define ARM_HCR_IMO BIT4\r | |
61 | #define ARM_HCR_AMO BIT5\r | |
62 | #define ARM_HCR_TGE BIT27\r | |
63 | \r | |
64 | // AArch64 Exception Level\r | |
65 | #define AARCH64_EL3 0xC\r | |
66 | #define AARCH64_EL2 0x8\r | |
67 | #define AARCH64_EL1 0x4\r | |
68 | \r | |
7e119c67 OM |
69 | // Saved Program Status Register definitions\r |
70 | #define SPSR_A BIT8\r | |
71 | #define SPSR_I BIT7\r | |
72 | #define SPSR_F BIT6\r | |
73 | \r | |
74 | #define SPSR_AARCH32 BIT4\r | |
75 | \r | |
76 | #define SPSR_AARCH32_MODE_USER 0x0\r | |
77 | #define SPSR_AARCH32_MODE_FIQ 0x1\r | |
78 | #define SPSR_AARCH32_MODE_IRQ 0x2\r | |
79 | #define SPSR_AARCH32_MODE_SVC 0x3\r | |
80 | #define SPSR_AARCH32_MODE_ABORT 0x7\r | |
81 | #define SPSR_AARCH32_MODE_UNDEF 0xB\r | |
82 | #define SPSR_AARCH32_MODE_SYS 0xF\r | |
83 | \r | |
84 | // Counter-timer Hypervisor Control register definitions\r | |
85 | #define CNTHCTL_EL2_EL1PCTEN BIT0\r | |
86 | #define CNTHCTL_EL2_EL1PCEN BIT1\r | |
87 | \r | |
25402f5d HL |
88 | #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)\r |
89 | \r | |
90 | VOID\r | |
91 | EFIAPI\r | |
92 | ArmEnableSWPInstruction (\r | |
93 | VOID\r | |
94 | );\r | |
95 | \r | |
96 | UINTN\r | |
97 | EFIAPI\r | |
98 | ArmReadCbar (\r | |
99 | VOID\r | |
100 | );\r | |
101 | \r | |
102 | UINTN\r | |
103 | EFIAPI\r | |
104 | ArmReadTpidrurw (\r | |
105 | VOID\r | |
106 | );\r | |
107 | \r | |
108 | VOID\r | |
109 | EFIAPI\r | |
110 | ArmWriteTpidrurw (\r | |
111 | UINTN Value\r | |
112 | );\r | |
113 | \r | |
25402f5d HL |
114 | UINTN\r |
115 | EFIAPI\r | |
116 | ArmGetTCR (\r | |
117 | VOID\r | |
118 | );\r | |
119 | \r | |
120 | VOID\r | |
121 | EFIAPI\r | |
122 | ArmSetTCR (\r | |
123 | UINTN Value\r | |
124 | );\r | |
125 | \r | |
126 | UINTN\r | |
127 | EFIAPI\r | |
128 | ArmGetMAIR (\r | |
129 | VOID\r | |
130 | );\r | |
131 | \r | |
132 | VOID\r | |
133 | EFIAPI\r | |
134 | ArmSetMAIR (\r | |
135 | UINTN Value\r | |
136 | );\r | |
137 | \r | |
138 | VOID\r | |
139 | EFIAPI\r | |
140 | ArmDisableAlignmentCheck (\r | |
141 | VOID\r | |
142 | );\r | |
143 | \r | |
25402f5d HL |
144 | VOID\r |
145 | EFIAPI\r | |
146 | ArmEnableAlignmentCheck (\r | |
147 | VOID\r | |
148 | );\r | |
149 | \r | |
150 | VOID\r | |
151 | EFIAPI\r | |
152 | ArmDisableAllExceptions (\r | |
153 | VOID\r | |
154 | );\r | |
155 | \r | |
156 | VOID\r | |
157 | ArmWriteHcr (\r | |
158 | IN UINTN Hcr\r | |
159 | );\r | |
160 | \r | |
161 | UINTN\r | |
162 | ArmReadCurrentEL (\r | |
163 | VOID\r | |
164 | );\r | |
165 | \r | |
166 | UINT64\r | |
167 | PageAttributeToGcdAttribute (\r | |
168 | IN UINT64 PageAttributes\r | |
169 | );\r | |
170 | \r | |
171 | UINT64\r | |
172 | GcdAttributeToPageAttribute (\r | |
173 | IN UINT64 GcdAttributes\r | |
174 | );\r | |
175 | \r | |
d6dc67ba OM |
176 | UINTN\r |
177 | ArmWriteCptr (\r | |
178 | IN UINT64 Cptr\r | |
179 | );\r | |
180 | \r | |
25402f5d | 181 | #endif // __AARCH64_H__\r |