projects / mirror_edk2.git / blame
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|---|---|---|
| 25402f5d HL |
1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
| b7dd4dbd | 4 | Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r |
| 25402f5d HL |
5 | \r |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #ifndef __AARCH64_H__\r | |
| 17 | #define __AARCH64_H__\r | |
| 18 | \r | |
| 19 | #include <Chipset/AArch64Mmu.h>\r | |
| 20 | #include <Chipset/ArmArchTimer.h>\r | |
| 21 | \r | |
| 22 | // ARM Interrupt ID in Exception Table\r | |
| 23 | #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ\r | |
| 24 | \r | |
| 25 | // CPACR - Coprocessor Access Control Register definitions\r | |
| 26 | #define CPACR_TTA_EN (1UL << 28)\r | |
| 27 | #define CPACR_FPEN_EL1 (1UL << 20)\r | |
| 28 | #define CPACR_FPEN_FULL (3UL << 20)\r | |
| 29 | #define CPACR_CP_FULL_ACCESS 0x300000\r | |
| 30 | \r | |
| 31 | // Coprocessor Trap Register (CPTR)\r | |
| 32 | #define AARCH64_CPTR_TFP (1 << 10)\r | |
| 33 | \r | |
| 34 | // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions\r | |
| 35 | #define AARCH64_PFR0_FP (0xF << 16)\r | |
| 36 | \r | |
| 25402f5d HL |
37 | // SCR - Secure Configuration Register definitions\r |
| 38 | #define SCR_NS (1 << 0)\r | |
| 39 | #define SCR_IRQ (1 << 1)\r | |
| 40 | #define SCR_FIQ (1 << 2)\r | |
| 41 | #define SCR_EA (1 << 3)\r | |
| 42 | #define SCR_FW (1 << 4)\r | |
| 43 | #define SCR_AW (1 << 5)\r | |
| 44 | \r | |
| 45 | // MIDR - Main ID Register definitions\r | |
| 46 | #define ARM_CPU_TYPE_MASK 0xFFF\r | |
| 47 | #define ARM_CPU_TYPE_AEMv8 0xD0F\r | |
| b7dd4dbd OM |
48 | #define ARM_CPU_TYPE_A53 0xD03\r |
| 49 | #define ARM_CPU_TYPE_A57 0xD07\r | |
| 25402f5d HL |
50 | #define ARM_CPU_TYPE_A15 0xC0F\r |
| 51 | #define ARM_CPU_TYPE_A9 0xC09\r | |
| 52 | #define ARM_CPU_TYPE_A5 0xC05\r | |
| 53 | \r | |
| b7dd4dbd OM |
54 | #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r |
| 55 | #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r | |
| 56 | \r | |
| 25402f5d HL |
57 | // Hypervisor Configuration Register\r |
| 58 | #define ARM_HCR_FMO BIT3\r | |
| 59 | #define ARM_HCR_IMO BIT4\r | |
| 60 | #define ARM_HCR_AMO BIT5\r | |
| 61 | #define ARM_HCR_TGE BIT27\r | |
| 62 | \r | |
| 63 | // AArch64 Exception Level\r | |
| 64 | #define AARCH64_EL3 0xC\r | |
| 65 | #define AARCH64_EL2 0x8\r | |
| 66 | #define AARCH64_EL1 0x4\r | |
| 67 | \r | |
| 68 | #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)\r | |
| 69 | \r | |
| 70 | VOID\r | |
| 71 | EFIAPI\r | |
| 72 | ArmEnableSWPInstruction (\r | |
| 73 | VOID\r | |
| 74 | );\r | |
| 75 | \r | |
| 76 | UINTN\r | |
| 77 | EFIAPI\r | |
| 78 | ArmReadCbar (\r | |
| 79 | VOID\r | |
| 80 | );\r | |
| 81 | \r | |
| 82 | UINTN\r | |
| 83 | EFIAPI\r | |
| 84 | ArmReadTpidrurw (\r | |
| 85 | VOID\r | |
| 86 | );\r | |
| 87 | \r | |
| 88 | VOID\r | |
| 89 | EFIAPI\r | |
| 90 | ArmWriteTpidrurw (\r | |
| 91 | UINTN Value\r | |
| 92 | );\r | |
| 93 | \r | |
| 25402f5d HL |
94 | UINTN\r |
| 95 | EFIAPI\r | |
| 96 | ArmGetTCR (\r | |
| 97 | VOID\r | |
| 98 | );\r | |
| 99 | \r | |
| 100 | VOID\r | |
| 101 | EFIAPI\r | |
| 102 | ArmSetTCR (\r | |
| 103 | UINTN Value\r | |
| 104 | );\r | |
| 105 | \r | |
| 106 | UINTN\r | |
| 107 | EFIAPI\r | |
| 108 | ArmGetMAIR (\r | |
| 109 | VOID\r | |
| 110 | );\r | |
| 111 | \r | |
| 112 | VOID\r | |
| 113 | EFIAPI\r | |
| 114 | ArmSetMAIR (\r | |
| 115 | UINTN Value\r | |
| 116 | );\r | |
| 117 | \r | |
| 118 | VOID\r | |
| 119 | EFIAPI\r | |
| 120 | ArmDisableAlignmentCheck (\r | |
| 121 | VOID\r | |
| 122 | );\r | |
| 123 | \r | |
| 25402f5d HL |
124 | VOID\r |
| 125 | EFIAPI\r | |
| 126 | ArmEnableAlignmentCheck (\r | |
| 127 | VOID\r | |
| 128 | );\r | |
| 129 | \r | |
| 130 | VOID\r | |
| 131 | EFIAPI\r | |
| 132 | ArmDisableAllExceptions (\r | |
| 133 | VOID\r | |
| 134 | );\r | |
| 135 | \r | |
| 136 | VOID\r | |
| 137 | ArmWriteHcr (\r | |
| 138 | IN UINTN Hcr\r | |
| 139 | );\r | |
| 140 | \r | |
| 141 | UINTN\r | |
| 142 | ArmReadCurrentEL (\r | |
| 143 | VOID\r | |
| 144 | );\r | |
| 145 | \r | |
| 146 | UINT64\r | |
| 147 | PageAttributeToGcdAttribute (\r | |
| 148 | IN UINT64 PageAttributes\r | |
| 149 | );\r | |
| 150 | \r | |
| 151 | UINT64\r | |
| 152 | GcdAttributeToPageAttribute (\r | |
| 153 | IN UINT64 GcdAttributes\r | |
| 154 | );\r | |
| 155 | \r | |
| d6dc67ba OM |
156 | UINTN\r |
| 157 | ArmWriteCptr (\r | |
| 158 | IN UINT64 Cptr\r | |
| 159 | );\r | |
| 160 | \r | |
| 25402f5d | 161 | #endif // __AARCH64_H__\r |