ArmPkg/Chipset: Added ARMv8 CPU's PartNum

PartNum is the field of MIDR that returns the CPU name.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15395 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
index e0115885092c9b3f5ca5e906d966adcd67ee6829..3e5b55bfd7345dedd7fcd0bd5362ad0b4a87694e 100644 (file)
--- a/ArmPkg/Include/Chipset/AArch64.h
+++ b/ArmPkg/Include/Chipset/AArch64.h
@@ -1,7 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -45,10 +45,15 @@
 // MIDR - Main ID Register definitions\r
 #define ARM_CPU_TYPE_MASK       0xFFF\r
 #define ARM_CPU_TYPE_AEMv8      0xD0F\r
+#define ARM_CPU_TYPE_A53        0xD03\r
+#define ARM_CPU_TYPE_A57        0xD07\r
 #define ARM_CPU_TYPE_A15        0xC0F\r
 #define ARM_CPU_TYPE_A9         0xC09\r
 #define ARM_CPU_TYPE_A5         0xC05\r
 \r
+#define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )\r
+#define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
+\r
 // Hypervisor Configuration Register\r
 #define ARM_HCR_FMO                            BIT3\r
 #define ARM_HCR_IMO                            BIT4\r
@@ -116,7 +121,6 @@ ArmDisableAlignmentCheck (
   VOID\r
   );\r
 \r
-\r
 VOID\r
 EFIAPI\r
 ArmEnableAlignmentCheck (\r

diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
index 3fcc4264fccf66a9fd1f98d346e86f0b6dcb8ec7..345554eb28a7063631593fd970fcfa303ea10235 100644 (file)
--- a/ArmPkg/Include/Chipset/ArmV7.h
+++ b/ArmPkg/Include/Chipset/ArmV7.h
@@ -1,7 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>\r
+  Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -71,10 +71,16 @@
 \r
 // MIDR - Main ID Register definitions\r
 #define ARM_CPU_TYPE_MASK       0xFFF\r
+#define ARM_CPU_TYPE_AEMv8      0xD0F\r
+#define ARM_CPU_TYPE_A53        0xD03\r
+#define ARM_CPU_TYPE_A57        0xD07\r
 #define ARM_CPU_TYPE_A15        0xC0F\r
 #define ARM_CPU_TYPE_A9         0xC09\r
 #define ARM_CPU_TYPE_A5         0xC05\r
 \r
+#define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )\r
+#define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
+\r
 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)\r
 \r
 VOID\r