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55a0d64b | 1 | /** @file\r |
2 | *\r | |
919697ae | 3 | * Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r |
55a0d64b | 4 | *\r |
1cb13673 OM |
5 | * This program and the accompanying materials\r |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
55a0d64b | 12 | *\r |
13 | **/\r | |
14 | \r | |
017baa1c OM |
15 | #ifndef __ARMGIC_H\r |
16 | #define __ARMGIC_H\r | |
55a0d64b | 17 | \r |
8d13298b | 18 | #include <Library/ArmGicArchLib.h>\r |
55a0d64b | 19 | \r |
20 | //\r | |
21 | // GIC Distributor\r | |
22 | //\r | |
23 | #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r | |
24 | #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r | |
25 | #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r | |
26 | \r | |
919697ae | 27 | // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r |
55a0d64b | 28 | #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r |
29 | #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r | |
30 | #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r | |
31 | #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r | |
32 | #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r | |
33 | #define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r | |
34 | \r | |
919697ae | 35 | // Each reg base below repeats for Number of interrupts / 4\r |
55a0d64b | 36 | #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r |
37 | \r | |
919697ae | 38 | // Each reg base below repeats for Number of interrupts\r |
55a0d64b | 39 | #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r |
40 | #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r | |
41 | \r | |
42 | #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r | |
43 | \r | |
44 | // just one of these\r | |
45 | #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r | |
46 | \r | |
919697ae OM |
47 | // GICv3 specific registers\r |
48 | #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r | |
49 | \r | |
c7fefb69 AB |
50 | // GICD_CTLR bits\r |
51 | #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)\r | |
52 | #define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)\r | |
f6d46e29 | 53 | \r |
919697ae OM |
54 | //\r |
55 | // GIC Redistributor\r | |
56 | //\r | |
57 | \r | |
58 | #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r | |
59 | #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r | |
60 | \r | |
61 | // GIC Redistributor Control frame\r | |
62 | #define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r | |
63 | \r | |
64 | // GIC SGI & PPI Redistributor frame\r | |
65 | #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r | |
66 | #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r | |
67 | \r | |
55a0d64b | 68 | //\r |
69 | // GIC Cpu interface\r | |
70 | //\r | |
71 | #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r | |
72 | #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r | |
73 | #define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r | |
74 | #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r | |
75 | #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r | |
76 | #define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r | |
77 | #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r | |
78 | #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r | |
e700a1fc | 79 | #define ARM_GIC_ICCIIDR 0xFC // Identification Register\r |
55a0d64b | 80 | \r |
81 | #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r | |
82 | #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r | |
83 | #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r | |
84 | \r | |
85 | // Bit-masks to configure the CPU Interface Control register\r | |
86 | #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r | |
87 | #define ARM_GIC_ICCICR_ENABLE_NS 0x02\r | |
88 | #define ARM_GIC_ICCICR_ACK_CTL 0x04\r | |
89 | #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r | |
90 | #define ARM_GIC_ICCICR_USE_SBPR 0x10\r | |
91 | \r | |
1cb13673 | 92 | // Bit Mask for GICC_IIDR\r |
e700a1fc OM |
93 | #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r |
94 | #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r | |
95 | #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r | |
96 | #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r | |
55a0d64b | 97 | \r |
5f81082e OM |
98 | // Bit Mask for\r |
99 | #define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r | |
100 | \r | |
e700a1fc OM |
101 | UINTN\r |
102 | EFIAPI\r | |
103 | ArmGicGetInterfaceIdentification (\r | |
104 | IN INTN GicInterruptInterfaceBase\r | |
105 | );\r | |
106 | \r | |
55a0d64b | 107 | //\r |
92534106 | 108 | // GIC Secure interfaces\r |
55a0d64b | 109 | //\r |
110 | VOID\r | |
111 | EFIAPI\r | |
112 | ArmGicSetupNonSecure (\r | |
5e773144 | 113 | IN UINTN MpId,\r |
55a0d64b | 114 | IN INTN GicDistributorBase,\r |
115 | IN INTN GicInterruptInterfaceBase\r | |
116 | );\r | |
117 | \r | |
92534106 | 118 | VOID\r |
119 | EFIAPI\r | |
120 | ArmGicSetSecureInterrupts (\r | |
121 | IN UINTN GicDistributorBase,\r | |
122 | IN UINTN* GicSecureInterruptMask,\r | |
123 | IN UINTN GicSecureInterruptMaskSize\r | |
124 | );\r | |
125 | \r | |
55a0d64b | 126 | VOID\r |
127 | EFIAPI\r | |
128 | ArmGicEnableInterruptInterface (\r | |
129 | IN INTN GicInterruptInterfaceBase\r | |
130 | );\r | |
131 | \r | |
9736c297 | 132 | VOID\r |
133 | EFIAPI\r | |
134 | ArmGicDisableInterruptInterface (\r | |
135 | IN INTN GicInterruptInterfaceBase\r | |
136 | );\r | |
137 | \r | |
55a0d64b | 138 | VOID\r |
139 | EFIAPI\r | |
140 | ArmGicEnableDistributor (\r | |
141 | IN INTN GicDistributorBase\r | |
142 | );\r | |
143 | \r | |
e700a1fc OM |
144 | VOID\r |
145 | EFIAPI\r | |
146 | ArmGicDisableDistributor (\r | |
147 | IN INTN GicDistributorBase\r | |
148 | );\r | |
149 | \r | |
e9f7c58f | 150 | UINTN\r |
151 | EFIAPI\r | |
152 | ArmGicGetMaxNumInterrupts (\r | |
153 | IN INTN GicDistributorBase\r | |
154 | );\r | |
155 | \r | |
55a0d64b | 156 | VOID\r |
157 | EFIAPI\r | |
158 | ArmGicSendSgiTo (\r | |
159 | IN INTN GicDistributorBase,\r | |
160 | IN INTN TargetListFilter,\r | |
4c19ece3 | 161 | IN INTN CPUTargetList,\r |
162 | IN INTN SgiId\r | |
55a0d64b | 163 | );\r |
164 | \r | |
1b0ac0de OM |
165 | /*\r |
166 | * Acknowledge and return the value of the Interrupt Acknowledge Register\r | |
167 | *\r | |
168 | * InterruptId is returned separately from the register value because in\r | |
169 | * the GICv2 the register value contains the CpuId and InterruptId while\r | |
170 | * in the GICv3 the register value is only the InterruptId.\r | |
171 | *\r | |
172 | * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r | |
173 | * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r | |
174 | *\r | |
175 | * @retval value returned by the Interrupt Acknowledge Register\r | |
176 | *\r | |
177 | */\r | |
2ca815a4 | 178 | UINTN\r |
55a0d64b | 179 | EFIAPI\r |
315649cd | 180 | ArmGicAcknowledgeInterrupt (\r |
1b0ac0de OM |
181 | IN UINTN GicInterruptInterfaceBase,\r |
182 | OUT UINTN *InterruptId\r | |
55a0d64b | 183 | );\r |
184 | \r | |
d80401a1 OM |
185 | VOID\r |
186 | EFIAPI\r | |
187 | ArmGicEndOfInterrupt (\r | |
188 | IN UINTN GicInterruptInterfaceBase,\r | |
189 | IN UINTN Source\r | |
190 | );\r | |
191 | \r | |
55a0d64b | 192 | UINTN\r |
193 | EFIAPI\r | |
194 | ArmGicSetPriorityMask (\r | |
195 | IN INTN GicInterruptInterfaceBase,\r | |
196 | IN INTN PriorityMask\r | |
197 | );\r | |
198 | \r | |
e700a1fc OM |
199 | VOID\r |
200 | EFIAPI\r | |
201 | ArmGicEnableInterrupt (\r | |
202 | IN UINTN GicDistributorBase,\r | |
41fb5d46 | 203 | IN UINTN GicRedistributorBase,\r |
e700a1fc OM |
204 | IN UINTN Source\r |
205 | );\r | |
206 | \r | |
207 | VOID\r | |
208 | EFIAPI\r | |
209 | ArmGicDisableInterrupt (\r | |
210 | IN UINTN GicDistributorBase,\r | |
41fb5d46 | 211 | IN UINTN GicRedistributorBase,\r |
e700a1fc OM |
212 | IN UINTN Source\r |
213 | );\r | |
214 | \r | |
215 | BOOLEAN\r | |
216 | EFIAPI\r | |
217 | ArmGicIsInterruptEnabled (\r | |
218 | IN UINTN GicDistributorBase,\r | |
41fb5d46 | 219 | IN UINTN GicRedistributorBase,\r |
e700a1fc OM |
220 | IN UINTN Source\r |
221 | );\r | |
222 | \r | |
bce29e30 AB |
223 | //\r |
224 | // GIC revision 2 specific declarations\r | |
225 | //\r | |
226 | \r | |
227 | // Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)\r | |
228 | #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r | |
229 | \r | |
230 | VOID\r | |
231 | EFIAPI\r | |
232 | ArmGicV2SetupNonSecure (\r | |
233 | IN UINTN MpId,\r | |
234 | IN INTN GicDistributorBase,\r | |
235 | IN INTN GicInterruptInterfaceBase\r | |
236 | );\r | |
237 | \r | |
238 | VOID\r | |
239 | EFIAPI\r | |
240 | ArmGicV2EnableInterruptInterface (\r | |
241 | IN INTN GicInterruptInterfaceBase\r | |
242 | );\r | |
243 | \r | |
244 | VOID\r | |
245 | EFIAPI\r | |
246 | ArmGicV2DisableInterruptInterface (\r | |
247 | IN INTN GicInterruptInterfaceBase\r | |
248 | );\r | |
249 | \r | |
250 | UINTN\r | |
251 | EFIAPI\r | |
252 | ArmGicV2AcknowledgeInterrupt (\r | |
253 | IN UINTN GicInterruptInterfaceBase\r | |
254 | );\r | |
255 | \r | |
256 | VOID\r | |
257 | EFIAPI\r | |
258 | ArmGicV2EndOfInterrupt (\r | |
259 | IN UINTN GicInterruptInterfaceBase,\r | |
260 | IN UINTN Source\r | |
261 | );\r | |
262 | \r | |
263 | //\r | |
264 | // GIC revision 3 specific declarations\r | |
265 | //\r | |
266 | \r | |
267 | #define ICC_SRE_EL2_SRE (1 << 0)\r | |
268 | \r | |
269 | #define ARM_GICD_IROUTER_IRM BIT31\r | |
270 | \r | |
271 | UINT32\r | |
272 | EFIAPI\r | |
273 | ArmGicV3GetControlSystemRegisterEnable (\r | |
274 | VOID\r | |
275 | );\r | |
276 | \r | |
277 | VOID\r | |
278 | EFIAPI\r | |
279 | ArmGicV3SetControlSystemRegisterEnable (\r | |
280 | IN UINT32 ControlSystemRegisterEnable\r | |
281 | );\r | |
282 | \r | |
283 | VOID\r | |
284 | EFIAPI\r | |
285 | ArmGicV3EnableInterruptInterface (\r | |
286 | VOID\r | |
287 | );\r | |
288 | \r | |
289 | VOID\r | |
290 | EFIAPI\r | |
291 | ArmGicV3DisableInterruptInterface (\r | |
292 | VOID\r | |
293 | );\r | |
294 | \r | |
295 | UINTN\r | |
296 | EFIAPI\r | |
297 | ArmGicV3AcknowledgeInterrupt (\r | |
298 | VOID\r | |
299 | );\r | |
300 | \r | |
301 | VOID\r | |
302 | EFIAPI\r | |
303 | ArmGicV3EndOfInterrupt (\r | |
304 | IN UINTN Source\r | |
305 | );\r | |
306 | \r | |
307 | VOID\r | |
308 | ArmGicV3SetBinaryPointer (\r | |
309 | IN UINTN BinaryPoint\r | |
310 | );\r | |
311 | \r | |
312 | VOID\r | |
313 | ArmGicV3SetPriorityMask (\r | |
314 | IN UINTN Priority\r | |
315 | );\r | |
316 | \r | |
55a0d64b | 317 | #endif\r |