projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 1e57a462 | 1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
| 4e57d6d7 | 4 | Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r |
| 1e57a462 | 5 | \r |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #ifndef __ARM_LIB__\r | |
| 17 | #define __ARM_LIB__\r | |
| 18 | \r | |
| 19 | #include <Uefi/UefiBaseType.h>\r | |
| 20 | \r | |
| 25402f5d HL |
21 | #ifdef MDE_CPU_ARM\r |
| 22 | #ifdef ARM_CPU_ARMv6\r | |
| 23 | #include <Chipset/ARM1176JZ-S.h>\r | |
| 24 | #else\r | |
| 25 | #include <Chipset/ArmV7.h>\r | |
| 26 | #endif\r | |
| 27 | #elif defined(MDE_CPU_AARCH64)\r | |
| 28 | #include <Chipset/AArch64.h>\r | |
| 1e57a462 | 29 | #else\r |
| 25402f5d | 30 | #error "Unknown chipset."\r |
| 1e57a462 | 31 | #endif\r |
| 32 | \r | |
| 33 | typedef enum {\r | |
| 34 | ARM_CACHE_TYPE_WRITE_BACK,\r | |
| 35 | ARM_CACHE_TYPE_UNKNOWN\r | |
| 36 | } ARM_CACHE_TYPE;\r | |
| 37 | \r | |
| 38 | typedef enum {\r | |
| 39 | ARM_CACHE_ARCHITECTURE_UNIFIED,\r | |
| 40 | ARM_CACHE_ARCHITECTURE_SEPARATE,\r | |
| 41 | ARM_CACHE_ARCHITECTURE_UNKNOWN\r | |
| 42 | } ARM_CACHE_ARCHITECTURE;\r | |
| 43 | \r | |
| 44 | typedef struct {\r | |
| 45 | ARM_CACHE_TYPE Type;\r | |
| 46 | ARM_CACHE_ARCHITECTURE Architecture;\r | |
| 47 | BOOLEAN DataCachePresent;\r | |
| 48 | UINTN DataCacheSize;\r | |
| 49 | UINTN DataCacheAssociativity;\r | |
| 50 | UINTN DataCacheLineLength;\r | |
| 51 | BOOLEAN InstructionCachePresent;\r | |
| 52 | UINTN InstructionCacheSize;\r | |
| 53 | UINTN InstructionCacheAssociativity;\r | |
| 54 | UINTN InstructionCacheLineLength;\r | |
| 55 | } ARM_CACHE_INFO;\r | |
| 56 | \r | |
| 57 | /**\r | |
| 58 | * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r | |
| 59 | *\r | |
| 60 | * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r | |
| 61 | * be used in Secure World to distinguished Secure to Non-Secure memory.\r | |
| 62 | */\r | |
| 63 | typedef enum {\r | |
| 64 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r | |
| 65 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r | |
| 66 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r | |
| 67 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r | |
| 68 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r | |
| 69 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r | |
| 70 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r | |
| 71 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r | |
| 72 | } ARM_MEMORY_REGION_ATTRIBUTES;\r | |
| 73 | \r | |
| 74 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r | |
| 75 | \r | |
| 76 | typedef struct {\r | |
| 77 | EFI_PHYSICAL_ADDRESS PhysicalBase;\r | |
| 78 | EFI_VIRTUAL_ADDRESS VirtualBase;\r | |
| c357fd6a | 79 | UINT64 Length;\r |
| 1e57a462 | 80 | ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r |
| 81 | } ARM_MEMORY_REGION_DESCRIPTOR;\r | |
| 82 | \r | |
| 83 | typedef VOID (*CACHE_OPERATION)(VOID);\r | |
| 84 | typedef VOID (*LINE_OPERATION)(UINTN);\r | |
| 85 | \r | |
| 86 | //\r | |
| 87 | // ARM Processor Mode\r | |
| 88 | //\r | |
| 89 | typedef enum {\r | |
| 90 | ARM_PROCESSOR_MODE_USER = 0x10,\r | |
| 91 | ARM_PROCESSOR_MODE_FIQ = 0x11,\r | |
| 92 | ARM_PROCESSOR_MODE_IRQ = 0x12,\r | |
| 93 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r | |
| 94 | ARM_PROCESSOR_MODE_ABORT = 0x17,\r | |
| 95 | ARM_PROCESSOR_MODE_HYP = 0x1A,\r | |
| 96 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r | |
| 97 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r | |
| 98 | ARM_PROCESSOR_MODE_MASK = 0x1F\r | |
| 99 | } ARM_PROCESSOR_MODE;\r | |
| 100 | \r | |
| 101 | //\r | |
| 102 | // ARM Cpu IDs\r | |
| 103 | //\r | |
| 104 | #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r | |
| 105 | #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r | |
| 106 | #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r | |
| 107 | #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r | |
| 108 | #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r | |
| 109 | #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r | |
| 110 | \r | |
| 111 | #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r | |
| 112 | #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r | |
| 113 | #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r | |
| 114 | #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r | |
| 115 | #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r | |
| 116 | #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r | |
| 117 | \r | |
| 118 | //\r | |
| 119 | // ARM MP Core IDs\r | |
| 120 | //\r | |
| 1e57a462 | 121 | #define ARM_CORE_MASK 0xFF\r |
| 122 | #define ARM_CLUSTER_MASK (0xFF << 8)\r | |
| 123 | #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r | |
| 124 | #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r | |
| e359565e | 125 | #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r |
| 1e57a462 | 126 | // Get the position of the core for the Stack Offset (4 Core per Cluster)\r |
| 127 | // Position = (ClusterId * 4) + CoreId\r | |
| 128 | #define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))\r | |
| 129 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r | |
| 130 | \r | |
| 131 | ARM_CACHE_TYPE\r | |
| 132 | EFIAPI\r | |
| 133 | ArmCacheType (\r | |
| 134 | VOID\r | |
| 135 | );\r | |
| 136 | \r | |
| 137 | ARM_CACHE_ARCHITECTURE\r | |
| 138 | EFIAPI\r | |
| 139 | ArmCacheArchitecture (\r | |
| 140 | VOID\r | |
| 141 | );\r | |
| 142 | \r | |
| 143 | VOID\r | |
| 144 | EFIAPI\r | |
| 145 | ArmCacheInformation (\r | |
| 146 | OUT ARM_CACHE_INFO *CacheInfo\r | |
| 147 | );\r | |
| 148 | \r | |
| 149 | BOOLEAN\r | |
| 150 | EFIAPI\r | |
| 151 | ArmDataCachePresent (\r | |
| 152 | VOID\r | |
| 153 | );\r | |
| 154 | \r | |
| 155 | UINTN\r | |
| 156 | EFIAPI\r | |
| 157 | ArmDataCacheSize (\r | |
| 158 | VOID\r | |
| 159 | );\r | |
| 160 | \r | |
| 161 | UINTN\r | |
| 162 | EFIAPI\r | |
| 163 | ArmDataCacheAssociativity (\r | |
| 164 | VOID\r | |
| 165 | );\r | |
| 166 | \r | |
| 167 | UINTN\r | |
| 168 | EFIAPI\r | |
| 169 | ArmDataCacheLineLength (\r | |
| 170 | VOID\r | |
| 171 | );\r | |
| 172 | \r | |
| 173 | BOOLEAN\r | |
| 174 | EFIAPI\r | |
| 175 | ArmInstructionCachePresent (\r | |
| 176 | VOID\r | |
| 177 | );\r | |
| 178 | \r | |
| 179 | UINTN\r | |
| 180 | EFIAPI\r | |
| 181 | ArmInstructionCacheSize (\r | |
| 182 | VOID\r | |
| 183 | );\r | |
| 184 | \r | |
| 185 | UINTN\r | |
| 186 | EFIAPI\r | |
| 187 | ArmInstructionCacheAssociativity (\r | |
| 188 | VOID\r | |
| 189 | );\r | |
| 190 | \r | |
| 191 | UINTN\r | |
| 192 | EFIAPI\r | |
| 193 | ArmInstructionCacheLineLength (\r | |
| 194 | VOID\r | |
| 195 | );\r | |
| 168d7245 OM |
196 | \r |
| 197 | UINTN\r | |
| 198 | EFIAPI\r | |
| 199 | ArmIsArchTimerImplemented (\r | |
| 200 | VOID\r | |
| 201 | );\r | |
| 202 | \r | |
| 203 | UINTN\r | |
| 204 | EFIAPI\r | |
| 205 | ArmReadIdPfr0 (\r | |
| 206 | VOID\r | |
| 207 | );\r | |
| 208 | \r | |
| 209 | UINTN\r | |
| 210 | EFIAPI\r | |
| 211 | ArmReadIdPfr1 (\r | |
| 212 | VOID\r | |
| 213 | );\r | |
| 214 | \r | |
| 1e57a462 | 215 | UINT32\r |
| 216 | EFIAPI\r | |
| 217 | Cp15IdCode (\r | |
| 218 | VOID\r | |
| 219 | );\r | |
| 220 | \r | |
| 221 | UINT32\r | |
| 222 | EFIAPI\r | |
| 223 | Cp15CacheInfo (\r | |
| 224 | VOID\r | |
| 225 | );\r | |
| 226 | \r | |
| 227 | BOOLEAN\r | |
| 228 | EFIAPI\r | |
| 229 | ArmIsMpCore (\r | |
| 230 | VOID\r | |
| 231 | );\r | |
| 232 | \r | |
| 233 | VOID\r | |
| 234 | EFIAPI\r | |
| 235 | ArmInvalidateDataCache (\r | |
| 236 | VOID\r | |
| 237 | );\r | |
| 238 | \r | |
| 239 | \r | |
| 240 | VOID\r | |
| 241 | EFIAPI\r | |
| 242 | ArmCleanInvalidateDataCache (\r | |
| 243 | VOID\r | |
| 244 | );\r | |
| 245 | \r | |
| 246 | VOID\r | |
| 247 | EFIAPI\r | |
| 248 | ArmCleanDataCache (\r | |
| 249 | VOID\r | |
| 250 | );\r | |
| 251 | \r | |
| 252 | VOID\r | |
| 253 | EFIAPI\r | |
| 254 | ArmCleanDataCacheToPoU (\r | |
| 255 | VOID\r | |
| 256 | );\r | |
| 257 | \r | |
| 258 | VOID\r | |
| 259 | EFIAPI\r | |
| 260 | ArmInvalidateInstructionCache (\r | |
| 261 | VOID\r | |
| 262 | );\r | |
| 263 | \r | |
| 264 | VOID\r | |
| 265 | EFIAPI\r | |
| 266 | ArmInvalidateDataCacheEntryByMVA (\r | |
| 267 | IN UINTN Address\r | |
| 268 | );\r | |
| 269 | \r | |
| 270 | VOID\r | |
| 271 | EFIAPI\r | |
| 272 | ArmCleanDataCacheEntryByMVA (\r | |
| 273 | IN UINTN Address\r | |
| 274 | );\r | |
| 275 | \r | |
| 276 | VOID\r | |
| 277 | EFIAPI\r | |
| 278 | ArmCleanInvalidateDataCacheEntryByMVA (\r | |
| 279 | IN UINTN Address\r | |
| 280 | );\r | |
| 281 | \r | |
| 0ff0e414 OM |
282 | VOID\r |
| 283 | EFIAPI\r | |
| 284 | ArmInvalidateDataCacheEntryBySetWay (\r | |
| 285 | IN UINTN SetWayFormat\r | |
| 286 | );\r | |
| 287 | \r | |
| 288 | VOID\r | |
| 289 | EFIAPI\r | |
| 290 | ArmCleanDataCacheEntryBySetWay (\r | |
| 291 | IN UINTN SetWayFormat\r | |
| 292 | );\r | |
| 293 | \r | |
| 294 | VOID\r | |
| 295 | EFIAPI\r | |
| 296 | ArmCleanInvalidateDataCacheEntryBySetWay (\r | |
| 297 | IN UINTN SetWayFormat\r | |
| 298 | );\r | |
| 299 | \r | |
| 1e57a462 | 300 | VOID\r |
| 301 | EFIAPI\r | |
| 302 | ArmEnableDataCache (\r | |
| 303 | VOID\r | |
| 304 | );\r | |
| 305 | \r | |
| 306 | VOID\r | |
| 307 | EFIAPI\r | |
| 308 | ArmDisableDataCache (\r | |
| 309 | VOID\r | |
| 310 | );\r | |
| 311 | \r | |
| 312 | VOID\r | |
| 313 | EFIAPI\r | |
| 314 | ArmEnableInstructionCache (\r | |
| 315 | VOID\r | |
| 316 | );\r | |
| 317 | \r | |
| 318 | VOID\r | |
| 319 | EFIAPI\r | |
| 320 | ArmDisableInstructionCache (\r | |
| 321 | VOID\r | |
| 322 | );\r | |
| 323 | \r | |
| 324 | VOID\r | |
| 325 | EFIAPI\r | |
| 326 | ArmEnableMmu (\r | |
| 327 | VOID\r | |
| 328 | );\r | |
| 329 | \r | |
| 330 | VOID\r | |
| 331 | EFIAPI\r | |
| 332 | ArmDisableMmu (\r | |
| 333 | VOID\r | |
| 334 | );\r | |
| 335 | \r | |
| 0ff0e414 OM |
336 | VOID\r |
| 337 | EFIAPI\r | |
| 338 | ArmEnableCachesAndMmu (\r | |
| 339 | VOID\r | |
| 340 | );\r | |
| 341 | \r | |
| 1e57a462 | 342 | VOID\r |
| 343 | EFIAPI\r | |
| 344 | ArmDisableCachesAndMmu (\r | |
| 345 | VOID\r | |
| 346 | );\r | |
| 347 | \r | |
| 348 | VOID\r | |
| 349 | EFIAPI\r | |
| 350 | ArmInvalidateInstructionAndDataTlb (\r | |
| 351 | VOID\r | |
| 352 | );\r | |
| 353 | \r | |
| 354 | VOID\r | |
| 355 | EFIAPI\r | |
| 356 | ArmEnableInterrupts (\r | |
| 357 | VOID\r | |
| 358 | );\r | |
| 359 | \r | |
| 360 | UINTN\r | |
| 361 | EFIAPI\r | |
| 362 | ArmDisableInterrupts (\r | |
| 363 | VOID\r | |
| 364 | );\r | |
| 47585ed5 | 365 | \r |
| 1e57a462 | 366 | BOOLEAN\r |
| 367 | EFIAPI\r | |
| 368 | ArmGetInterruptState (\r | |
| 369 | VOID\r | |
| 370 | );\r | |
| 371 | \r | |
| 0ff0e414 OM |
372 | VOID\r |
| 373 | EFIAPI\r | |
| 374 | ArmEnableAsynchronousAbort (\r | |
| 375 | VOID\r | |
| 376 | );\r | |
| 377 | \r | |
| 47585ed5 | 378 | UINTN\r |
| 379 | EFIAPI\r | |
| 0ff0e414 | 380 | ArmDisableAsynchronousAbort (\r |
| 47585ed5 | 381 | VOID\r |
| 382 | );\r | |
| 383 | \r | |
| 384 | VOID\r | |
| 385 | EFIAPI\r | |
| 386 | ArmEnableIrq (\r | |
| 387 | VOID\r | |
| 388 | );\r | |
| 389 | \r | |
| 0ff0e414 OM |
390 | UINTN\r |
| 391 | EFIAPI\r | |
| 392 | ArmDisableIrq (\r | |
| 393 | VOID\r | |
| 394 | );\r | |
| 395 | \r | |
| 1e57a462 | 396 | VOID\r |
| 397 | EFIAPI\r | |
| 398 | ArmEnableFiq (\r | |
| 399 | VOID\r | |
| 400 | );\r | |
| 401 | \r | |
| 402 | UINTN\r | |
| 403 | EFIAPI\r | |
| 404 | ArmDisableFiq (\r | |
| 405 | VOID\r | |
| 406 | );\r | |
| 407 | \r | |
| 408 | BOOLEAN\r | |
| 409 | EFIAPI\r | |
| 410 | ArmGetFiqState (\r | |
| 411 | VOID\r | |
| 412 | );\r | |
| 413 | \r | |
| 414 | VOID\r | |
| 415 | EFIAPI\r | |
| 416 | ArmInvalidateTlb (\r | |
| 417 | VOID\r | |
| 418 | );\r | |
| 419 | \r | |
| 420 | VOID\r | |
| 421 | EFIAPI\r | |
| 422 | ArmUpdateTranslationTableEntry (\r | |
| 423 | IN VOID *TranslationTableEntry,\r | |
| 424 | IN VOID *Mva\r | |
| 425 | );\r | |
| 426 | \r | |
| 427 | VOID\r | |
| 428 | EFIAPI\r | |
| 429 | ArmSetDomainAccessControl (\r | |
| 430 | IN UINT32 Domain\r | |
| 431 | );\r | |
| 432 | \r | |
| 433 | VOID\r | |
| 434 | EFIAPI\r | |
| 435 | ArmSetTTBR0 (\r | |
| 436 | IN VOID *TranslationTableBase\r | |
| 437 | );\r | |
| 438 | \r | |
| 439 | VOID *\r | |
| 440 | EFIAPI\r | |
| 441 | ArmGetTTBR0BaseAddress (\r | |
| 442 | VOID\r | |
| 443 | );\r | |
| 444 | \r | |
| 6f050ad6 | 445 | RETURN_STATUS\r |
| 1e57a462 | 446 | EFIAPI\r |
| 447 | ArmConfigureMmu (\r | |
| 448 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r | |
| 6f050ad6 | 449 | OUT VOID **TranslationTableBase OPTIONAL,\r |
| 1e57a462 | 450 | OUT UINTN *TranslationTableSize OPTIONAL\r |
| 451 | );\r | |
| 452 | \r | |
| 453 | BOOLEAN\r | |
| 454 | EFIAPI\r | |
| 455 | ArmMmuEnabled (\r | |
| 456 | VOID\r | |
| 457 | );\r | |
| 458 | \r | |
| 459 | VOID\r | |
| 460 | EFIAPI\r | |
| 461 | ArmSwitchProcessorMode (\r | |
| 462 | IN ARM_PROCESSOR_MODE Mode\r | |
| 463 | );\r | |
| 464 | \r | |
| 465 | ARM_PROCESSOR_MODE\r | |
| 466 | EFIAPI\r | |
| 467 | ArmProcessorMode (\r | |
| 468 | VOID\r | |
| 469 | );\r | |
| 470 | \r | |
| 471 | VOID\r | |
| 472 | EFIAPI\r | |
| 473 | ArmEnableBranchPrediction (\r | |
| 474 | VOID\r | |
| 475 | );\r | |
| 476 | \r | |
| 477 | VOID\r | |
| 478 | EFIAPI\r | |
| 479 | ArmDisableBranchPrediction (\r | |
| 480 | VOID\r | |
| 481 | );\r | |
| 482 | \r | |
| 483 | VOID\r | |
| 484 | EFIAPI\r | |
| 485 | ArmSetLowVectors (\r | |
| 486 | VOID\r | |
| 487 | );\r | |
| 488 | \r | |
| 489 | VOID\r | |
| 490 | EFIAPI\r | |
| 491 | ArmSetHighVectors (\r | |
| 492 | VOID\r | |
| 493 | );\r | |
| 494 | \r | |
| 0ff0e414 OM |
495 | VOID\r |
| 496 | EFIAPI\r | |
| 497 | ArmDrainWriteBuffer (\r | |
| 498 | VOID\r | |
| 499 | );\r | |
| 500 | \r | |
| 1e57a462 | 501 | VOID\r |
| 502 | EFIAPI\r | |
| 503 | ArmDataMemoryBarrier (\r | |
| 504 | VOID\r | |
| 505 | );\r | |
| 506 | \r | |
| 507 | VOID\r | |
| 508 | EFIAPI\r | |
| 509 | ArmDataSyncronizationBarrier (\r | |
| 510 | VOID\r | |
| 511 | );\r | |
| 512 | \r | |
| 513 | VOID\r | |
| 514 | EFIAPI\r | |
| 515 | ArmInstructionSynchronizationBarrier (\r | |
| 516 | VOID\r | |
| 517 | );\r | |
| 518 | \r | |
| 519 | VOID\r | |
| 520 | EFIAPI\r | |
| 521 | ArmWriteVBar (\r | |
| 4e57d6d7 | 522 | IN UINTN VectorBase\r |
| 1e57a462 | 523 | );\r |
| 524 | \r | |
| 4e57d6d7 | 525 | UINTN\r |
| 1e57a462 | 526 | EFIAPI\r |
| 527 | ArmReadVBar (\r | |
| 528 | VOID\r | |
| 529 | );\r | |
| 530 | \r | |
| 531 | VOID\r | |
| 532 | EFIAPI\r | |
| 533 | ArmWriteAuxCr (\r | |
| 534 | IN UINT32 Bit\r | |
| 535 | );\r | |
| 536 | \r | |
| 537 | UINT32\r | |
| 538 | EFIAPI\r | |
| 539 | ArmReadAuxCr (\r | |
| 540 | VOID\r | |
| 541 | );\r | |
| 542 | \r | |
| 543 | VOID\r | |
| 544 | EFIAPI\r | |
| 545 | ArmSetAuxCrBit (\r | |
| 546 | IN UINT32 Bits\r | |
| 547 | );\r | |
| 548 | \r | |
| 549 | VOID\r | |
| 550 | EFIAPI\r | |
| 551 | ArmUnsetAuxCrBit (\r | |
| 552 | IN UINT32 Bits\r | |
| 553 | );\r | |
| 554 | \r | |
| 555 | VOID\r | |
| 556 | EFIAPI\r | |
| 557 | ArmCallSEV (\r | |
| 558 | VOID\r | |
| 559 | );\r | |
| 560 | \r | |
| 561 | VOID\r | |
| 562 | EFIAPI\r | |
| 563 | ArmCallWFE (\r | |
| 564 | VOID\r | |
| 565 | );\r | |
| 566 | \r | |
| 567 | VOID\r | |
| 568 | EFIAPI\r | |
| 569 | ArmCallWFI (\r | |
| 25402f5d | 570 | \r |
| 1e57a462 | 571 | VOID\r |
| 572 | );\r | |
| 573 | \r | |
| 574 | UINTN\r | |
| 575 | EFIAPI\r | |
| 576 | ArmReadMpidr (\r | |
| 577 | VOID\r | |
| 578 | );\r | |
| 579 | \r | |
| 9401d6f4 OM |
580 | UINTN\r |
| 581 | EFIAPI\r | |
| 582 | ArmReadMidr (\r | |
| 583 | VOID\r | |
| 584 | );\r | |
| 585 | \r | |
| 1e57a462 | 586 | UINT32\r |
| 587 | EFIAPI\r | |
| 588 | ArmReadCpacr (\r | |
| 589 | VOID\r | |
| 590 | );\r | |
| 591 | \r | |
| 592 | VOID\r | |
| 593 | EFIAPI\r | |
| 594 | ArmWriteCpacr (\r | |
| 595 | IN UINT32 Access\r | |
| 596 | );\r | |
| 597 | \r | |
| 598 | VOID\r | |
| 599 | EFIAPI\r | |
| 600 | ArmEnableVFP (\r | |
| 601 | VOID\r | |
| 602 | );\r | |
| 603 | \r | |
| 1e57a462 | 604 | UINT32\r |
| 605 | EFIAPI\r | |
| 606 | ArmReadScr (\r | |
| 607 | VOID\r | |
| 608 | );\r | |
| 609 | \r | |
| 610 | VOID\r | |
| 611 | EFIAPI\r | |
| 612 | ArmWriteScr (\r | |
| 613 | IN UINT32 SetWayFormat\r | |
| 614 | );\r | |
| 615 | \r | |
| 616 | UINT32\r | |
| 617 | EFIAPI\r | |
| 618 | ArmReadMVBar (\r | |
| 619 | VOID\r | |
| 620 | );\r | |
| 621 | \r | |
| 622 | VOID\r | |
| 623 | EFIAPI\r | |
| 624 | ArmWriteMVBar (\r | |
| 625 | IN UINT32 VectorMonitorBase\r | |
| 626 | );\r | |
| 627 | \r | |
| 628 | UINT32\r | |
| 629 | EFIAPI\r | |
| 630 | ArmReadSctlr (\r | |
| 631 | VOID\r | |
| 632 | );\r | |
| 633 | \r | |
| 5ea2c2d3 | 634 | UINTN\r |
| 635 | EFIAPI\r | |
| 636 | ArmReadHVBar (\r | |
| 637 | VOID\r | |
| 638 | );\r | |
| 639 | \r | |
| 640 | VOID\r | |
| 641 | EFIAPI\r | |
| 642 | ArmWriteHVBar (\r | |
| 643 | IN UINTN HypModeVectorBase\r | |
| 644 | );\r | |
| 645 | \r | |
| 1e57a462 | 646 | #endif // __ARM_LIB__\r |