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EmbeddedPkg: Clarify the declaration of SerialPortGetControl()
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1e57a462 1/** @file\r
2\r
3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
4e57d6d7 4 Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
1e57a462 5\r
6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef __ARM_LIB__\r
17#define __ARM_LIB__\r
18\r
19#include <Uefi/UefiBaseType.h>\r
20\r
25402f5d
HL		 21#ifdef MDE_CPU_ARM\r
22 #ifdef ARM_CPU_ARMv6\r
23 #include <Chipset/ARM1176JZ-S.h>\r
24 #else\r
25 #include <Chipset/ArmV7.h>\r
26 #endif\r
27#elif defined(MDE_CPU_AARCH64)\r
28 #include <Chipset/AArch64.h>\r
1e57a462 29#else\r
25402f5d 30 #error "Unknown chipset."\r
1e57a462 31#endif\r
32\r
33typedef enum {\r
34 ARM_CACHE_TYPE_WRITE_BACK,\r
35 ARM_CACHE_TYPE_UNKNOWN\r
36} ARM_CACHE_TYPE;\r
37\r
38typedef enum {\r
39 ARM_CACHE_ARCHITECTURE_UNIFIED,\r
40 ARM_CACHE_ARCHITECTURE_SEPARATE,\r
41 ARM_CACHE_ARCHITECTURE_UNKNOWN\r
42} ARM_CACHE_ARCHITECTURE;\r
43\r
44typedef struct {\r
45 ARM_CACHE_TYPE Type;\r
46 ARM_CACHE_ARCHITECTURE Architecture;\r
47 BOOLEAN DataCachePresent;\r
48 UINTN DataCacheSize;\r
49 UINTN DataCacheAssociativity;\r
50 UINTN DataCacheLineLength;\r
51 BOOLEAN InstructionCachePresent;\r
52 UINTN InstructionCacheSize;\r
53 UINTN InstructionCacheAssociativity;\r
54 UINTN InstructionCacheLineLength;\r
55} ARM_CACHE_INFO;\r
56\r
57/**\r
58 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
59 *\r
60 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
61 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
62 */\r
63typedef enum {\r
64 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
65 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
66 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
67 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
68 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
69 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
70 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
71 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
72} ARM_MEMORY_REGION_ATTRIBUTES;\r
73\r
74#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
75\r
76typedef struct {\r
77 EFI_PHYSICAL_ADDRESS PhysicalBase;\r
78 EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a 79 UINT64 Length;\r
1e57a462 80 ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
81} ARM_MEMORY_REGION_DESCRIPTOR;\r
82\r
83typedef VOID (*CACHE_OPERATION)(VOID);\r
84typedef VOID (*LINE_OPERATION)(UINTN);\r
85\r
86//\r
87// ARM Processor Mode\r
88//\r
89typedef enum {\r
90 ARM_PROCESSOR_MODE_USER = 0x10,\r
91 ARM_PROCESSOR_MODE_FIQ = 0x11,\r
92 ARM_PROCESSOR_MODE_IRQ = 0x12,\r
93 ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
94 ARM_PROCESSOR_MODE_ABORT = 0x17,\r
95 ARM_PROCESSOR_MODE_HYP = 0x1A,\r
96 ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
97 ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
98 ARM_PROCESSOR_MODE_MASK = 0x1F\r
99} ARM_PROCESSOR_MODE;\r
100\r
101//\r
102// ARM Cpu IDs\r
103//\r
104#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
105#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
106#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
107#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
108#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
109#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
110\r
111#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
112#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
113#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
114#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
115#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
116#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
117\r
118//\r
119// ARM MP Core IDs\r
120//\r
1e57a462 121#define ARM_CORE_MASK 0xFF\r
122#define ARM_CLUSTER_MASK (0xFF << 8)\r
123#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
124#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e 125#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
1e57a462 126#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
127\r
128ARM_CACHE_TYPE\r
129EFIAPI\r
130ArmCacheType (\r
131 VOID\r
132 );\r
133\r
134ARM_CACHE_ARCHITECTURE\r
135EFIAPI\r
136ArmCacheArchitecture (\r
137 VOID\r
138 );\r
139\r
140VOID\r
141EFIAPI\r
142ArmCacheInformation (\r
143 OUT ARM_CACHE_INFO *CacheInfo\r
144 );\r
145\r
146BOOLEAN\r
147EFIAPI\r
148ArmDataCachePresent (\r
149 VOID\r
150 );\r
3402aac7 151\r
1e57a462 152UINTN\r
153EFIAPI\r
154ArmDataCacheSize (\r
155 VOID\r
156 );\r
3402aac7 157\r
1e57a462 158UINTN\r
159EFIAPI\r
160ArmDataCacheAssociativity (\r
161 VOID\r
162 );\r
3402aac7 163\r
1e57a462 164UINTN\r
165EFIAPI\r
166ArmDataCacheLineLength (\r
167 VOID\r
168 );\r
3402aac7 169\r
1e57a462 170BOOLEAN\r
171EFIAPI\r
172ArmInstructionCachePresent (\r
173 VOID\r
174 );\r
3402aac7 175\r
1e57a462 176UINTN\r
177EFIAPI\r
178ArmInstructionCacheSize (\r
179 VOID\r
180 );\r
3402aac7 181\r
1e57a462 182UINTN\r
183EFIAPI\r
184ArmInstructionCacheAssociativity (\r
185 VOID\r
186 );\r
3402aac7 187\r
1e57a462 188UINTN\r
189EFIAPI\r
190ArmInstructionCacheLineLength (\r
191 VOID\r
192 );\r
168d7245
OM		 193\r
194UINTN\r
195EFIAPI\r
196ArmIsArchTimerImplemented (\r
197 VOID\r
198 );\r
199\r
200UINTN\r
201EFIAPI\r
202ArmReadIdPfr0 (\r
203 VOID\r
204 );\r
205\r
206UINTN\r
207EFIAPI\r
208ArmReadIdPfr1 (\r
209 VOID\r
210 );\r
211\r
64751727 212UINTN\r
1e57a462 213EFIAPI\r
64751727 214ArmCacheInfo (\r
1e57a462 215 VOID\r
216 );\r
217\r
218BOOLEAN\r
219EFIAPI\r
220ArmIsMpCore (\r
221 VOID\r
222 );\r
223\r
224VOID\r
225EFIAPI\r
226ArmInvalidateDataCache (\r
227 VOID\r
228 );\r
229\r
230\r
231VOID\r
232EFIAPI\r
233ArmCleanInvalidateDataCache (\r
234 VOID\r
235 );\r
236\r
237VOID\r
238EFIAPI\r
239ArmCleanDataCache (\r
240 VOID\r
241 );\r
242\r
243VOID\r
244EFIAPI\r
245ArmCleanDataCacheToPoU (\r
246 VOID\r
247 );\r
248\r
249VOID\r
250EFIAPI\r
251ArmInvalidateInstructionCache (\r
252 VOID\r
253 );\r
254\r
255VOID\r
256EFIAPI\r
257ArmInvalidateDataCacheEntryByMVA (\r
258 IN UINTN Address\r
259 );\r
260\r
261VOID\r
262EFIAPI\r
263ArmCleanDataCacheEntryByMVA (\r
264 IN UINTN Address\r
265 );\r
266\r
267VOID\r
268EFIAPI\r
269ArmCleanInvalidateDataCacheEntryByMVA (\r
270 IN UINTN Address\r
271 );\r
272\r
0ff0e414
OM		 273VOID\r
274EFIAPI\r
275ArmInvalidateDataCacheEntryBySetWay (\r
276 IN UINTN SetWayFormat\r
277 );\r
278\r
279VOID\r
280EFIAPI\r
281ArmCleanDataCacheEntryBySetWay (\r
282 IN UINTN SetWayFormat\r
283 );\r
284\r
285VOID\r
286EFIAPI\r
287ArmCleanInvalidateDataCacheEntryBySetWay (\r
288 IN UINTN SetWayFormat\r
289 );\r
290\r
1e57a462 291VOID\r
292EFIAPI\r
293ArmEnableDataCache (\r
294 VOID\r
295 );\r
296\r
297VOID\r
298EFIAPI\r
299ArmDisableDataCache (\r
300 VOID\r
301 );\r
302\r
303VOID\r
304EFIAPI\r
305ArmEnableInstructionCache (\r
306 VOID\r
307 );\r
308\r
309VOID\r
310EFIAPI\r
311ArmDisableInstructionCache (\r
312 VOID\r
313 );\r
3402aac7 314\r
1e57a462 315VOID\r
316EFIAPI\r
317ArmEnableMmu (\r
318 VOID\r
319 );\r
320\r
321VOID\r
322EFIAPI\r
323ArmDisableMmu (\r
324 VOID\r
325 );\r
326\r
0ff0e414
OM		 327VOID\r
328EFIAPI\r
329ArmEnableCachesAndMmu (\r
330 VOID\r
331 );\r
332\r
1e57a462 333VOID\r
334EFIAPI\r
335ArmDisableCachesAndMmu (\r
336 VOID\r
337 );\r
338\r
339VOID\r
340EFIAPI\r
341ArmInvalidateInstructionAndDataTlb (\r
342 VOID\r
343 );\r
344\r
345VOID\r
346EFIAPI\r
347ArmEnableInterrupts (\r
348 VOID\r
349 );\r
350\r
351UINTN\r
352EFIAPI\r
353ArmDisableInterrupts (\r
354 VOID\r
355 );\r
47585ed5 356\r
1e57a462 357BOOLEAN\r
358EFIAPI\r
359ArmGetInterruptState (\r
360 VOID\r
361 );\r
362\r
0ff0e414
OM		 363VOID\r
364EFIAPI\r
365ArmEnableAsynchronousAbort (\r
366 VOID\r
367 );\r
368\r
47585ed5 369UINTN\r
370EFIAPI\r
0ff0e414 371ArmDisableAsynchronousAbort (\r
47585ed5 372 VOID\r
373 );\r
374\r
375VOID\r
376EFIAPI\r
377ArmEnableIrq (\r
378 VOID\r
379 );\r
380\r
0ff0e414
OM		 381UINTN\r
382EFIAPI\r
383ArmDisableIrq (\r
384 VOID\r
385 );\r
386\r
1e57a462 387VOID\r
388EFIAPI\r
389ArmEnableFiq (\r
390 VOID\r
391 );\r
392\r
393UINTN\r
394EFIAPI\r
395ArmDisableFiq (\r
396 VOID\r
397 );\r
3402aac7 398\r
1e57a462 399BOOLEAN\r
400EFIAPI\r
401ArmGetFiqState (\r
402 VOID\r
403 );\r
404\r
405VOID\r
406EFIAPI\r
407ArmInvalidateTlb (\r
408 VOID\r
409 );\r
3402aac7 410\r
1e57a462 411VOID\r
412EFIAPI\r
413ArmUpdateTranslationTableEntry (\r
414 IN VOID *TranslationTableEntry,\r
415 IN VOID *Mva\r
416 );\r
3402aac7 417\r
1e57a462 418VOID\r
419EFIAPI\r
420ArmSetDomainAccessControl (\r
421 IN UINT32 Domain\r
422 );\r
423\r
424VOID\r
425EFIAPI\r
426ArmSetTTBR0 (\r
427 IN VOID *TranslationTableBase\r
428 );\r
429\r
430VOID *\r
431EFIAPI\r
432ArmGetTTBR0BaseAddress (\r
433 VOID\r
434 );\r
435\r
6f050ad6 436RETURN_STATUS\r
1e57a462 437EFIAPI\r
438ArmConfigureMmu (\r
439 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
6f050ad6 440 OUT VOID **TranslationTableBase OPTIONAL,\r
1e57a462 441 OUT UINTN *TranslationTableSize OPTIONAL\r
442 );\r
3402aac7 443\r
1e57a462 444BOOLEAN\r
445EFIAPI\r
446ArmMmuEnabled (\r
447 VOID\r
448 );\r
3402aac7 449\r
1e57a462 450VOID\r
451EFIAPI\r
452ArmEnableBranchPrediction (\r
453 VOID\r
454 );\r
455\r
456VOID\r
457EFIAPI\r
458ArmDisableBranchPrediction (\r
459 VOID\r
460 );\r
461\r
462VOID\r
463EFIAPI\r
464ArmSetLowVectors (\r
465 VOID\r
466 );\r
467\r
468VOID\r
469EFIAPI\r
470ArmSetHighVectors (\r
471 VOID\r
472 );\r
473\r
0ff0e414
OM		 474VOID\r
475EFIAPI\r
476ArmDrainWriteBuffer (\r
477 VOID\r
478 );\r
479\r
1e57a462 480VOID\r
481EFIAPI\r
482ArmDataMemoryBarrier (\r
483 VOID\r
484 );\r
3402aac7 485\r
1e57a462 486VOID\r
487EFIAPI\r
488ArmDataSyncronizationBarrier (\r
489 VOID\r
490 );\r
3402aac7 491\r
1e57a462 492VOID\r
493EFIAPI\r
494ArmInstructionSynchronizationBarrier (\r
495 VOID\r
496 );\r
497\r
498VOID\r
499EFIAPI\r
500ArmWriteVBar (\r
4e57d6d7 501 IN UINTN VectorBase\r
1e57a462 502 );\r
503\r
4e57d6d7 504UINTN\r
1e57a462 505EFIAPI\r
506ArmReadVBar (\r
507 VOID\r
508 );\r
509\r
510VOID\r
511EFIAPI\r
512ArmWriteAuxCr (\r
513 IN UINT32 Bit\r
514 );\r
515\r
516UINT32\r
517EFIAPI\r
518ArmReadAuxCr (\r
519 VOID\r
520 );\r
521\r
522VOID\r
523EFIAPI\r
524ArmSetAuxCrBit (\r
525 IN UINT32 Bits\r
526 );\r
527\r
528VOID\r
529EFIAPI\r
530ArmUnsetAuxCrBit (\r
531 IN UINT32 Bits\r
532 );\r
533\r
534VOID\r
535EFIAPI\r
536ArmCallSEV (\r
537 VOID\r
538 );\r
539\r
540VOID\r
541EFIAPI\r
542ArmCallWFE (\r
543 VOID\r
544 );\r
545\r
546VOID\r
547EFIAPI\r
548ArmCallWFI (\r
25402f5d 549\r
1e57a462 550 VOID\r
551 );\r
552\r
553UINTN\r
554EFIAPI\r
555ArmReadMpidr (\r
556 VOID\r
557 );\r
558\r
9401d6f4
OM		 559UINTN\r
560EFIAPI\r
561ArmReadMidr (\r
562 VOID\r
563 );\r
564\r
1e57a462 565UINT32\r
566EFIAPI\r
567ArmReadCpacr (\r
568 VOID\r
569 );\r
570\r
571VOID\r
572EFIAPI\r
573ArmWriteCpacr (\r
574 IN UINT32 Access\r
575 );\r
576\r
577VOID\r
578EFIAPI\r
579ArmEnableVFP (\r
580 VOID\r
581 );\r
582\r
46d4d75c
OM		 583/**\r
584 Get the Secure Configuration Register value\r
585\r
586 @return Value read from the Secure Configuration Register\r
587\r
588**/\r
1e57a462 589UINT32\r
590EFIAPI\r
591ArmReadScr (\r
592 VOID\r
593 );\r
594\r
46d4d75c
OM		 595/**\r
596 Set the Secure Configuration Register\r
597\r
598 @param Value Value to write to the Secure Configuration Register\r
599\r
600**/\r
1e57a462 601VOID\r
602EFIAPI\r
603ArmWriteScr (\r
46d4d75c 604 IN UINT32 Value\r
1e57a462 605 );\r
606\r
607UINT32\r
608EFIAPI\r
609ArmReadMVBar (\r
610 VOID\r
611 );\r
612\r
613VOID\r
614EFIAPI\r
615ArmWriteMVBar (\r
616 IN UINT32 VectorMonitorBase\r
617 );\r
618\r
619UINT32\r
620EFIAPI\r
621ArmReadSctlr (\r
622 VOID\r
623 );\r
624\r
5ea2c2d3 625UINTN\r
626EFIAPI\r
627ArmReadHVBar (\r
628 VOID\r
629 );\r
630\r
631VOID\r
632EFIAPI\r
633ArmWriteHVBar (\r
634 IN UINTN HypModeVectorBase\r
635 );\r
636\r
52d44f77
OM		 637\r
638//\r
639// Helper functions for accessing CPU ACTLR\r
640//\r
641\r
642UINTN\r
643EFIAPI\r
644ArmReadCpuActlr (\r
645 VOID\r
646 );\r
647\r
648VOID\r
649EFIAPI\r
650ArmWriteCpuActlr (\r
651 IN UINTN Val\r
652 );\r
653\r
654VOID\r
655EFIAPI\r
656ArmSetCpuActlrBit (\r
657 IN UINTN Bits\r
658 );\r
659\r
660VOID\r
661EFIAPI\r
662ArmUnsetCpuActlrBit (\r
663 IN UINTN Bits\r
664 );\r
665\r
1e57a462 666#endif // __ARM_LIB__\r
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