ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory
[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm / ArmLibSupport.S
CommitLineData
3402aac7 1#------------------------------------------------------------------------------\r
bd6b9799 2#\r
3# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
ff1f27c0 4# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
0efaa42f 5# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
bd6b9799 6#\r
7# This program and the accompanying materials\r
8# are licensed and made available under the terms and conditions of the BSD License\r
9# which accompanies this distribution. The full text of the license may be found at\r
10# http://opensource.org/licenses/bsd-license.php\r
11#\r
12# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14#\r
15#------------------------------------------------------------------------------\r
16\r
17#include <AsmMacroIoLib.h>\r
18\r
0efaa42f 19ASM_FUNC(ArmReadMidr)\r
bd6b9799 20 mrc p15,0,R0,c0,c0,0\r
21 bx LR\r
22\r
0efaa42f 23ASM_FUNC(ArmCacheInfo)\r
bd6b9799 24 mrc p15,0,R0,c0,c0,1\r
25 bx LR\r
26\r
0efaa42f 27ASM_FUNC(ArmGetInterruptState)\r
bd6b9799 28 mrs R0,CPSR\r
29 tst R0,#0x80 @Check if IRQ is enabled.\r
30 moveq R0,#1\r
31 movne R0,#0\r
32 bx LR\r
33\r
0efaa42f 34ASM_FUNC(ArmGetFiqState)\r
bd6b9799 35 mrs R0,CPSR\r
36 tst R0,#0x40 @Check if FIQ is enabled.\r
37 moveq R0,#1\r
38 movne R0,#0\r
39 bx LR\r
40\r
0efaa42f 41ASM_FUNC(ArmSetDomainAccessControl)\r
bd6b9799 42 mcr p15,0,r0,c3,c0,0\r
43 bx lr\r
44\r
0efaa42f 45ASM_FUNC(CPSRMaskInsert) @ on entry, r0 is the mask and r1 is the field to insert\r
bd6b9799 46 stmfd sp!, {r4-r12, lr} @ save all the banked registers\r
47 mov r3, sp @ copy the stack pointer into a non-banked register\r
48 mrs r2, cpsr @ read the cpsr\r
49 bic r2, r2, r0 @ clear mask in the cpsr\r
50 and r1, r1, r0 @ clear bits outside the mask in the input\r
51 orr r2, r2, r1 @ set field\r
52 msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)\r
53 isb\r
54 mov sp, r3 @ restore stack pointer\r
55 ldmfd sp!, {r4-r12, lr} @ restore registers\r
27995cd5 56 bx lr @ return (hopefully thumb-safe!)\r
bd6b9799 57\r
0efaa42f 58ASM_FUNC(CPSRRead)\r
bd6b9799 59 mrs r0, cpsr\r
60 bx lr\r
61\r
0efaa42f 62ASM_FUNC(ArmReadCpacr)\r
836c3500 63 mrc p15, 0, r0, c1, c0, 2\r
64 bx lr\r
65\r
0efaa42f 66ASM_FUNC(ArmWriteCpacr)\r
bd6b9799 67 mcr p15, 0, r0, c1, c0, 2\r
18029bb9 68 isb\r
bd6b9799 69 bx lr\r
70\r
0efaa42f 71ASM_FUNC(ArmWriteAuxCr)\r
bd6b9799 72 mcr p15, 0, r0, c1, c0, 1\r
73 bx lr\r
74\r
0efaa42f 75ASM_FUNC(ArmReadAuxCr)\r
bd6b9799 76 mrc p15, 0, r0, c1, c0, 1\r
3402aac7 77 bx lr\r
bd6b9799 78\r
0efaa42f 79ASM_FUNC(ArmSetTTBR0)\r
bd6b9799 80 mcr p15,0,r0,c2,c0,0\r
81 isb\r
82 bx lr\r
83\r
0efaa42f 84ASM_FUNC(ArmSetTTBCR)\r
ff1f27c0
EL
85 mcr p15, 0, r0, c2, c0, 2\r
86 isb\r
87 bx lr\r
88\r
0efaa42f 89ASM_FUNC(ArmGetTTBR0BaseAddress)\r
bd6b9799 90 mrc p15,0,r0,c2,c0,0\r
0efaa42f 91 MOV32 (r1, 0xFFFFC000)\r
bd6b9799 92 and r0, r0, r1\r
93 isb\r
94 bx lr\r
95\r
96//\r
97//VOID\r
98//ArmUpdateTranslationTableEntry (\r
99// IN VOID *TranslationTableEntry // R0\r
100// IN VOID *MVA // R1\r
101// );\r
0efaa42f 102ASM_FUNC(ArmUpdateTranslationTableEntry)\r
3402aac7 103 mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA\r
bd6b9799 104 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
105 dsb\r
106 isb\r
107 bx lr\r
108\r
0efaa42f 109ASM_FUNC(ArmInvalidateTlb)\r
bd6b9799 110 mov r0,#0\r
111 mcr p15,0,r0,c8,c7,0\r
112 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
113 dsb\r
114 isb\r
115 bx lr\r
116\r
0efaa42f 117ASM_FUNC(ArmReadScr)\r
836c3500 118 mrc p15, 0, r0, c1, c1, 0\r
119 bx lr\r
120\r
0efaa42f 121ASM_FUNC(ArmWriteScr)\r
bd6b9799 122 mcr p15, 0, r0, c1, c1, 0\r
b2d0e0c5 123 isb\r
bd6b9799 124 bx lr\r
125\r
0efaa42f 126ASM_FUNC(ArmReadHVBar)\r
5ea2c2d3 127 mrc p15, 4, r0, c12, c0, 0\r
128 bx lr\r
129\r
0efaa42f 130ASM_FUNC(ArmWriteHVBar)\r
5ea2c2d3 131 mcr p15, 4, r0, c12, c0, 0\r
132 bx lr\r
133\r
0efaa42f 134ASM_FUNC(ArmReadMVBar)\r
836c3500 135 mrc p15, 0, r0, c12, c0, 1\r
136 bx lr\r
137\r
0efaa42f 138ASM_FUNC(ArmWriteMVBar)\r
bd6b9799 139 mcr p15, 0, r0, c12, c0, 1\r
140 bx lr\r
141\r
0efaa42f 142ASM_FUNC(ArmCallWFE)\r
b1d41be7 143 wfe\r
144 bx lr\r
145\r
0efaa42f 146ASM_FUNC(ArmCallSEV)\r
b1d41be7 147 sev\r
148 bx lr\r
149\r
0efaa42f 150ASM_FUNC(ArmReadSctlr)\r
52d44f77
OM
151 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
152 bx lr\r
153\r
1e1d1697
MZ
154ASM_FUNC(ArmWriteSctlr)\r
155 mcr p15, 0, r0, c1, c0, 0\r
156 bx lr\r
157\r
0efaa42f 158ASM_FUNC(ArmReadCpuActlr)\r
52d44f77
OM
159 mrc p15, 0, r0, c1, c0, 1\r
160 bx lr\r
161\r
0efaa42f 162ASM_FUNC(ArmWriteCpuActlr)\r
52d44f77
OM
163 mcr p15, 0, r0, c1, c0, 1\r
164 dsb\r
165 isb\r
166 bx lr\r
836c3500 167\r
bd6b9799 168ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r