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ArmPkg/ArmLib: add support for reading the max physical address space size
[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm / ArmV7ArchTimerSupport.S
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3402aac7 1#------------------------------------------------------------------------------\r
da9675a2 2#\r
3# Copyright (c) 2011, ARM Limited. All rights reserved.\r
0efaa42f 4# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
da9675a2 5#\r
6# This program and the accompanying materials\r
7# are licensed and made available under the terms and conditions of the BSD License\r
8# which accompanies this distribution. The full text of the license may be found at\r
9# http://opensource.org/licenses/bsd-license.php\r
10#\r
11# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13#\r
14#------------------------------------------------------------------------------\r
15\r
0efaa42f
AB
16#include <AsmMacroIoLib.h>\r
17\r
18ASM_FUNC(ArmReadCntFrq)\r
da9675a2 19 mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ\r
20 bx lr\r
21\r
0efaa42f 22ASM_FUNC(ArmWriteCntFrq)\r
da9675a2 23 mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ\r
24 bx lr\r
25\r
0efaa42f 26ASM_FUNC(ArmReadCntPct)\r
da9675a2 27 mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)\r
28 bx lr\r
29\r
0efaa42f 30ASM_FUNC(ArmReadCntkCtl)\r
da9675a2 31 mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)\r
32 bx lr\r
33\r
0efaa42f 34ASM_FUNC(ArmWriteCntkCtl)\r
da9675a2 35 mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)\r
36 bx lr\r
37\r
0efaa42f 38ASM_FUNC(ArmReadCntpTval)\r
da9675a2 39 mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)\r
40 bx lr\r
41\r
0efaa42f 42ASM_FUNC(ArmWriteCntpTval)\r
da9675a2 43 mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)\r
44 bx lr\r
45\r
0efaa42f 46ASM_FUNC(ArmReadCntpCtl)\r
da9675a2 47 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)\r
48 bx lr\r
49\r
0efaa42f 50ASM_FUNC(ArmWriteCntpCtl)\r
da9675a2 51 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
52 bx lr\r
53\r
0efaa42f 54ASM_FUNC(ArmReadCntvTval)\r
da9675a2 55 mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)\r
56 bx lr\r
57\r
0efaa42f 58ASM_FUNC(ArmWriteCntvTval)\r
da9675a2 59 mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)\r
60 bx lr\r
61\r
0efaa42f 62ASM_FUNC(ArmReadCntvCtl)\r
da9675a2 63 mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)\r
64 bx lr\r
65\r
0efaa42f 66ASM_FUNC(ArmWriteCntvCtl)\r
da9675a2 67 mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)\r
68 bx lr\r
69\r
0efaa42f 70ASM_FUNC(ArmReadCntvCt)\r
da9675a2 71 mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)\r
72 bx lr\r
73\r
0efaa42f 74ASM_FUNC(ArmReadCntpCval)\r
da9675a2 75 mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
76 bx lr\r
77\r
0efaa42f 78ASM_FUNC(ArmWriteCntpCval)\r
da9675a2 79 mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
80 bx lr\r
81\r
0efaa42f 82ASM_FUNC(ArmReadCntvCval)\r
da9675a2 83 mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
84 bx lr\r
85\r
0efaa42f 86ASM_FUNC(ArmWriteCntvCval)\r
da9675a2 87 mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
88 bx lr\r
89\r
0efaa42f 90ASM_FUNC(ArmReadCntvOff)\r
da9675a2 91 mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)\r
92 bx lr\r
93\r
0efaa42f 94ASM_FUNC(ArmWriteCntvOff)\r
da9675a2 95 mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)\r
96 bx lr\r
97\r
98ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r