ArmPlatformPkg: Reformat VE Memory Map code

[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibRTSM / RTSMMem.c

/** @file\r
*\r
*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <ArmPlatform.h>\r
\r
// Number of Virtual Memory Map Descriptors\r
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          6\r
\r
// DDR attributes\r
#define DDR_ATTRIBUTES_CACHED   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
\r
/**\r
  Return the Virtual Memory Map of your platform\r
\r
  This Virtual Memory Map is used by MemoryInitPei Module to initialize\r
  the MMU on your platform.\r
\r
  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR\r
                                    describing a Physical-to-Virtual Memory\r
                                    mapping. This array must be ended by a\r
                                    zero-filled entry.\r
\r
**/\r
VOID\r
ArmPlatformGetVirtualMemoryMap (\r
  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
  )\r
{\r
  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;\r
  EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;\r
  UINTN                         Index = 0;\r
  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;\r
  UINT32                        SysId;\r
  BOOLEAN                       HasSparseMemory;\r
  EFI_VIRTUAL_ADDRESS           SparseMemoryBase;\r
  UINT64                        SparseMemorySize;\r
\r
  ASSERT (VirtualMemoryMap != NULL);\r
\r
  // The FVP model has Sparse memory\r
  SysId = MmioRead32 (ARM_VE_SYS_ID_REG);\r
  if (SysId != ARM_RTSM_SYS_ID) {\r
    HasSparseMemory = TRUE;\r
\r
    ResourceAttributes =\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED;\r
\r
    // Declared the additional DRAM from 2GB to 4GB\r
    SparseMemoryBase = 0x0880000000;\r
    SparseMemorySize = SIZE_2GB;\r
\r
    BuildResourceDescriptorHob (\r
        EFI_RESOURCE_SYSTEM_MEMORY,\r
        ResourceAttributes,\r
        SparseMemoryBase,\r
        SparseMemorySize);\r
  } else {\r
    HasSparseMemory = FALSE;\r
    SparseMemoryBase = 0x0;\r
    SparseMemorySize = 0x0;\r
  }\r
\r
  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)\r
    AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR)\r
                                      * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
  if (VirtualMemoryTable == NULL) {\r
    return;\r
  }\r
\r
  CacheAttributes = (FeaturePcdGet(PcdCacheEnable))\r
                    ? DDR_ATTRIBUTES_CACHED\r
                    : DDR_ATTRIBUTES_UNCACHED;\r
\r
  // ReMap (Either NOR Flash or DRAM)\r
  VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;\r
  VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;\r
  VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;\r
  VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
\r
  // DDR\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
  VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r
  VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r
  VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
\r
  // CPU peripherals. TRM. Manual says not all of them are implemented.\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r
  VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r
  VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;\r
  VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
\r
  // SMB CS0-CS1 - NOR Flash 1 & 2\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
  VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
  VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
  VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
\r
  // SMB CS2 - SRAM\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
  VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
  VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
  VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
\r
  // Peripheral CS2 and CS3\r
  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
  VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
  VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;\r
  VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
\r
  // Map sparse memory region if present\r
  if (HasSparseMemory) {\r
    VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;\r
    VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase;\r
    VirtualMemoryTable[Index].Length = SparseMemorySize;\r
    VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
  }\r
\r
  // End of Table\r
  VirtualMemoryTable[++Index].PhysicalBase = 0;\r
  VirtualMemoryTable[Index].VirtualBase = 0;\r
  VirtualMemoryTable[Index].Length = 0;\r
  VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
\r
  *VirtualMemoryMap = VirtualMemoryTable;\r
}\r