[mirror_edk2.git] / ArmPlatformPkg / Drivers / PL35xSmc / InitializeSMC.S

#\r
#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
#  \r
#  This program and the accompanying materials                          \r
#  are licensed and made available under the terms and conditions of the BSD License         \r
#  which accompanies this distribution.  The full text of the license may be found at        \r
#  http:#opensource.org/licenses/bsd-license.php                                            \r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
#\r
#\r
\r
#include <AsmMacroIoLib.h>\r
#include <Library/PcdLib.h>\r
#include <AutoGen.h>\r
#include <Drivers/PL35xSmc.h>\r
\r
.text\r
\r
#Maintain 8 byte alignment\r
.align 3\r
\r
\r
GCC_ASM_EXPORT(SMCInitializeNOR)\r
GCC_ASM_EXPORT(SMCInitializeSRAM)\r
GCC_ASM_EXPORT(SMCInitializePeripherals)\r
GCC_ASM_EXPORT(SMCInitializeVRAM)\r
\r
\r
# CS0  CS0-Interf0     NOR1 flash on the motherboard\r
# CS1  CS1-Interf0     Reserved for the motherboard\r
# CS2  CS2-Interf0     SRAM on the motherboard\r
# CS3  CS3-Interf0     memory-mapped Ethernet and USB controllers on the motherboard\r
# CS4  CS0-Interf1     NOR2 flash on the motherboard\r
# CS5  CS1-Interf1     memory-mapped peripherals\r
# CS6  CS2-Interf1     memory-mapped peripherals\r
# CS7  CS3-Interf1     system memory-mapped peripherals on the motherboard.\r
\r
// IN r1 SmcBase\r
// IN r2 ChipSelect\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
//       could be overwritten (case of 'r0')\r
ASM_PFX(SMCInitializeNOR):\r
#\r
# Setup NOR1 (CS0-Interface0)\r
#\r
\r
  # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
     #Read cycle timeout = 0xA (0:3)\r
     #Write cycle timeout = 0x3(7:4)\r
     #OE Assertion Delay = 0x9(11:8)\r
     #WE Assertion delay = 0x3(15:12)\r
     #Page cycle timeout = 0x2(19:16)  \r
  LoadConstantToReg (0x0002393A,r0)       @ldr     r0, = 0x0002393A\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
  \r
  # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
     # 0x00000002 = MemoryWidth: 32bit\r
     # 0x00000028 = ReadMemoryBurstLength:continuous\r
     # 0x00000280 = WriteMemoryBurstLength:continuous\r
     # 0x00000800 = Set Address Valid\r
  LoadConstantToReg (0x00000AAA,r0)       @ldr     r0, = 0x00000AAA\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
\r
 # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
     # 0x00000000 = ChipSelect0-Interface 0\r
     # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x00400000,r0)       @ldr     r0, = 0x00400000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  \r
  bx lr\r
\r
ASM_PFX(SMCInitializeSRAM):\r
#\r
# Setup SRAM (CS2-Interface0)\r
#\r
  LoadConstantToReg (0x00027158,r0)       @ldr     r0, = 0x00027158\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
\r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000800 = Set Address Valid\r
  LoadConstantToReg (0x00000802,r0)       @ldr     r0, = 0x00000802\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
  \r
  # 0x01000000 = ChipSelect2-Interface 0\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x01400000,r0)       @ldr     r0, = 0x01400000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
  bx    lr\r
\r
ASM_PFX(SMCInitializePeripherals):\r
#\r
# USB/Eth/VRAM (CS3-Interface0)\r
#\r
  LoadConstantToReg (0x000CD2AA,r0)      @ldr     r0, = 0x000CD2AA\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000004 = Memory reads are synchronous\r
  # 0x00000040 = Memory writes are synchronous\r
  LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  # 0x01800000 = ChipSelect3-Interface 0\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x01C00000,r0)      @ldr     r0, = 0x01C00000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
#\r
# Setup NOR3 (CS0-Interface1)\r
#\r
  LoadConstantToReg (0x0002393A,r0)      @ldr     r0, = 0x0002393A\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000028 = ReadMemoryBurstLength:continuous\r
  # 0x00000280 = WriteMemoryBurstLength:continuous\r
  # 0x00000800 = Set Address Valid\r
  LoadConstantToReg (0x00000AAA,r0)      @ldr     r0, = 0x00000AAA\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  # 0x02000000 = ChipSelect0-Interface 1\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x02400000,r0)      @ldr     r0, = 0x02400000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
 \r
#\r
# Setup Peripherals (CS3-Interface1)\r
#\r
  LoadConstantToReg (0x00025156,r0)      @ldr     r0, = 0x00025156\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000004 = Memory reads are synchronous\r
  # 0x00000040 = Memory writes are synchronous\r
  LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  # 0x03800000 = ChipSelect3-Interface 1\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x03C00000,r0)      @ldr     r0, = 0x03C00000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  bx    lr\r
\r
// IN r1 SmcBase\r
// IN r2 VideoSRamBase\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
//       could be overwritten (case of 'r0')\r
ASM_PFX(SMCInitializeVRAM):\r
#\r
# Setup VRAM (CS1-Interface0)\r
#\r
  LoadConstantToReg (0x00049249,r0)      @ldr     r0, =  0x00049249\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000004 = Memory reads are synchronous\r
  # 0x00000040 = Memory writes are synchronous\r
  LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  # 0x00800000 = ChipSelect1-Interface 0\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x00C00000,r0)      @ldr     r0, = 0x00C00000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  \r
#\r
# Page mode setup for VRAM\r
#\r
  #read current state \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, [r2, #0]  \r
\r
  #enable page mode \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  LoadConstantToReg (0x00900090,r0)      @ldr     r0, = 0x00900090\r
  str     r0, [r2, #0] \r
\r
  #confirm page mode enabled\r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, [r2, #0]  \r
  \r
  bx    lr\r
  \r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
Commit	Line	Data
633724f4	1	#\r
	2	# Copyright (c) 2011, ARM Limited. All rights reserved.\r
	3	# \r
	4	# This program and the accompanying materials \r
	5	# are licensed and made available under the terms and conditions of the BSD License \r
	6	# which accompanies this distribution. The full text of the license may be found at \r
	7	# http:#opensource.org/licenses/bsd-license.php \r
	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	#\r
	12	#\r
	13	\r
	14	#include <AsmMacroIoLib.h>\r
	15	#include <Library/PcdLib.h>\r
	16	#include <AutoGen.h>\r
	17	#include <Drivers/PL35xSmc.h>\r
	18	\r
	19	.text\r
	20	\r
	21	#Maintain 8 byte alignment\r
	22	.align 3\r
	23	\r
	24	\r
	25	GCC_ASM_EXPORT(SMCInitializeNOR)\r
	26	GCC_ASM_EXPORT(SMCInitializeSRAM)\r
	27	GCC_ASM_EXPORT(SMCInitializePeripherals)\r
	28	GCC_ASM_EXPORT(SMCInitializeVRAM)\r
	29	\r
	30	\r
	31	# CS0 CS0-Interf0 NOR1 flash on the motherboard\r
	32	# CS1 CS1-Interf0 Reserved for the motherboard\r
	33	# CS2 CS2-Interf0 SRAM on the motherboard\r
	34	# CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
	35	# CS4 CS0-Interf1 NOR2 flash on the motherboard\r
	36	# CS5 CS1-Interf1 memory-mapped peripherals\r
	37	# CS6 CS2-Interf1 memory-mapped peripherals\r
	38	# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
	39	\r
	40	// IN r1 SmcBase\r
	41	// IN r2 ChipSelect\r
	42	// NOTE: This code is been called before any stack has been setup. It means some registers\r
	43	// could be overwritten (case of 'r0')\r
	44	ASM_PFX(SMCInitializeNOR):\r
	45	#\r
	46	# Setup NOR1 (CS0-Interface0)\r
	47	#\r
	48	\r
	49	# Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
	50	#Read cycle timeout = 0xA (0:3)\r
	51	#Write cycle timeout = 0x3(7:4)\r
	52	#OE Assertion Delay = 0x9(11:8)\r
	53	#WE Assertion delay = 0x3(15:12)\r
	54	#Page cycle timeout = 0x2(19:16) \r
	55	LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
	56	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
	57	\r
	58	# Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
	59	# 0x00000002 = MemoryWidth: 32bit\r
	60	# 0x00000028 = ReadMemoryBurstLength:continuous\r
	61	# 0x00000280 = WriteMemoryBurstLength:continuous\r
	62	# 0x00000800 = Set Address Valid\r
	63	LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
	64	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
65	\r
66	# Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
67	# 0x00000000 = ChipSelect0-Interface 0\r
68	# 0x00400000 = CmdTypes: UpdateRegs\r
69	LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000\r
70	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
71	\r
72	bx lr\r
73	\r
74	ASM_PFX(SMCInitializeSRAM):\r
75	#\r
76	# Setup SRAM (CS2-Interface0)\r
77	#\r
78	LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158\r
79	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
80	\r
81	# 0x00000002 = MemoryWidth: 32bit\r
82	# 0x00000800 = Set Address Valid\r
83	LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802\r
84	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
85	\r
86	# 0x01000000 = ChipSelect2-Interface 0\r
87	# 0x00400000 = CmdTypes: UpdateRegs\r
88	LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000\r
89	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
90	\r
91	bx lr\r
92	\r
93	ASM_PFX(SMCInitializePeripherals):\r
94	#\r
95	# USB/Eth/VRAM (CS3-Interface0)\r
96	#\r
97	LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA\r
98	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
99	\r
100	# 0x00000002 = MemoryWidth: 32bit\r
101	# 0x00000004 = Memory reads are synchronous\r
102	# 0x00000040 = Memory writes are synchronous\r
103	LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
104	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
105	\r
106	# 0x01800000 = ChipSelect3-Interface 0\r
107	# 0x00400000 = CmdTypes: UpdateRegs\r
108	LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000\r
109	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
110	\r
111	#\r
112	# Setup NOR3 (CS0-Interface1)\r
113	#\r
114	LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
115	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
116	\r
117	# 0x00000002 = MemoryWidth: 32bit\r
118	# 0x00000028 = ReadMemoryBurstLength:continuous\r
119	# 0x00000280 = WriteMemoryBurstLength:continuous\r
120	# 0x00000800 = Set Address Valid\r
121	LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
122	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
123	\r
124	# 0x02000000 = ChipSelect0-Interface 1\r
125	# 0x00400000 = CmdTypes: UpdateRegs\r
126	LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000\r
127	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
128	\r
129	#\r
130	# Setup Peripherals (CS3-Interface1)\r
131	#\r
132	LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156\r
133	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
134	\r
135	# 0x00000002 = MemoryWidth: 32bit\r
136	# 0x00000004 = Memory reads are synchronous\r
137	# 0x00000040 = Memory writes are synchronous\r
138	LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
139	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
140	\r
141	# 0x03800000 = ChipSelect3-Interface 1\r
142	# 0x00400000 = CmdTypes: UpdateRegs\r
143	LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000\r
144	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
145	bx lr\r
146	\r
147	// IN r1 SmcBase\r
148	// IN r2 VideoSRamBase\r
149	// NOTE: This code is been called before any stack has been setup. It means some registers\r
150	// could be overwritten (case of 'r0')\r
151	ASM_PFX(SMCInitializeVRAM):\r
152	#\r
153	# Setup VRAM (CS1-Interface0)\r
154	#\r
155	LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249\r
156	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
157	\r
158	# 0x00000002 = MemoryWidth: 32bit\r
159	# 0x00000004 = Memory reads are synchronous\r
160	# 0x00000040 = Memory writes are synchronous\r
161	LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
162	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
163	\r
164	# 0x00800000 = ChipSelect1-Interface 0\r
165	# 0x00400000 = CmdTypes: UpdateRegs\r
166	LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000\r
167	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
168	\r
169	#\r
170	# Page mode setup for VRAM\r
171	#\r
172	#read current state \r
173	ldr r0, [r2, #0] \r
174	ldr r0, [r2, #0] \r
175	LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
176	str r0, [r2, #0] \r
177	ldr r0, [r2, #0] \r
178	\r
179	#enable page mode \r
180	ldr r0, [r2, #0] \r
181	ldr r0, [r2, #0] \r
182	LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
183	str r0, [r2, #0] \r
184	LoadConstantToReg (0x00900090,r0) @ldr r0, = 0x00900090\r
185	str r0, [r2, #0] \r
186	\r
187	#confirm page mode enabled\r
188	ldr r0, [r2, #0] \r
189	ldr r0, [r2, #0] \r
190	LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
191	str r0, [r2, #0] \r
192	ldr r0, [r2, #0] \r
193	\r
194	bx lr\r
195	\r
196	ASM_FUNCTION_REMOVE_IF_UNREFERENCED