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[mirror_edk2.git] / ArmPlatformPkg / Include / Library / LcdPlatformLib.h
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7d0f2f23 1/** @file\r
2\r
b1b69d26 3 Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r
7d0f2f23 4 This program and the accompanying materials\r
5 are licensed and made available under the terms and conditions of the BSD License\r
6 which accompanies this distribution. The full text of the license may be found at\r
7 http://opensource.org/licenses/bsd-license.php\r
8\r
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11\r
12 **/\r
13\r
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14#ifndef LCD_PLATFORM_LIB_H_\r
15#define LCD_PLATFORM_LIB_H_\r
7d0f2f23 16\r
17#include <Protocol/GraphicsOutput.h>\r
18\r
19#define LCD_VRAM_SIZE SIZE_8MB\r
20\r
7d0f2f23 21// Modes definitions\r
7d0f2f23 22#define VGA 0\r
23#define SVGA 1\r
24#define XGA 2\r
25#define SXGA 3\r
beeb44f4 26#define WSXGA 4\r
27#define UXGA 5\r
28#define HD 6\r
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29#define WVGA 7\r
30#define QHD 8\r
31#define WSVGA 9\r
32#define HD720 10\r
33#define WXGA 11\r
7d0f2f23 34\r
7d0f2f23 35// VGA Mode: 640 x 480\r
7d0f2f23 36#define VGA_H_RES_PIXELS 640\r
37#define VGA_V_RES_PIXELS 480\r
38#define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */\r
39\r
40#define VGA_H_SYNC ( 80 - 1)\r
41#define VGA_H_FRONT_PORCH ( 16 - 1)\r
42#define VGA_H_BACK_PORCH ( 64 - 1)\r
43\r
44#define VGA_V_SYNC ( 4 - 1)\r
45#define VGA_V_FRONT_PORCH ( 3 - 1)\r
46#define VGA_V_BACK_PORCH ( 13 - 1)\r
47\r
7d0f2f23 48// SVGA Mode: 800 x 600\r
7d0f2f23 49#define SVGA_H_RES_PIXELS 800\r
50#define SVGA_V_RES_PIXELS 600\r
51#define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */\r
52\r
53#define SVGA_H_SYNC ( 80 - 1)\r
54#define SVGA_H_FRONT_PORCH ( 32 - 1)\r
55#define SVGA_H_BACK_PORCH (112 - 1)\r
56\r
57#define SVGA_V_SYNC ( 4 - 1)\r
58#define SVGA_V_FRONT_PORCH ( 3 - 1)\r
59#define SVGA_V_BACK_PORCH ( 17 - 1)\r
60\r
7d0f2f23 61// XGA Mode: 1024 x 768\r
7d0f2f23 62#define XGA_H_RES_PIXELS 1024\r
63#define XGA_V_RES_PIXELS 768\r
64#define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */\r
65\r
66#define XGA_H_SYNC (104 - 1)\r
67#define XGA_H_FRONT_PORCH ( 48 - 1)\r
68#define XGA_H_BACK_PORCH (152 - 1)\r
69\r
70#define XGA_V_SYNC ( 4 - 1)\r
71#define XGA_V_FRONT_PORCH ( 3 - 1)\r
72#define XGA_V_BACK_PORCH ( 23 - 1)\r
73\r
7d0f2f23 74// SXGA Mode: 1280 x 1024\r
7d0f2f23 75#define SXGA_H_RES_PIXELS 1280\r
76#define SXGA_V_RES_PIXELS 1024\r
77#define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */\r
78\r
79#define SXGA_H_SYNC (136 - 1)\r
80#define SXGA_H_FRONT_PORCH ( 80 - 1)\r
81#define SXGA_H_BACK_PORCH (216 - 1)\r
82\r
83#define SXGA_V_SYNC ( 7 - 1)\r
84#define SXGA_V_FRONT_PORCH ( 3 - 1)\r
85#define SXGA_V_BACK_PORCH ( 29 - 1)\r
86\r
beeb44f4 87// WSXGA+ Mode: 1680 x 1050\r
beeb44f4 88#define WSXGA_H_RES_PIXELS 1680\r
89#define WSXGA_V_RES_PIXELS 1050\r
90#define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */\r
91\r
92#define WSXGA_H_SYNC (170 - 1)\r
93#define WSXGA_H_FRONT_PORCH (104 - 1)\r
94#define WSXGA_H_BACK_PORCH (274 - 1)\r
95\r
96#define WSXGA_V_SYNC ( 5 - 1)\r
97#define WSXGA_V_FRONT_PORCH ( 4 - 1)\r
98#define WSXGA_V_BACK_PORCH ( 41 - 1)\r
99\r
7d0f2f23 100// UXGA Mode: 1600 x 1200\r
7d0f2f23 101#define UXGA_H_RES_PIXELS 1600\r
102#define UXGA_V_RES_PIXELS 1200\r
103#define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */\r
104\r
105#define UXGA_H_SYNC (168 - 1)\r
106#define UXGA_H_FRONT_PORCH (112 - 1)\r
107#define UXGA_H_BACK_PORCH (280 - 1)\r
108\r
109#define UXGA_V_SYNC ( 4 - 1)\r
110#define UXGA_V_FRONT_PORCH ( 3 - 1)\r
111#define UXGA_V_BACK_PORCH ( 38 - 1)\r
112\r
7d0f2f23 113// HD Mode: 1920 x 1080\r
7d0f2f23 114#define HD_H_RES_PIXELS 1920\r
115#define HD_V_RES_PIXELS 1080\r
deb8a061 116#define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */\r
7d0f2f23 117\r
deb8a061 118#define HD_H_SYNC ( 79 - 1)\r
7d0f2f23 119#define HD_H_FRONT_PORCH (128 - 1)\r
120#define HD_H_BACK_PORCH (328 - 1)\r
121\r
122#define HD_V_SYNC ( 5 - 1)\r
123#define HD_V_FRONT_PORCH ( 3 - 1)\r
124#define HD_V_BACK_PORCH ( 32 - 1)\r
125\r
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126// WVGA Mode: 800 x 480\r
127#define WVGA_H_RES_PIXELS 800\r
128#define WVGA_V_RES_PIXELS 480\r
129#define WVGA_OSC_FREQUENCY 29500000 /* 0x01C22260 */\r
130#define WVGA_H_SYNC ( 72 - 1)\r
131#define WVGA_H_FRONT_PORCH ( 24 - 1)\r
132#define WVGA_H_BACK_PORCH ( 96 - 1)\r
133#define WVGA_V_SYNC ( 7 - 1)\r
134#define WVGA_V_FRONT_PORCH ( 3 - 1)\r
135#define WVGA_V_BACK_PORCH ( 10 - 1)\r
136\r
137// QHD Mode: 960 x 540\r
138#define QHD_H_RES_PIXELS 960\r
139#define QHD_V_RES_PIXELS 540\r
140#define QHD_OSC_FREQUENCY 40750000 /* 0x026DCBB0 */\r
141#define QHD_H_SYNC ( 96 - 1)\r
142#define QHD_H_FRONT_PORCH ( 32 - 1)\r
143#define QHD_H_BACK_PORCH (128 - 1)\r
144#define QHD_V_SYNC ( 5 - 1)\r
145#define QHD_V_FRONT_PORCH ( 3 - 1)\r
146#define QHD_V_BACK_PORCH ( 14 - 1)\r
147\r
148// WSVGA Mode: 1024 x 600\r
149#define WSVGA_H_RES_PIXELS 1024\r
150#define WSVGA_V_RES_PIXELS 600\r
151#define WSVGA_OSC_FREQUENCY 49000000 /* 0x02EBAE40 */\r
152#define WSVGA_H_SYNC (104 - 1)\r
153#define WSVGA_H_FRONT_PORCH ( 40 - 1)\r
154#define WSVGA_H_BACK_PORCH (144 - 1)\r
155#define WSVGA_V_SYNC ( 10 - 1)\r
156#define WSVGA_V_FRONT_PORCH ( 3 - 1)\r
157#define WSVGA_V_BACK_PORCH ( 11 - 1)\r
158\r
159// HD720 Mode: 1280 x 720\r
160#define HD720_H_RES_PIXELS 1280\r
161#define HD720_V_RES_PIXELS 720\r
162#define HD720_OSC_FREQUENCY 74500000 /* 0x0470C7A0 */\r
163#define HD720_H_SYNC (128 - 1)\r
164#define HD720_H_FRONT_PORCH ( 64 - 1)\r
165#define HD720_H_BACK_PORCH (192 - 1)\r
166#define HD720_V_SYNC ( 5 - 1)\r
167#define HD720_V_FRONT_PORCH ( 3 - 1)\r
168#define HD720_V_BACK_PORCH ( 20 - 1)\r
169\r
170// WXGA Mode: 1280 x 800\r
171#define WXGA_H_RES_PIXELS 1280\r
172#define WXGA_V_RES_PIXELS 800\r
173#define WXGA_OSC_FREQUENCY 83500000 /* 0x04FA1BE0 */\r
174#define WXGA_H_SYNC (128 - 1)\r
175#define WXGA_H_FRONT_PORCH ( 72 - 1)\r
176#define WXGA_H_BACK_PORCH (200 - 1)\r
177#define WXGA_V_SYNC ( 6 - 1)\r
178#define WXGA_V_FRONT_PORCH ( 3 - 1)\r
179#define WXGA_V_BACK_PORCH ( 22 - 1)\r
180\r
7d0f2f23 181// Colour Masks\r
7d0f2f23 182#define LCD_24BPP_RED_MASK 0x00FF0000\r
183#define LCD_24BPP_GREEN_MASK 0x0000FF00\r
184#define LCD_24BPP_BLUE_MASK 0x000000FF\r
185#define LCD_24BPP_RESERVED_MASK 0xFF000000\r
186\r
187#define LCD_16BPP_555_RED_MASK 0x00007C00\r
188#define LCD_16BPP_555_GREEN_MASK 0x000003E0\r
189#define LCD_16BPP_555_BLUE_MASK 0x0000001F\r
190#define LCD_16BPP_555_RESERVED_MASK 0x00000000\r
191\r
192#define LCD_16BPP_565_RED_MASK 0x0000F800\r
193#define LCD_16BPP_565_GREEN_MASK 0x000007E0\r
194#define LCD_16BPP_565_BLUE_MASK 0x0000001F\r
195#define LCD_16BPP_565_RESERVED_MASK 0x00008000\r
196\r
197#define LCD_12BPP_444_RED_MASK 0x00000F00\r
198#define LCD_12BPP_444_GREEN_MASK 0x000000F0\r
199#define LCD_12BPP_444_BLUE_MASK 0x0000000F\r
200#define LCD_12BPP_444_RESERVED_MASK 0x0000F000\r
201\r
4257dfaa 202/** The enumeration maps the PL111 LcdBpp values used in the LCD Control\r
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203 Register\r
204**/\r
7d0f2f23 205typedef enum {\r
206 LCD_BITS_PER_PIXEL_1 = 0,\r
207 LCD_BITS_PER_PIXEL_2,\r
208 LCD_BITS_PER_PIXEL_4,\r
209 LCD_BITS_PER_PIXEL_8,\r
210 LCD_BITS_PER_PIXEL_16_555,\r
211 LCD_BITS_PER_PIXEL_24,\r
212 LCD_BITS_PER_PIXEL_16_565,\r
213 LCD_BITS_PER_PIXEL_12_444\r
214} LCD_BPP;\r
215\r
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216// Display timing settings.\r
217typedef struct {\r
218 UINT32 Resolution;\r
219 UINT32 Sync;\r
220 UINT32 BackPorch;\r
221 UINT32 FrontPorch;\r
222} SCAN_TIMINGS;\r
223\r
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224/** Platform related initialization function.\r
225\r
226 @param[in] Handle Handle to the LCD device instance.\r
227\r
228 @retval EFI_SUCCESS Plaform library initialized successfully.\r
229 @retval !(EFI_SUCCESS) Other errors.\r
230**/\r
7d0f2f23 231EFI_STATUS\r
232LcdPlatformInitializeDisplay (\r
6d8d7363 233 IN EFI_HANDLE Handle\r
7d0f2f23 234 );\r
235\r
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236/** Allocate VRAM memory in DRAM for the framebuffer\r
237 (unless it is reserved already).\r
238\r
239 The allocated address can be used to set the framebuffer.\r
240\r
241 @param[out] VramBaseAddress A pointer to the framebuffer address.\r
242 @param[out] VramSize A pointer to the size of the frame\r
243 buffer in bytes\r
244\r
245 @retval EFI_SUCCESS Frame buffer memory allocated successfully.\r
246 @retval !(EFI_SUCCESS) Other errors.\r
247**/\r
7d0f2f23 248EFI_STATUS\r
249LcdPlatformGetVram (\r
250 OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,\r
251 OUT UINTN* VramSize\r
252 );\r
253\r
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254/** Return total number of modes supported.\r
255\r
256 Note: Valid mode numbers are 0 to MaxMode - 1\r
257 See Section 12.9 of the UEFI Specification 2.7\r
258\r
259 @retval UINT32 Mode Number.\r
260**/\r
7d0f2f23 261UINT32\r
262LcdPlatformGetMaxMode (\r
263 VOID\r
264 );\r
265\r
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266/** Set the requested display mode.\r
267\r
268 @param[in] ModeNumber Mode Number.\r
269\r
270 @retval EFI_SUCCESS Mode set successfully.\r
271 @retval EFI_INVALID_PARAMETER Requested mode not found.\r
272 @retval !(EFI_SUCCESS) Other errors.\r
273**/\r
7d0f2f23 274EFI_STATUS\r
275LcdPlatformSetMode (\r
276 IN UINT32 ModeNumber\r
277 );\r
278\r
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279/** Return information for the requested mode number.\r
280\r
281 @param[in] ModeNumber Mode Number.\r
282 @param[out] Info Pointer for returned mode information\r
283 (on success).\r
284\r
285 @retval EFI_SUCCESS Mode information for the requested mode\r
286 returned successfully.\r
287 @retval EFI_INVALID_PARAMETER Requested mode not found.\r
288**/\r
7d0f2f23 289EFI_STATUS\r
290LcdPlatformQueryMode (\r
291 IN UINT32 ModeNumber,\r
292 OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info\r
293 );\r
294\r
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295/** Return display timing information for the requested mode number.\r
296\r
297 @param[in] ModeNumber Mode Number.\r
298\r
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299 @param[out] Horizontal Pointer to horizontal timing parameters.\r
300 (Resolution, Sync, Back porch, Front porch)\r
301 @param[out] Vertical Pointer to vertical timing parameters.\r
302 (Resolution, Sync, Back porch, Front porch)\r
303\r
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304\r
305 @retval EFI_SUCCESS Display timing information for the requested\r
306 mode returned successfully.\r
307 @retval EFI_INVALID_PARAMETER Requested mode not found.\r
308**/\r
7d0f2f23 309EFI_STATUS\r
310LcdPlatformGetTimings (\r
311 IN UINT32 ModeNumber,\r
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312 OUT SCAN_TIMINGS **Horizontal,\r
313 OUT SCAN_TIMINGS **Vertical\r
7d0f2f23 314 );\r
315\r
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316/** Return bits per pixel information for a mode number.\r
317\r
318 @param[in] ModeNumber Mode Number.\r
319\r
320 @param[out] Bpp Pointer to value bits per pixel information.\r
321\r
322 @retval EFI_SUCCESS Bit per pixel information for the requested\r
323 mode returned successfully.\r
324 @retval EFI_INVALID_PARAMETER Requested mode not found.\r
325**/\r
7d0f2f23 326EFI_STATUS\r
327LcdPlatformGetBpp (\r
328 IN UINT32 ModeNumber,\r
329 OUT LCD_BPP* Bpp\r
330 );\r
331\r
b1b69d26 332#endif /* LCD_PLATFORM_LIB_H_ */\r