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1d5d0ae9 1//\r
2// Copyright (c) 2011, ARM Limited. All rights reserved.\r
3// \r
4// This program and the accompanying materials \r
5// are licensed and made available under the terms and conditions of the BSD License \r
6// which accompanies this distribution. The full text of the license may be found at \r
7// http://opensource.org/licenses/bsd-license.php \r
8//\r
9// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11//\r
12//\r
13\r
14#include <AsmMacroIoLib.h>\r
15#include <Base.h>\r
16#include <Library/PcdLib.h>\r
17#include <AutoGen.h>\r
18\r
19 INCLUDE AsmMacroIoLib.inc\r
20 \r
21 IMPORT CEntryPoint\r
0787bc61 22 IMPORT ArmReadMpidr\r
1d5d0ae9 23 EXPORT _ModuleEntryPoint\r
24 \r
25 PRESERVE8\r
26 AREA PrePeiCoreEntryPoint, CODE, READONLY\r
27 \r
28StartupAddr DCD CEntryPoint\r
29\r
1d5d0ae9 30_ModuleEntryPoint\r
31 // Identify CPU ID\r
0787bc61 32 bl ArmReadMpidr\r
33 // Get ID of this CPU in Multicore system\r
34 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
1377db63 35 and r5, r0, r1\r
36 \r
37 // Get the top of the primary stacks (and the base of the secondary stacks)\r
2dbcb8f0 38 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r
39 LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
1377db63 40 add r1, r1, r2\r
2dbcb8f0 41\r
42 // Is it the Primary Core ?\r
1377db63 43 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
44 cmp r5, r3\r
2dbcb8f0 45 beq _SetupPrimaryCoreStack\r
46\r
47_SetupSecondaryCoreStack\r
1377db63 48 // r1 contains the base of the secondary stacks\r
2dbcb8f0 49\r
1377db63 50 // Get the Core Position (ClusterId * 4) + CoreId\r
a32dae48 51 GetCorePositionFromMpId(r0, r5, r2)\r
2dbcb8f0 52 // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
1377db63 53 add r0, r0, #1\r
1d5d0ae9 54\r
2dbcb8f0 55 // StackOffset = CorePos * StackSize\r
1377db63 56 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2)\r
57 mul r0, r0, r2\r
2dbcb8f0 58 // SP = StackBase + StackOffset\r
1377db63 59 add sp, r1, r0\r
47a8e12f 60\r
61_PrepareArguments\r
1d5d0ae9 62 // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
f92b93c9 63 LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)\r
1d5d0ae9 64 add r2, r2, #4\r
65 ldr r1, [r2]\r
66\r
1377db63 67 // Move sec startup address into a data register\r
68 // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
69 ldr r3, StartupAddr\r
70 \r
71 // Jump to PrePeiCore C code\r
0787bc61 72 // r0 = mp_id\r
1d5d0ae9 73 // r1 = pei_core_address\r
1377db63 74 mov r0, r5\r
75 blx r3\r
76\r
77_SetupPrimaryCoreStack\r
78 // r1 contains the top of the primary stack\r
79 LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2)\r
80\r
81 // The reserved space for global variable must be 8-bytes aligned for pushing\r
82 // 64-bit variable on the stack\r
83 SetPrimaryStack (r1, r2, r3)\r
84 b _PrepareArguments\r
1d5d0ae9 85\r
2dbcb8f0 86_NeverReturn\r
87 b _NeverReturn\r
88\r
1d5d0ae9 89 END\r