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1d5d0ae9 | 1 | /** @file\r |
2 | *\r | |
1b0ac0de | 3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
1d5d0ae9 | 4 | *\r |
f4dfad05 | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1d5d0ae9 | 6 | *\r |
7 | **/\r | |
8 | \r | |
55a0d64b | 9 | #include <Library/ArmGicLib.h>\r |
44788bae | 10 | \r |
11 | #include <Ppi/ArmMpCoreInfo.h>\r | |
12 | \r | |
f598bf12 | 13 | #include "PrePeiCore.h"\r |
14 | \r | |
1d5d0ae9 | 15 | /*\r |
16 | * This is the main function for secondary cores. They loop around until a non Null value is written to\r | |
17 | * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r | |
18 | * Note:The secondary cores, while executing secondary_main, assumes that:\r | |
19 | * : SGI 0 is configured as Non-secure interrupt\r | |
20 | * : Priority Mask is configured to allow SGI 0\r | |
21 | * : Interrupt Distributor and CPU interfaces are enabled\r | |
22 | *\r | |
23 | */\r | |
24 | VOID\r | |
25 | EFIAPI\r | |
f598bf12 | 26 | SecondaryMain (\r |
0787bc61 | 27 | IN UINTN MpId\r |
f598bf12 | 28 | )\r |
1d5d0ae9 | 29 | {\r |
44788bae | 30 | EFI_STATUS Status;\r |
31 | UINTN PpiListSize;\r | |
32 | UINTN PpiListCount;\r | |
33 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
34 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
35 | UINTN Index;\r | |
36 | UINTN ArmCoreCount;\r | |
37 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
38 | UINT32 ClusterId;\r | |
39 | UINT32 CoreId;\r | |
40 | VOID (*SecondaryStart)(VOID);\r | |
41 | UINTN SecondaryEntryAddr;\r | |
1b0ac0de OM |
42 | UINTN AcknowledgeInterrupt;\r |
43 | UINTN InterruptId;\r | |
44788bae | 44 | \r |
45 | ClusterId = GET_CLUSTER_ID(MpId);\r | |
46 | CoreId = GET_CORE_ID(MpId);\r | |
47 | \r | |
48 | // Get the gArmMpCoreInfoPpiGuid\r | |
49 | PpiListSize = 0;\r | |
50 | ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r | |
51 | PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r | |
52 | for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r | |
53 | if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {\r | |
54 | break;\r | |
55 | }\r | |
56 | }\r | |
57 | \r | |
58 | // On MP Core Platform we must implement the ARM MP Core Info PPI\r | |
59 | ASSERT (Index != PpiListCount);\r | |
60 | \r | |
61 | ArmMpCoreInfoPpi = PpiList->Ppi;\r | |
62 | ArmCoreCount = 0;\r | |
63 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
64 | ASSERT_EFI_ERROR (Status);\r | |
65 | \r | |
66 | // Find the core in the ArmCoreTable\r | |
67 | for (Index = 0; Index < ArmCoreCount; Index++) {\r | |
68 | if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r | |
69 | break;\r | |
70 | }\r | |
71 | }\r | |
72 | \r | |
73 | // The ARM Core Info Table must define every core\r | |
74 | ASSERT (Index != ArmCoreCount);\r | |
1d5d0ae9 | 75 | \r |
f598bf12 | 76 | // Clear Secondary cores MailBox\r |
44788bae | 77 | MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r |
1d5d0ae9 | 78 | \r |
315649cd | 79 | do {\r |
44788bae | 80 | ArmCallWFI ();\r |
315649cd | 81 | \r |
82 | // Read the Mailbox\r | |
83 | SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r | |
84 | \r | |
f598bf12 | 85 | // Acknowledge the interrupt and send End of Interrupt signal.\r |
8a1f2378 | 86 | AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);\r |
2ca815a4 | 87 | // Check if it is a valid interrupt ID\r |
8a1f2378 | 88 | if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {\r |
2ca815a4 | 89 | // Got a valid SGI number hence signal End of Interrupt\r |
8a1f2378 | 90 | ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r |
2ca815a4 | 91 | }\r |
f93f248a | 92 | } while (SecondaryEntryAddr == 0);\r |
1d5d0ae9 | 93 | \r |
f598bf12 | 94 | // Jump to secondary core entry point.\r |
44788bae | 95 | SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r |
96 | SecondaryStart();\r | |
1d5d0ae9 | 97 | \r |
f598bf12 | 98 | // The secondaries shouldn't reach here\r |
99 | ASSERT(FALSE);\r | |
1d5d0ae9 | 100 | }\r |
101 | \r | |
f598bf12 | 102 | VOID\r |
103 | EFIAPI\r | |
104 | PrimaryMain (\r | |
1d5d0ae9 | 105 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
106 | )\r | |
107 | {\r | |
f598bf12 | 108 | EFI_SEC_PEI_HAND_OFF SecCoreData;\r |
77de7e53 | 109 | UINTN PpiListSize;\r |
110 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
111 | UINTN TemporaryRamBase;\r | |
112 | UINTN TemporaryRamSize;\r | |
113 | \r | |
114 | CreatePpiList (&PpiListSize, &PpiList);\r | |
1d5d0ae9 | 115 | \r |
55a0d64b | 116 | // Enable the GIC Distributor\r |
8a1f2378 | 117 | ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));\r |
1d5d0ae9 | 118 | \r |
f598bf12 | 119 | // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r |
55a0d64b | 120 | if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r |
f598bf12 | 121 | // Sending SGI to all the Secondary CPU interfaces\r |
8a1f2378 | 122 | ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r |
f598bf12 | 123 | }\r |
1d5d0ae9 | 124 | \r |
77de7e53 | 125 | // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r |
126 | // the base of the primary core stack\r | |
7945b29c | 127 | PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);\r |
bb5420bb | 128 | TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r |
77de7e53 | 129 | TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r |
130 | \r | |
f598bf12 | 131 | //\r |
132 | // Bind this information into the SEC hand-off state\r | |
133 | // Note: this must be in sync with the stuff in the asm file\r | |
134 | // Note also: HOBs (pei temp ram) MUST be above stack\r | |
135 | //\r | |
136 | SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r | |
bb5420bb | 137 | SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r |
f92b93c9 | 138 | SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r |
77de7e53 | 139 | SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r |
140 | SecCoreData.TemporaryRamSize = TemporaryRamSize;\r | |
141 | SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r | |
7945b29c | 142 | SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r |
bc299a9f | 143 | SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r |
3222e7b1 | 144 | SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r |
1d5d0ae9 | 145 | \r |
f598bf12 | 146 | // Jump to PEI core entry point\r |
6f711615 | 147 | PeiCoreEntryPoint (&SecCoreData, PpiList);\r |
1d5d0ae9 | 148 | }\r |