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1d5d0ae9 | 1 | /** @file\r |
2 | * Main file supporting the transition to PEI Core in Normal World for Versatile Express\r | |
3 | *\r | |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
5 | * \r | |
6 | * This program and the accompanying materials \r | |
7 | * are licensed and made available under the terms and conditions of the BSD License \r | |
8 | * which accompanies this distribution. The full text of the license may be found at \r | |
9 | * http://opensource.org/licenses/bsd-license.php \r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | *\r | |
14 | **/\r | |
15 | \r | |
1d5d0ae9 | 16 | #include <Library/IoLib.h>\r |
17 | #include <Library/BaseLib.h>\r | |
18 | #include <Library/BaseMemoryLib.h>\r | |
a6caee65 | 19 | #include <Library/DebugAgentLib.h>\r |
f598bf12 | 20 | #include <Library/PrintLib.h>\r |
1d5d0ae9 | 21 | #include <Library/ArmLib.h>\r |
f598bf12 | 22 | #include <Library/SerialPortLib.h>\r |
1d5d0ae9 | 23 | #include <Chipset/ArmV7.h>\r |
24 | \r | |
f598bf12 | 25 | #include "PrePeiCore.h"\r |
1d5d0ae9 | 26 | \r |
80ddb68d | 27 | EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};\r |
1d5d0ae9 | 28 | \r |
29 | EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {\r | |
30 | {\r | |
31 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
32 | &gEfiTemporaryRamSupportPpiGuid,\r | |
33 | &mSecTemporaryRamSupportPpi\r | |
34 | }\r | |
35 | };\r | |
36 | \r | |
1d5d0ae9 | 37 | VOID\r |
38 | CEntryPoint (\r | |
0787bc61 | 39 | IN UINTN MpId,\r |
1d5d0ae9 | 40 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
41 | )\r | |
42 | {\r | |
43 | //Clean Data cache\r | |
44 | ArmCleanInvalidateDataCache();\r | |
45 | \r | |
46 | //Invalidate instruction cache\r | |
47 | ArmInvalidateInstructionCache();\r | |
48 | \r | |
49 | // Enable Instruction & Data caches\r | |
f598bf12 | 50 | ArmEnableDataCache ();\r |
51 | ArmEnableInstructionCache ();\r | |
1d5d0ae9 | 52 | \r |
53 | //\r | |
54 | // Note: Doesn't have to Enable CPU interface in non-secure world,\r | |
55 | // as Non-secure interface is already enabled in Secure world.\r | |
56 | //\r | |
57 | \r | |
58 | // Write VBAR - The Vector table must be 32-byte aligned\r | |
59 | ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);\r | |
60 | ArmWriteVBar((UINT32)PeiVectorTable);\r | |
61 | \r | |
62 | //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r | |
63 | \r | |
64 | //If not primary Jump to Secondary Main\r | |
0787bc61 | 65 | if (IS_PRIMARY_CORE(MpId)) {\r |
a6caee65 | 66 | // Initialize the Debug Agent for Source Level Debugging\r |
67 | InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r | |
68 | SaveAndSetDebugTimerInterrupt (TRUE);\r | |
69 | \r | |
70 | // Goto primary Main.\r | |
f598bf12 | 71 | PrimaryMain (PeiCoreEntryPoint);\r |
1d5d0ae9 | 72 | } else {\r |
0787bc61 | 73 | SecondaryMain (MpId);\r |
1d5d0ae9 | 74 | }\r |
75 | \r | |
76 | // PEI Core should always load and never return\r | |
77 | ASSERT (FALSE);\r | |
78 | }\r | |
79 | \r | |
80 | EFI_STATUS\r | |
81 | EFIAPI\r | |
82 | SecTemporaryRamSupport (\r | |
83 | IN CONST EFI_PEI_SERVICES **PeiServices,\r | |
84 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r | |
85 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r | |
86 | IN UINTN CopySize\r | |
87 | )\r | |
88 | {\r | |
89 | //\r | |
90 | // Migrate the whole temporary memory to permenent memory.\r | |
f598bf12 | 91 | //\r |
1d5d0ae9 | 92 | CopyMem (\r |
93 | (VOID*)(UINTN)PermanentMemoryBase, \r | |
94 | (VOID*)(UINTN)TemporaryMemoryBase, \r | |
95 | CopySize\r | |
96 | );\r | |
97 | \r | |
98 | SecSwitchStack((UINTN)(PermanentMemoryBase - TemporaryMemoryBase));\r | |
99 | \r | |
100 | return EFI_SUCCESS;\r | |
101 | }\r | |
102 | \r | |
2637d1ef | 103 | VOID\r |
104 | PeiCommonExceptionEntry (\r | |
105 | IN UINT32 Entry,\r | |
106 | IN UINT32 LR\r | |
107 | )\r | |
108 | {\r | |
109 | CHAR8 Buffer[100];\r | |
110 | UINTN CharCount;\r | |
111 | \r | |
1d5d0ae9 | 112 | switch (Entry) {\r |
113 | case 0:\r | |
2637d1ef | 114 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);\r |
1d5d0ae9 | 115 | break;\r |
116 | case 1:\r | |
2637d1ef | 117 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);\r |
1d5d0ae9 | 118 | break;\r |
119 | case 2:\r | |
2637d1ef | 120 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);\r |
1d5d0ae9 | 121 | break;\r |
122 | case 3:\r | |
2637d1ef | 123 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);\r |
1d5d0ae9 | 124 | break;\r |
125 | case 4:\r | |
2637d1ef | 126 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);\r |
1d5d0ae9 | 127 | break;\r |
128 | case 5:\r | |
2637d1ef | 129 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);\r |
1d5d0ae9 | 130 | break;\r |
131 | case 6:\r | |
2637d1ef | 132 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);\r |
1d5d0ae9 | 133 | break;\r |
134 | case 7:\r | |
2637d1ef | 135 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);\r |
1d5d0ae9 | 136 | break;\r |
137 | default:\r | |
2637d1ef | 138 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);\r |
1d5d0ae9 | 139 | break;\r |
140 | }\r | |
2637d1ef | 141 | SerialPortWrite ((UINT8 *) Buffer, CharCount);\r |
1d5d0ae9 | 142 | while(1);\r |
143 | }\r |