[mirror_edk2.git] / ArmVirtPkg / PciHostBridgeDxe / PciHostBridge.c

/** @file\r
  Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation\r
\r
Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are\r
licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PciHostBridge.h"\r
\r
//\r
// Hard code: Root Bridge Number within the host bridge\r
//            Root Bridge's attribute\r
//            Root Bridge's device path\r
//            Root Bridge's resource aperture\r
//\r
UINTN RootBridgeNumber[1] = { 1 };\r
\r
UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };\r
\r
EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {\r
  {\r
    {\r
      {\r
        {\r
          ACPI_DEVICE_PATH,\r
          ACPI_DP,\r
          {\r
            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
          }\r
        },\r
        EISA_PNP_ID(0x0A03),\r
        0\r
      },\r
\r
      {\r
        END_DEVICE_PATH_TYPE,\r
        END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
        {\r
          END_DEVICE_PATH_LENGTH,\r
          0\r
        }\r
      }\r
    }\r
  }\r
};\r
\r
STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE  mResAperture[1][1];\r
\r
EFI_HANDLE mDriverImageHandle;\r
\r
PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {\r
  PCI_HOST_BRIDGE_SIGNATURE,  // Signature\r
  NULL,                       // HostBridgeHandle\r
  0,                          // RootBridgeNumber\r
  {NULL, NULL},               // Head\r
  FALSE,                      // ResourceSubiteed\r
  TRUE,                       // CanRestarted\r
  {\r
    NotifyPhase,\r
    GetNextRootBridge,\r
    GetAttributes,\r
    StartBusEnumeration,\r
    SetBusNumbers,\r
    SubmitResources,\r
    GetProposedResources,\r
    PreprocessController\r
  }\r
};\r
\r
//\r
// Implementation\r
//\r
\r
STATIC\r
VOID\r
SetLinuxPciProbeOnlyProperty (\r
  IN FDT_CLIENT_PROTOCOL         *FdtClient\r
  )\r
{\r
  INT32         Node;\r
  UINT32        Tmp;\r
  EFI_STATUS    Status;\r
\r
  if (!FeaturePcdGet (PcdPureAcpiBoot)) {\r
    //\r
    // Set the /chosen/linux,pci-probe-only property to 1, so that the PCI\r
    // setup we will perform in the firmware is honored by the Linux OS,\r
    // rather than torn down and done from scratch. This is generally a more\r
    // sensible approach, and aligns with what ACPI based OSes do typically.\r
    //\r
    // In case we are exposing an emulated VGA PCI device to the guest, which\r
    // may subsequently get exposed via the Graphics Output protocol and\r
    // driven as an efifb by Linux, we need this setting to prevent the\r
    // framebuffer from becoming unresponsive.\r
    //\r
    Status = FdtClient->GetOrInsertChosenNode (FdtClient, &Node);\r
\r
    if (!EFI_ERROR (Status)) {\r
      Tmp = SwapBytes32 (1);\r
      Status = FdtClient->SetNodeProperty (FdtClient, Node,\r
                            "linux,pci-probe-only", &Tmp, sizeof (Tmp));\r
    }\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((EFI_D_WARN,\r
        "Failed to set /chosen/linux,pci-probe-only property\n"));\r
    }\r
  }\r
}\r
\r
//\r
// We expect the "ranges" property of "pci-host-ecam-generic" to consist of\r
// records like this.\r
//\r
#pragma pack (1)\r
typedef struct {\r
  UINT32 Type;\r
  UINT64 ChildBase;\r
  UINT64 CpuBase;\r
  UINT64 Size;\r
} DTB_PCI_HOST_RANGE_RECORD;\r
#pragma pack ()\r
\r
#define DTB_PCI_HOST_RANGE_RELOCATABLE  BIT31\r
#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30\r
#define DTB_PCI_HOST_RANGE_ALIASED      BIT29\r
#define DTB_PCI_HOST_RANGE_MMIO32       BIT25\r
#define DTB_PCI_HOST_RANGE_MMIO64       (BIT25 | BIT24)\r
#define DTB_PCI_HOST_RANGE_IO           BIT24\r
#define DTB_PCI_HOST_RANGE_TYPEMASK     (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)\r
\r
STATIC\r
EFI_STATUS\r
ProcessPciHost (\r
  OUT  UINT64    *IoBase,\r
  OUT  UINT64    *IoSize,\r
  OUT  UINT64    *IoTranslation,\r
  OUT  UINT64    *MmioBase,\r
  OUT  UINT64    *MmioSize,\r
  OUT  UINT64    *MmioTranslation,\r
  OUT  UINT32    *BusMin,\r
  OUT  UINT32    *BusMax\r
  )\r
{\r
  FDT_CLIENT_PROTOCOL         *FdtClient;\r
  INT32                       Node;\r
  UINT64                      ConfigBase, ConfigSize;\r
  CONST VOID                  *Prop;\r
  UINT32                      Len;\r
  UINT32                      RecordIdx;\r
  EFI_STATUS                  Status;\r
\r
  //\r
  // The following output arguments are initialized only in\r
  // order to suppress '-Werror=maybe-uninitialized' warnings\r
  // *incorrectly* emitted by some gcc versions.\r
  //\r
  *IoBase = 0;\r
  *IoTranslation = 0;\r
  *MmioBase = 0;\r
  *MmioTranslation = 0;\r
  *BusMin = 0;\r
  *BusMax = 0;\r
\r
  //\r
  // *IoSize and *MmioSize are initialized to zero because the logic below\r
  // requires it. However, since they are also affected by the issue reported\r
  // above, they are initialized early.\r
  //\r
  *IoSize = 0;\r
  *MmioSize = 0;\r
\r
  Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,\r
                  (VOID **)&FdtClient);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",\r
                        &Node);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_INFO,\r
      "%a: No 'pci-host-ecam-generic' compatible DT node found\n",\r
      __FUNCTION__));\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  DEBUG_CODE (\r
    INT32 Tmp;\r
\r
    //\r
    // A DT can legally describe multiple PCI host bridges, but we are not\r
    // equipped to deal with that. So assert that there is only one.\r
    //\r
    Status = FdtClient->FindNextCompatibleNode (FdtClient,\r
                          "pci-host-ecam-generic", Node, &Tmp);\r
    ASSERT (Status == EFI_NOT_FOUND);\r
  );\r
\r
  Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);\r
  if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {\r
    DEBUG ((EFI_D_ERROR, "%a: 'reg' property not found or invalid\n",\r
      __FUNCTION__));\r
    return EFI_PROTOCOL_ERROR;\r
  }\r
\r
  //\r
  // Fetch the ECAM window.\r
  //\r
  ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);\r
  ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);\r
\r
  //\r
  // Fetch the bus range (note: inclusive).\r
  //\r
  Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,\r
                        &Len);\r
  if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {\r
    DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",\r
      __FUNCTION__));\r
    return EFI_PROTOCOL_ERROR;\r
  }\r
  *BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);\r
  *BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);\r
\r
  //\r
  // Sanity check: the config space must accommodate all 4K register bytes of\r
  // all 8 functions of all 32 devices of all buses.\r
  //\r
  if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||\r
      DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {\r
    DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",\r
      __FUNCTION__));\r
    return EFI_PROTOCOL_ERROR;\r
  }\r
\r
  //\r
  // Iterate over "ranges".\r
  //\r
  Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);\r
  if (EFI_ERROR (Status) || Len == 0 ||\r
      Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {\r
    DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));\r
    return EFI_PROTOCOL_ERROR;\r
  }\r
\r
  for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);\r
       ++RecordIdx) {\r
    CONST DTB_PCI_HOST_RANGE_RECORD *Record;\r
\r
    Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;\r
    switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {\r
    case DTB_PCI_HOST_RANGE_IO:\r
      *IoBase = SwapBytes64 (Record->ChildBase);\r
      *IoSize = SwapBytes64 (Record->Size);\r
      *IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;\r
      break;\r
\r
    case DTB_PCI_HOST_RANGE_MMIO32:\r
      *MmioBase = SwapBytes64 (Record->ChildBase);\r
      *MmioSize = SwapBytes64 (Record->Size);\r
      *MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase;\r
\r
      if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 ||\r
          *MmioBase + *MmioSize > SIZE_4GB) {\r
        DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));\r
        return EFI_PROTOCOL_ERROR;\r
      }\r
\r
      if (*MmioTranslation != 0) {\r
        DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "\r
          "0x%Lx\n", __FUNCTION__, *MmioTranslation));\r
        return EFI_UNSUPPORTED;\r
      }\r
\r
      break;\r
    }\r
  }\r
  if (*IoSize == 0 || *MmioSize == 0) {\r
    DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,\r
      (*IoSize == 0) ? "IO" : "MMIO32"));\r
    return EFI_PROTOCOL_ERROR;\r
  }\r
\r
  //\r
  // The dynamic PCD PcdPciExpressBaseAddress should have already been set,\r
  // and should match the value we found in the DT node.\r
  //\r
  ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);\r
\r
  SetLinuxPciProbeOnlyProperty (FdtClient);\r
\r
  DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "\r
    "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, ConfigBase,\r
    ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, *IoTranslation, *MmioBase,\r
    *MmioSize, *MmioTranslation));\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  Entry point of this driver\r
\r
  @param ImageHandle     Handle of driver image\r
  @param SystemTable     Point to EFI_SYSTEM_TABLE\r
\r
  @retval EFI_ABORTED           PCI host bridge not present\r
  @retval EFI_OUT_OF_RESOURCES  Can not allocate memory resource\r
  @retval EFI_DEVICE_ERROR      Can not install the protocol instance\r
  @retval EFI_SUCCESS           Success to initialize the Pci host bridge.\r
**/\r
EFI_STATUS\r
EFIAPI\r
InitializePciHostBridge (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  UINT64                      MmioAttributes;\r
  EFI_STATUS                  Status;\r
  UINTN                       Loop1;\r
  UINTN                       Loop2;\r
  PCI_HOST_BRIDGE_INSTANCE    *HostBridge;\r
  PCI_ROOT_BRIDGE_INSTANCE    *PrivateData;\r
  UINT64                      IoBase, IoSize, IoTranslation;\r
  UINT64                      MmioBase, MmioSize, MmioTranslation;\r
  UINT32                      BusMin, BusMax;\r
\r
  if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {\r
    DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));\r
    return EFI_ABORTED;\r
  }\r
\r
  Status = ProcessPciHost (&IoBase, &IoSize, &IoTranslation, &MmioBase,\r
             &MmioSize, &MmioTranslation, &BusMin, &BusMax);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  mDriverImageHandle = ImageHandle;\r
\r
  mResAperture[0][0].BusBase  = BusMin;\r
  mResAperture[0][0].BusLimit = BusMax;\r
\r
  mResAperture[0][0].MemBase  = MmioBase;\r
  mResAperture[0][0].MemLimit = MmioBase + MmioSize - 1;\r
\r
  mResAperture[0][0].IoBase        = IoBase;\r
  mResAperture[0][0].IoLimit       = IoBase + IoSize - 1;\r
  mResAperture[0][0].IoTranslation = IoTranslation;\r
\r
  //\r
  // Add IO and MMIO memory space, so that resources can be allocated in the\r
  // EfiPciHostBridgeAllocateResources phase.\r
  //\r
  Status = gDS->AddIoSpace (\r
                  EfiGcdIoTypeIo,\r
                  IoBase,\r
                  IoSize\r
                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  MmioAttributes = FeaturePcdGet (PcdKludgeMapPciMmioAsCached) ?\r
                   EFI_MEMORY_WB : EFI_MEMORY_UC;\r
\r
  Status = gDS->AddMemorySpace (\r
                  EfiGcdMemoryTypeMemoryMappedIo,\r
                  MmioBase,\r
                  MmioSize,\r
                  MmioAttributes\r
                  );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status));\r
    return Status;\r
  }\r
\r
  Status = gDS->SetMemorySpaceAttributes (\r
                  MmioBase,\r
                  MmioSize,\r
                  MmioAttributes\r
                  );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__,\r
      Status));\r
    return Status;\r
  }\r
\r
  //\r
  // Create Host Bridge Device Handle\r
  //\r
  for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {\r
    HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);\r
    if (HostBridge == NULL) {\r
      return EFI_OUT_OF_RESOURCES;\r
    }\r
\r
    HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];\r
    InitializeListHead (&HostBridge->Head);\r
\r
    Status = gBS->InstallMultipleProtocolInterfaces (\r
                    &HostBridge->HostBridgeHandle,\r
                    &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,\r
                    NULL\r
                    );\r
    if (EFI_ERROR (Status)) {\r
      FreePool (HostBridge);\r
      return EFI_DEVICE_ERROR;\r
    }\r
\r
    //\r
    // Create Root Bridge Device Handle in this Host Bridge\r
    //\r
\r
    for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {\r
      PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));\r
      if (PrivateData == NULL) {\r
        return EFI_OUT_OF_RESOURCES;\r
      }\r
\r
      PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r
      PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];\r
\r
      RootBridgeConstructor (\r
        &PrivateData->Io,\r
        HostBridge->HostBridgeHandle,\r
        RootBridgeAttribute[Loop1][Loop2],\r
        &mResAperture[Loop1][Loop2]\r
        );\r
\r
      Status = gBS->InstallMultipleProtocolInterfaces(\r
                      &PrivateData->Handle,\r
                      &gEfiDevicePathProtocolGuid,      PrivateData->DevicePath,\r
                      &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,\r
                      NULL\r
                      );\r
      if (EFI_ERROR (Status)) {\r
        FreePool(PrivateData);\r
        return EFI_DEVICE_ERROR;\r
      }\r
\r
      InsertTailList (&HostBridge->Head, &PrivateData->Link);\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
   These are the notifications from the PCI bus driver that it is about to enter a certain\r
   phase of the PCI enumeration process.\r
\r
   This member function can be used to notify the host bridge driver to perform specific actions,\r
   including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
   Eight notification points are defined at this time. See belows:\r
   EfiPciHostBridgeBeginEnumeration       Resets the host bridge PCI apertures and internal data\r
                                          structures. The PCI enumerator should issue this notification\r
                                          before starting a fresh enumeration process. Enumeration cannot\r
                                          be restarted after sending any other notification such as\r
                                          EfiPciHostBridgeBeginBusAllocation.\r
   EfiPciHostBridgeBeginBusAllocation     The bus allocation phase is about to begin. No specific action is\r
                                          required here. This notification can be used to perform any\r
                                          chipset-specific programming.\r
   EfiPciHostBridgeEndBusAllocation       The bus allocation and bus programming phase is complete. No\r
                                          specific action is required here. This notification can be used to\r
                                          perform any chipset-specific programming.\r
   EfiPciHostBridgeBeginResourceAllocation\r
                                          The resource allocation phase is about to begin. No specific\r
                                          action is required here. This notification can be used to perform\r
                                          any chipset-specific programming.\r
   EfiPciHostBridgeAllocateResources      Allocates resources per previously submitted requests for all the PCI\r
                                          root bridges. These resource settings are returned on the next call to\r
                                          GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
                                          EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
                                          for gathering I/O and memory requests for\r
                                          all the PCI root bridges and submitting these requests using\r
                                          SubmitResources(). This function pads the resource amount\r
                                          to suit the root bridge hardware, takes care of dependencies between\r
                                          the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
                                          with the allocation request. In the case of padding, the allocated range\r
                                          could be bigger than what was requested.\r
   EfiPciHostBridgeSetResources           Programs the host bridge hardware to decode previously allocated\r
                                          resources (proposed resources) for all the PCI root bridges. After the\r
                                          hardware is programmed, reassigning resources will not be supported.\r
                                          The bus settings are not affected.\r
   EfiPciHostBridgeFreeResources          Deallocates resources that were previously allocated for all the PCI\r
                                          root bridges and resets the I/O and memory apertures to their initial\r
                                          state. The bus settings are not affected. If the request to allocate\r
                                          resources fails, the PCI enumerator can use this notification to\r
                                          deallocate previous resources, adjust the requests, and retry\r
                                          allocation.\r
   EfiPciHostBridgeEndResourceAllocation  The resource allocation phase is completed. No specific action is\r
                                          required here. This notification can be used to perform any chipsetspecific\r
                                          programming.\r
\r
   @param[in] This                The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
   @param[in] Phase               The phase during enumeration\r
\r
   @retval EFI_NOT_READY          This phase cannot be entered at this time. For example, this error\r
                                  is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
                                  SubmitResources() has not been called for one or more\r
                                  PCI root bridges before this call\r
   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error. This error is valid\r
                                  for a Phase of EfiPciHostBridgeSetResources.\r
   @retval EFI_INVALID_PARAMETER  Invalid phase parameter\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
                                  This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
                                  previously submitted resource requests cannot be fulfilled or\r
                                  were only partially fulfilled.\r
   @retval EFI_SUCCESS            The notification was accepted without any errors.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
NotifyPhase(\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase\r
  )\r
{\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  PCI_RESOURCE_TYPE                     Index;\r
  LIST_ENTRY                            *List;\r
  EFI_PHYSICAL_ADDRESS                  BaseAddress;\r
  UINT64                                AddrLen;\r
  UINTN                                 BitsOfAlignment;\r
  EFI_STATUS                            Status;\r
  EFI_STATUS                            ReturnStatus;\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
\r
  switch (Phase) {\r
\r
  case EfiPciHostBridgeBeginEnumeration:\r
    if (HostBridgeInstance->CanRestarted) {\r
      //\r
      // Reset the Each Root Bridge\r
      //\r
      List = HostBridgeInstance->Head.ForwardLink;\r
\r
      while (List != &HostBridgeInstance->Head) {\r
        RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
        for (Index = TypeIo; Index < TypeMax; Index++) {\r
          RootBridgeInstance->ResAllocNode[Index].Type      = Index;\r
          RootBridgeInstance->ResAllocNode[Index].Base      = 0;\r
          RootBridgeInstance->ResAllocNode[Index].Length    = 0;\r
          RootBridgeInstance->ResAllocNode[Index].Status    = ResNone;\r
        }\r
\r
        List = List->ForwardLink;\r
      }\r
\r
      HostBridgeInstance->ResourceSubmited = FALSE;\r
      HostBridgeInstance->CanRestarted     = TRUE;\r
    } else {\r
      //\r
      // Can not restart\r
      //\r
      return EFI_NOT_READY;\r
    }\r
    break;\r
\r
  case EfiPciHostBridgeEndEnumeration:\r
    break;\r
\r
  case EfiPciHostBridgeBeginBusAllocation:\r
    //\r
    // No specific action is required here, can perform any chipset specific programing\r
    //\r
    HostBridgeInstance->CanRestarted = FALSE;\r
    break;\r
\r
  case EfiPciHostBridgeEndBusAllocation:\r
    //\r
    // No specific action is required here, can perform any chipset specific programing\r
    //\r
    //HostBridgeInstance->CanRestarted = FALSE;\r
    break;\r
\r
  case EfiPciHostBridgeBeginResourceAllocation:\r
    //\r
    // No specific action is required here, can perform any chipset specific programing\r
    //\r
    //HostBridgeInstance->CanRestarted = FALSE;\r
    break;\r
\r
  case EfiPciHostBridgeAllocateResources:\r
    ReturnStatus = EFI_SUCCESS;\r
    if (HostBridgeInstance->ResourceSubmited) {\r
      //\r
      // Take care of the resource dependencies between the root bridges\r
      //\r
      List = HostBridgeInstance->Head.ForwardLink;\r
\r
      while (List != &HostBridgeInstance->Head) {\r
        RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
        for (Index = TypeIo; Index < TypeBus; Index++) {\r
          if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
\r
            AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
\r
            //\r
            // Get the number of '1' in Alignment.\r
            //\r
            BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);\r
\r
            switch (Index) {\r
\r
              case TypeIo:\r
                //\r
                // It is impossible for this chipset to align 0xFFFF for IO16\r
                // So clear it\r
                //\r
                if (BitsOfAlignment >= 16) {\r
                  BitsOfAlignment = 0;\r
                }\r
\r
                BaseAddress = mResAperture[0][0].IoLimit;\r
                Status = gDS->AllocateIoSpace (\r
                                EfiGcdAllocateMaxAddressSearchTopDown,\r
                                EfiGcdIoTypeIo,\r
                                BitsOfAlignment,\r
                                AddrLen,\r
                                &BaseAddress,\r
                                mDriverImageHandle,\r
                                NULL\r
                                );\r
\r
                if (!EFI_ERROR (Status)) {\r
                  RootBridgeInstance->ResAllocNode[Index].Base   = (UINTN)BaseAddress;\r
                  RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r
                } else {\r
                  ReturnStatus = Status;\r
                  if (Status != EFI_OUT_OF_RESOURCES) {\r
                    RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
                  }\r
                }\r
\r
                break;\r
\r
\r
              case TypeMem32:\r
                //\r
                // It is impossible for this chipset to align 0xFFFFFFFF for Mem32\r
                // So clear it\r
                //\r
\r
                if (BitsOfAlignment >= 32) {\r
                  BitsOfAlignment = 0;\r
                }\r
\r
                BaseAddress = mResAperture[0][0].MemLimit;\r
                Status = gDS->AllocateMemorySpace (\r
                                EfiGcdAllocateMaxAddressSearchTopDown,\r
                                EfiGcdMemoryTypeMemoryMappedIo,\r
                                BitsOfAlignment,\r
                                AddrLen,\r
                                &BaseAddress,\r
                                mDriverImageHandle,\r
                                NULL\r
                                );\r
\r
                if (!EFI_ERROR (Status)) {\r
                  // We were able to allocate the PCI memory\r
                  RootBridgeInstance->ResAllocNode[Index].Base   = (UINTN)BaseAddress;\r
                  RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r
\r
                } else {\r
                  // Not able to allocate enough PCI memory\r
                  ReturnStatus = Status;\r
\r
                  if (Status != EFI_OUT_OF_RESOURCES) {\r
                    RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
                  }\r
                  ASSERT (FALSE);\r
                }\r
                break;\r
\r
              case TypePMem32:\r
              case TypeMem64:\r
              case TypePMem64:\r
                  ReturnStatus = EFI_ABORTED;\r
                  break;\r
              default:\r
                ASSERT (FALSE);\r
                break;\r
              }; //end switch\r
          }\r
        }\r
\r
        List = List->ForwardLink;\r
      }\r
\r
      return ReturnStatus;\r
    } else {\r
      return EFI_NOT_READY;\r
    }\r
\r
  case EfiPciHostBridgeSetResources:\r
    break;\r
\r
  case EfiPciHostBridgeFreeResources:\r
    ReturnStatus = EFI_SUCCESS;\r
    List = HostBridgeInstance->Head.ForwardLink;\r
    while (List != &HostBridgeInstance->Head) {\r
      RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
      for (Index = TypeIo; Index < TypeBus; Index++) {\r
        if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {\r
          AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
          BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;\r
          switch (Index) {\r
\r
          case TypeIo:\r
            Status = gDS->FreeIoSpace (BaseAddress, AddrLen);\r
            if (EFI_ERROR (Status)) {\r
              ReturnStatus = Status;\r
            }\r
            break;\r
\r
          case TypeMem32:\r
            Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);\r
            if (EFI_ERROR (Status)) {\r
              ReturnStatus = Status;\r
            }\r
            break;\r
\r
          case TypePMem32:\r
            break;\r
\r
          case TypeMem64:\r
            break;\r
\r
          case TypePMem64:\r
            break;\r
\r
          default:\r
            ASSERT (FALSE);\r
            break;\r
\r
          }; //end switch\r
          RootBridgeInstance->ResAllocNode[Index].Type      = Index;\r
          RootBridgeInstance->ResAllocNode[Index].Base      = 0;\r
          RootBridgeInstance->ResAllocNode[Index].Length    = 0;\r
          RootBridgeInstance->ResAllocNode[Index].Status    = ResNone;\r
        }\r
      }\r
\r
      List = List->ForwardLink;\r
    }\r
\r
    HostBridgeInstance->ResourceSubmited = FALSE;\r
    HostBridgeInstance->CanRestarted     = TRUE;\r
    return ReturnStatus;\r
\r
  case EfiPciHostBridgeEndResourceAllocation:\r
    HostBridgeInstance->CanRestarted = FALSE;\r
    break;\r
\r
  default:\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Return the device handle of the next PCI root bridge that is associated with this Host Bridge.\r
\r
   This function is called multiple times to retrieve the device handles of all the PCI root bridges that\r
   are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI\r
   root bridges. On each call, the handle that was returned by the previous call is passed into the\r
   interface, and on output the interface returns the device handle of the next PCI root bridge. The\r
   caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
   for that root bridge. When there are no more PCI root bridges to report, the interface returns\r
   EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they\r
   are returned by this function.\r
   For D945 implementation, there is only one root bridge in PCI host bridge.\r
\r
   @param[in]       This              The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
   @param[in, out]  RootBridgeHandle  Returns the device handle of the next PCI root bridge.\r
\r
   @retval EFI_SUCCESS            If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
                                  specific Host bridge and return EFI_SUCCESS.\r
   @retval EFI_NOT_FOUND          Can not find the any more root bridge in specific host bridge.\r
   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not an EFI_HANDLE that was\r
                                  returned on a previous call to GetNextRootBridge().\r
**/\r
EFI_STATUS\r
EFIAPI\r
GetNextRootBridge(\r
  IN       EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN OUT   EFI_HANDLE                                       *RootBridgeHandle\r
  )\r
{\r
  BOOLEAN                               NoRootBridge;\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
\r
  NoRootBridge = TRUE;\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
\r
  while (List != &HostBridgeInstance->Head) {\r
    NoRootBridge = FALSE;\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (*RootBridgeHandle == NULL) {\r
      //\r
      // Return the first Root Bridge Handle of the Host Bridge\r
      //\r
      *RootBridgeHandle = RootBridgeInstance->Handle;\r
      return EFI_SUCCESS;\r
    } else {\r
      if (*RootBridgeHandle == RootBridgeInstance->Handle) {\r
        //\r
        // Get next if have\r
        //\r
        List = List->ForwardLink;\r
        if (List!=&HostBridgeInstance->Head) {\r
          RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
          *RootBridgeHandle = RootBridgeInstance->Handle;\r
          return EFI_SUCCESS;\r
        } else {\r
          return EFI_NOT_FOUND;\r
        }\r
      }\r
    }\r
\r
    List = List->ForwardLink;\r
  } //end while\r
\r
  if (NoRootBridge) {\r
    return EFI_NOT_FOUND;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
}\r
\r
/**\r
   Returns the allocation attributes of a PCI root bridge.\r
\r
   The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary\r
   from one PCI root bridge to another. These attributes are different from the decode-related\r
   attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
   RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device\r
   handles of all the root bridges that are associated with this host bridge must be obtained by calling\r
   GetNextRootBridge(). The attributes are static in the sense that they do not change during or\r
   after the enumeration process. The hardware may provide mechanisms to change the attributes on\r
   the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is\r
   installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
   "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.\r
   For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to\r
   include requests for the prefetchable memory in the nonprefetchable memory pool and not request any\r
   prefetchable memory.\r
      Attribute                                 Description\r
   ------------------------------------         ----------------------------------------------------------------------\r
   EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM         If this bit is set, then the PCI root bridge does not support separate\r
                                                windows for nonprefetchable and prefetchable memory. A PCI bus\r
                                                driver needs to include requests for prefetchable memory in the\r
                                                nonprefetchable memory pool.\r
\r
   EFI_PCI_HOST_BRIDGE_MEM64_DECODE             If this bit is set, then the PCI root bridge supports 64-bit memory\r
                                                windows. If this bit is not set, the PCI bus driver needs to include\r
                                                requests for a 64-bit memory address in the corresponding 32-bit\r
                                                memory pool.\r
\r
   @param[in]   This               The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
   @param[in]   RootBridgeHandle   The device handle of the PCI root bridge in which the caller is interested. Type\r
                                   EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
   @param[out]  Attributes         The pointer to attribte of root bridge, it is output parameter\r
\r
   @retval EFI_INVALID_PARAMETER   Attribute pointer is NULL\r
   @retval EFI_INVALID_PARAMETER   RootBridgehandle is invalid.\r
   @retval EFI_SUCCESS             Success to get attribute of interested root bridge.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
GetAttributes(\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN  EFI_HANDLE                                       RootBridgeHandle,\r
  OUT UINT64                                           *Attributes\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
\r
  if (Attributes == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      *Attributes = RootBridgeInstance->RootBridgeAttrib;\r
      return EFI_SUCCESS;\r
    }\r
    List = List->ForwardLink;\r
  }\r
\r
  //\r
  // RootBridgeHandle is not an EFI_HANDLE\r
  // that was returned on a previous call to GetNextRootBridge()\r
  //\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
/**\r
   Sets up the specified PCI root bridge for the bus enumeration process.\r
\r
   This member function sets up the root bridge for bus enumeration and returns the PCI bus range\r
   over which the search should be performed in ACPI 2.0 resource descriptor format.\r
\r
   @param[in]   This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
   @param[in]   RootBridgeHandle  The PCI Root Bridge to be set up.\r
   @param[out]  Configuration     Pointer to the pointer to the PCI bus resource descriptor.\r
\r
   @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
   @retval EFI_OUT_OF_RESOURCES  Fail to allocate ACPI resource descriptor tag.\r
   @retval EFI_SUCCESS           Sucess to allocate ACPI resource descriptor.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
StartBusEnumeration(\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN  EFI_HANDLE                                       RootBridgeHandle,\r
  OUT VOID                                             **Configuration\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  VOID                                  *Buffer;\r
  UINT8                                 *Temp;\r
  UINT64                                BusStart;\r
  UINT64                                BusEnd;\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      //\r
      // Set up the Root Bridge for Bus Enumeration\r
      //\r
      BusStart = RootBridgeInstance->BusBase;\r
      BusEnd   = RootBridgeInstance->BusLimit;\r
      //\r
      // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR\r
      //\r
\r
      Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));\r
      if (Buffer == NULL) {\r
        return EFI_OUT_OF_RESOURCES;\r
      }\r
\r
      Temp = (UINT8 *)Buffer;\r
\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len  = 0x2B;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;\r
      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;\r
\r
      Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r
      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r
\r
      *Configuration = Buffer;\r
      return EFI_SUCCESS;\r
    }\r
    List = List->ForwardLink;\r
  }\r
\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
/**\r
   Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
\r
   This member function programs the specified PCI root bridge to decode the bus range that is\r
   specified by the input parameter Configuration.\r
   The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.\r
\r
   @param[in] This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
   @param[in] RootBridgeHandle  The PCI Root Bridge whose bus range is to be programmed\r
   @param[in] Configuration     The pointer to the PCI bus resource descriptor\r
\r
   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.\r
   @retval EFI_INVALID_PARAMETER  Configuration is NULL.\r
   @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
   @retval EFI_INVALID_PARAMETER  Configuration does not include a valid ACPI 2.0 bus resource descriptor.\r
   @retval EFI_INVALID_PARAMETER  Configuration includes valid ACPI 2.0 resource descriptors other than\r
                                  bus descriptors.\r
   @retval EFI_INVALID_PARAMETER  Configuration contains one or more invalid ACPI resource descriptors.\r
   @retval EFI_INVALID_PARAMETER  "Address Range Minimum" is invalid for this root bridge.\r
   @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this root bridge.\r
   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.\r
   @retval EFI_SUCCESS            The bus range for the PCI root bridge was programmed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SetBusNumbers(\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN EFI_HANDLE                                       RootBridgeHandle,\r
  IN VOID                                             *Configuration\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  UINT8                                 *Ptr;\r
  UINTN                                 BusStart;\r
  UINTN                                 BusEnd;\r
  UINTN                                 BusLen;\r
\r
  if (Configuration == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Ptr = Configuration;\r
\r
  //\r
  // Check the Configuration is valid\r
  //\r
  if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
  if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  Ptr = Configuration;\r
\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;\r
      BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;\r
      BusEnd = BusStart + BusLen - 1;\r
\r
      if (BusStart > BusEnd) {\r
        return EFI_INVALID_PARAMETER;\r
      }\r
\r
      if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {\r
        return EFI_INVALID_PARAMETER;\r
      }\r
\r
      //\r
      // Update the Bus Range\r
      //\r
      RootBridgeInstance->ResAllocNode[TypeBus].Base   = BusStart;\r
      RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;\r
      RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;\r
\r
      //\r
      // Program the Root Bridge Hardware\r
      //\r
\r
      return EFI_SUCCESS;\r
    }\r
\r
    List = List->ForwardLink;\r
  }\r
\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
\r
/**\r
   Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
\r
   This function is used to submit all the I/O and memory resources that are required by the specified\r
   PCI root bridge. The input parameter Configuration is used to specify the following:\r
   - The various types of resources that are required\r
   - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
\r
   @param[in] This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
   @param[in] RootBridgeHandle  The PCI root bridge whose I/O and memory resource requirements are being submitted.\r
   @param[in] Configuration     The pointer to the PCI I/O and PCI memory resource descriptor.\r
\r
   @retval EFI_SUCCESS            The I/O and memory resource requests for a PCI root bridge were accepted.\r
   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.\r
   @retval EFI_INVALID_PARAMETER  Configuration is NULL.\r
   @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
   @retval EFI_INVALID_PARAMETER  Configuration includes requests for one or more resource types that are\r
                                  not supported by this PCI root bridge. This error will happen if the caller\r
                                  did not combine resources according to Attributes that were returned by\r
                                  GetAllocAttributes().\r
   @retval EFI_INVALID_PARAMETER  Address Range Maximum" is invalid.\r
   @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  "Address Space Granularity" is invalid for this PCI root bridge.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SubmitResources(\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN EFI_HANDLE                                       RootBridgeHandle,\r
  IN VOID                                             *Configuration\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  UINT8                                 *Temp;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;\r
  UINT64                                AddrLen;\r
  UINT64                                Alignment;\r
\r
  //\r
  // Check the input parameter: Configuration\r
  //\r
  if (Configuration == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  Temp = (UINT8 *)Configuration;\r
  while ( *Temp == 0x8A) {\r
    Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;\r
  }\r
  if (*Temp != 0x79) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Temp = (UINT8 *)Configuration;\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      for (;\r
           *Temp == 0x8A;\r
           Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)\r
           ) {\r
        Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
\r
        //\r
        // Check Address Length\r
        //\r
        if (Ptr->AddrLen == 0) {\r
          HostBridgeInstance->ResourceSubmited = TRUE;\r
          continue;\r
        }\r
        if (Ptr->AddrLen > 0xffffffff) {\r
          return EFI_INVALID_PARAMETER;\r
        }\r
\r
        //\r
        // Check address range alignment\r
        //\r
        if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {\r
          return EFI_INVALID_PARAMETER;\r
        }\r
\r
        switch (Ptr->ResType) {\r
\r
        case 0:\r
\r
          //\r
          // Check invalid Address Sapce Granularity\r
          //\r
          if (Ptr->AddrSpaceGranularity != 32) {\r
            return EFI_INVALID_PARAMETER;\r
          }\r
\r
          //\r
          // check the memory resource request is supported by PCI root bridge\r
          //\r
          if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&\r
               Ptr->SpecificFlag == 0x06) {\r
            return EFI_INVALID_PARAMETER;\r
          }\r
\r
          AddrLen = Ptr->AddrLen;\r
          Alignment = Ptr->AddrRangeMax;\r
          if (Ptr->AddrSpaceGranularity == 32) {\r
            if (Ptr->SpecificFlag == 0x06) {\r
              //\r
              // Apply from GCD\r
              //\r
              RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;\r
            } else {\r
              RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;\r
              RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;\r
              RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;\r
              HostBridgeInstance->ResourceSubmited = TRUE;\r
            }\r
          }\r
\r
          if (Ptr->AddrSpaceGranularity == 64) {\r
            if (Ptr->SpecificFlag == 0x06) {\r
              RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;\r
            } else {\r
              RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;\r
            }\r
          }\r
          break;\r
\r
        case 1:\r
          AddrLen = (UINTN) Ptr->AddrLen;\r
          Alignment = (UINTN) Ptr->AddrRangeMax;\r
          RootBridgeInstance->ResAllocNode[TypeIo].Length  = AddrLen;\r
          RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r
          RootBridgeInstance->ResAllocNode[TypeIo].Status  = ResRequested;\r
          HostBridgeInstance->ResourceSubmited = TRUE;\r
          break;\r
\r
        default:\r
            break;\r
        };\r
      }\r
\r
      return EFI_SUCCESS;\r
    }\r
\r
    List = List->ForwardLink;\r
  }\r
\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
/**\r
   Returns the proposed resource settings for the specified PCI root bridge.\r
\r
   This member function returns the proposed resource settings for the specified PCI root bridge. The\r
   proposed resource settings are prepared when NotifyPhase() is called with a Phase of\r
   EfiPciHostBridgeAllocateResources. The output parameter Configuration\r
   specifies the following:\r
   - The various types of resources, excluding bus resources, that are allocated\r
   - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
\r
   @param[in]  This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
   @param[in]  RootBridgeHandle  The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
   @param[out] Configuration     The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
\r
   @retval EFI_SUCCESS            The requested parameters were returned.\r
   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.\r
   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
GetProposedResources(\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN  EFI_HANDLE                                       RootBridgeHandle,\r
  OUT VOID                                             **Configuration\r
  )\r
{\r
  LIST_ENTRY                            *List;\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  UINTN                                 Index;\r
  UINTN                                 Number;\r
  VOID                                  *Buffer;\r
  UINT8                                 *Temp;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;\r
  UINT64                                ResStatus;\r
\r
  Buffer = NULL;\r
  Number = 0;\r
  //\r
  // Get the Host Bridge Instance from the resource allocation protocol\r
  //\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  //\r
  // Enumerate the root bridges in this host bridge\r
  //\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      for (Index = 0; Index < TypeBus; Index ++) {\r
        if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
          Number ++;\r
        }\r
      }\r
\r
      if (Number ==  0) {\r
        EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
\r
        End = AllocateZeroPool (sizeof *End);\r
        if (End == NULL) {\r
          return EFI_OUT_OF_RESOURCES;\r
        }\r
        End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
        *Configuration = End;\r
        return EFI_SUCCESS;\r
      }\r
\r
      Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));\r
      if (Buffer == NULL) {\r
        return EFI_OUT_OF_RESOURCES;\r
      }\r
\r
      Temp = Buffer;\r
      for (Index = 0; Index < TypeBus; Index ++) {\r
        if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
          Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r
          ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r
\r
          switch (Index) {\r
\r
          case TypeIo:\r
            //\r
            // Io\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 1;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 0;\r
            Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = \\r
                 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
            Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
            break;\r
\r
          case TypeMem32:\r
            //\r
            // Memory 32\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 0;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 0;\r
            Ptr->AddrSpaceGranularity = 32;\r
            Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = \\r
                 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
            Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
            break;\r
\r
          case TypePMem32:\r
            //\r
            // Prefetch memory 32\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 0;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 6;\r
            Ptr->AddrSpaceGranularity = 32;\r
            Ptr->AddrRangeMin = 0;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
            Ptr->AddrLen = 0;\r
            break;\r
\r
          case TypeMem64:\r
            //\r
            // Memory 64\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 0;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 0;\r
            Ptr->AddrSpaceGranularity = 64;\r
            Ptr->AddrRangeMin = 0;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
            Ptr->AddrLen = 0;\r
            break;\r
\r
          case TypePMem64:\r
            //\r
            // Prefetch memory 64\r
            //\r
            Ptr->Desc = 0x8A;\r
            Ptr->Len  = 0x2B;\r
            Ptr->ResType = 0;\r
            Ptr->GenFlag = 0;\r
            Ptr->SpecificFlag = 6;\r
            Ptr->AddrSpaceGranularity = 64;\r
            Ptr->AddrRangeMin = 0;\r
            Ptr->AddrRangeMax = 0;\r
            Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
            Ptr->AddrLen = 0;\r
            break;\r
          };\r
\r
          Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
        }\r
      }\r
\r
      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r
      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r
\r
      *Configuration = Buffer;\r
\r
      return EFI_SUCCESS;\r
    }\r
\r
    List = List->ForwardLink;\r
  }\r
\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
/**\r
   Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
   stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
   PCI controllers before enumeration.\r
\r
   This function is called during the PCI enumeration process. No specific action is expected from this\r
   member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
   enumeration.\r
\r
   @param This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
   @param RootBridgeHandle  The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r
                            InstallProtocolInterface() in the UEFI 2.0 Specification.\r
   @param PciAddress        The address of the PCI device on the PCI bus. This address can be passed to the\r
                            EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r
                            configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r
                            the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
   @param Phase             The phase of the PCI device enumeration.\r
\r
   @retval EFI_SUCCESS              The requested parameters were returned.\r
   @retval EFI_INVALID_PARAMETER    RootBridgeHandle is not a valid root bridge handle.\r
   @retval EFI_INVALID_PARAMETER    Phase is not a valid phase that is defined in\r
                                    EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
   @retval EFI_DEVICE_ERROR         Programming failed due to a hardware error. The PCI enumerator should\r
                                    not enumerate this device, including its child devices if it is a PCI-to-PCI\r
                                    bridge.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PreprocessController (\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL          *This,\r
  IN  EFI_HANDLE                                                RootBridgeHandle,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS               PciAddress,\r
  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE              Phase\r
  )\r
{\r
  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;\r
  LIST_ENTRY                            *List;\r
\r
  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
  List = HostBridgeInstance->Head.ForwardLink;\r
\r
  //\r
  // Enumerate the root bridges in this host bridge\r
  //\r
  while (List != &HostBridgeInstance->Head) {\r
    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
    if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
      break;\r
    }\r
    List = List->ForwardLink;\r
  }\r
  if (List == &HostBridgeInstance->Head) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((UINT32)Phase > EfiPciBeforeResourceCollection) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r