projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| cf1d4549 JY |
1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | This program and the accompanying materials\r | |
| 5 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 6 | which accompanies this distribution. The full text of the license may be found at\r | |
| 7 | http://opensource.org/licenses/bsd-license.php.\r | |
| 8 | \r | |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 11 | \r | |
| 12 | **/\r | |
| 13 | \r | |
| 14 | #ifndef _FSP_MEASURE_POINT_ID_H_\r | |
| 15 | #define _FSP_MEASURE_POINT_ID_H_\r | |
| 16 | \r | |
| 17 | //\r | |
| 18 | // 0xD0 - 0xEF are reserved for FSP common measure point\r | |
| 19 | //\r | |
| 20 | #define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0\r | |
| 21 | #define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1)\r | |
| 22 | \r | |
| 23 | #define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8\r | |
| 24 | #define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1)\r | |
| 25 | \r | |
| 26 | #define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA\r | |
| 27 | #define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1)\r | |
| 28 | \r | |
| 29 | #define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0\r | |
| 30 | #define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1)\r | |
| 31 | \r | |
| 32 | #define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8\r | |
| 33 | #define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1)\r | |
| 34 | \r | |
| 35 | #define FSP_PERF_ID_ME_INIT_ENTRY 0xEA\r | |
| 36 | #define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1)\r | |
| 37 | \r | |
| 38 | //\r | |
| 39 | // 0xF0 - 0xFF are reserved for FSP API\r | |
| 40 | //\r | |
| 41 | #define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0\r | |
| 42 | #define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)\r | |
| 43 | \r | |
| 44 | #define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2\r | |
| 45 | #define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)\r | |
| 46 | \r | |
| 47 | #define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4\r | |
| 48 | #define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)\r | |
| 49 | \r | |
| 50 | #define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6\r | |
| 51 | #define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)\r | |
| 52 | \r | |
| 53 | #define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8\r | |
| 54 | #define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)\r | |
| 55 | \r | |
| 56 | #define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA\r | |
| 57 | #define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)\r | |
| 58 | \r | |
| 59 | #define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC\r | |
| 60 | #define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1)\r | |
| 61 | \r | |
| 62 | #endif\r |