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7e74fd57 JY |
1 | /** @file\r |
2 | IGD OpRegion definition from Intel Integrated Graphics Device OpRegion\r | |
3 | Specification.\r | |
4 | \r | |
98e059ba | 5 | https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf\r |
7e74fd57 | 6 | \r |
34c5a69a | 7 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r |
8f7a05e1 | 8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
7e74fd57 JY |
9 | \r |
10 | **/\r | |
11 | #ifndef _IGD_OPREGION_H_\r | |
12 | #define _IGD_OPREGION_H_\r | |
13 | \r | |
98e059ba GM |
14 | #define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem"\r |
15 | #define IGD_OPREGION_HEADER_MBOX1 BIT0\r | |
16 | #define IGD_OPREGION_HEADER_MBOX2 BIT1\r | |
17 | #define IGD_OPREGION_HEADER_MBOX3 BIT2\r | |
18 | #define IGD_OPREGION_HEADER_MBOX4 BIT3\r | |
19 | #define IGD_OPREGION_HEADER_MBOX5 BIT4\r | |
20 | \r | |
7e74fd57 | 21 | /**\r |
5c66efd0 MG |
22 | OpRegion structures:\r |
23 | Sub-structures define the different parts of the OpRegion followed by the\r | |
24 | main structure representing the entire OpRegion.\r | |
7e74fd57 | 25 | \r |
6e9e19aa | 26 | @note These structures are packed to 1 byte offsets because the exact\r |
5c66efd0 MG |
27 | data location is required by the supporting design specification due to\r |
28 | the fact that the data is used by ASL and Graphics driver code compiled\r | |
29 | separately.\r | |
7e74fd57 JY |
30 | **/\r |
31 | #pragma pack(1)\r | |
32 | ///\r | |
72092534 | 33 | /// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to\r |
5c66efd0 | 34 | /// identify a block of memory as the graphics driver OpRegion.\r |
72092534 | 35 | /// Offset 0x0, Size 0x100\r |
7e74fd57 JY |
36 | ///\r |
37 | typedef struct {\r | |
5c66efd0 MG |
38 | CHAR8 SIGN[0x10]; ///< Offset 0x00 OpRegion Signature\r |
39 | UINT32 SIZE; ///< Offset 0x10 OpRegion Size\r | |
40 | UINT32 OVER; ///< Offset 0x14 OpRegion Structure Version\r | |
41 | UINT8 SVER[0x20]; ///< Offset 0x18 System BIOS Build Version\r | |
42 | UINT8 VVER[0x10]; ///< Offset 0x38 Video BIOS Build Version\r | |
43 | UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version\r | |
44 | UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes\r | |
45 | UINT32 DMOD; ///< Offset 0x5C Driver Model\r | |
98e059ba | 46 | UINT32 PCON; ///< Offset 0x60 Platform Configuration\r |
c3aa61b5 | 47 | CHAR16 DVER[0x10]; ///< Offset 0x64 GOP Version\r |
98e059ba | 48 | UINT8 RM01[0x7C]; ///< Offset 0x84 Reserved Must be zero\r |
72092534 | 49 | } IGD_OPREGION_HEADER;\r |
7e74fd57 JY |
50 | \r |
51 | ///\r | |
72092534 MG |
52 | /// OpRegion Mailbox 1 - Public ACPI Methods\r |
53 | /// Offset 0x100, Size 0x100\r | |
7e74fd57 JY |
54 | ///\r |
55 | typedef struct {\r | |
5c66efd0 MG |
56 | UINT32 DRDY; ///< Offset 0x100 Driver Readiness\r |
57 | UINT32 CSTS; ///< Offset 0x104 Status\r | |
58 | UINT32 CEVT; ///< Offset 0x108 Current Event\r | |
98e059ba | 59 | UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero\r |
5c66efd0 MG |
60 | UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List\r |
61 | UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devices List\r | |
62 | UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices List\r | |
63 | UINT32 NADL[8]; ///< Offset 0x180 Next Active Devices List\r | |
64 | UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out\r | |
65 | UINT32 TIDX; ///< Offset 0x1A4 Toggle Table Index\r | |
66 | UINT32 CHPD; ///< Offset 0x1A8 Current Hotplug Enable Indicator\r | |
67 | UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator\r | |
68 | UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator\r | |
69 | UINT32 SXSW; ///< Offset 0x1B4 Display Switch Notification on Sx State Resume\r | |
70 | UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL\r | |
71 | UINT32 CNOT; ///< Offset 0x1BC Current OS Notification\r | |
72 | UINT32 NRDY; ///< Offset 0x1C0 Driver Status\r | |
98e059ba GM |
73 | UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)\r |
74 | UINT8 CPD2[0x1C]; ///< Offset 0x1E0 Extended Attached Display Devices List\r | |
75 | UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero\r | |
72092534 | 76 | } IGD_OPREGION_MBOX1;\r |
7e74fd57 JY |
77 | \r |
78 | ///\r | |
72092534 MG |
79 | /// OpRegion Mailbox 2 - Software SCI Interface\r |
80 | /// Offset 0x200, Size 0x100\r | |
7e74fd57 JY |
81 | ///\r |
82 | typedef struct {\r | |
5c66efd0 MG |
83 | UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / Data\r |
84 | UINT32 PARM; ///< Offset 0x204 Software SCI Parameters\r | |
85 | UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out\r | |
98e059ba | 86 | UINT8 RM21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero\r |
72092534 | 87 | } IGD_OPREGION_MBOX2;\r |
7e74fd57 JY |
88 | \r |
89 | ///\r | |
72092534 MG |
90 | /// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support\r |
91 | /// Offset 0x300, Size 0x100\r | |
7e74fd57 JY |
92 | ///\r |
93 | typedef struct {\r | |
5c66efd0 MG |
94 | UINT32 ARDY; ///< Offset 0x300 Driver Readiness\r |
95 | UINT32 ASLC; ///< Offset 0x304 ASLE Interrupt Command / Status\r | |
96 | UINT32 TCHE; ///< Offset 0x308 Technology Enabled Indicator\r | |
97 | UINT32 ALSI; ///< Offset 0x30C Current ALS Luminance Reading\r | |
98 | UINT32 BCLP; ///< Offset 0x310 Requested Backlight Brightness\r | |
99 | UINT32 PFIT; ///< Offset 0x314 Panel Fitting State or Request\r | |
100 | UINT32 CBLV; ///< Offset 0x318 Current Brightness Level\r | |
101 | UINT16 BCLM[0x14]; ///< Offset 0x31C Backlight Brightness Levels Duty Cycle Mapping Table\r | |
102 | UINT32 CPFM; ///< Offset 0x344 Current Panel Fitting Mode\r | |
103 | UINT32 EPFM; ///< Offset 0x348 Enabled Panel Fitting Modes\r | |
104 | UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier\r | |
105 | UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Brightness\r | |
106 | UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values\r | |
98e059ba GM |
107 | UINT32 PCFT; ///< Offset 0x39E Power Conservation Features\r |
108 | UINT32 SROT; ///< Offset 0x3A2 Supported Rotation Angles\r | |
109 | UINT32 IUER; ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register\r | |
110 | UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature\r | |
111 | UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer\r | |
112 | UINT32 STAT; ///< Offset 0x3B6 State Indicator\r | |
34c5a69a SD |
113 | UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB.\r |
114 | UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB.\r | |
115 | UINT8 RM32[0x3A]; ///< Offset 0x3C6 - 0x3FF Reserved Must be zero.\r | |
72092534 | 116 | } IGD_OPREGION_MBOX3;\r |
7e74fd57 JY |
117 | \r |
118 | ///\r | |
72092534 MG |
119 | /// OpRegion Mailbox 4 - VBT Video BIOS Table\r |
120 | /// Offset 0x400, Size 0x1800\r | |
7e74fd57 JY |
121 | ///\r |
122 | typedef struct {\r | |
5c66efd0 | 123 | UINT8 RVBT[0x1800]; ///< Offset 0x400 - 0x1BFF Raw VBT Data\r |
72092534 | 124 | } IGD_OPREGION_MBOX4;\r |
7e74fd57 | 125 | \r |
98e059ba GM |
126 | ///\r |
127 | /// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync\r | |
128 | /// Offset 0x1C00, Size 0x400\r | |
129 | ///\r | |
130 | typedef struct {\r | |
131 | UINT32 PHED; ///< Offset 0x1C00 Panel Header\r | |
132 | UINT8 BDDC[0x100]; ///< Offset 0x1C04 Panel EDID (DDC data)\r | |
133 | UINT8 RM51[0x2FC]; ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero\r | |
134 | } IGD_OPREGION_MBOX5;\r | |
135 | \r | |
7e74fd57 JY |
136 | ///\r |
137 | /// IGD OpRegion Structure\r | |
138 | ///\r | |
139 | typedef struct {\r | |
72092534 MG |
140 | IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)\r |
141 | IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100)\r | |
142 | IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)\r | |
143 | IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)\r | |
144 | IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)\r | |
98e059ba | 145 | IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)\r |
72092534 | 146 | } IGD_OPREGION_STRUCTURE;\r |
9fb16e21 JY |
147 | #pragma pack()\r |
148 | \r | |
149 | #endif\r |