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MdeModulePkg/NvmExpressDxe: Check if CSTS.RDY is 0 to wait NVMe Host controller disable
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.h
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eb290d02
FT		 1/** @file\r
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
3 NVM Express specification.\r
4\r
4ab4497c 5 Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
eb290d02
FT		 6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php.\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _NVME_HCI_H_\r
17#define _NVME_HCI_H_\r
18\r
19#define NVME_BAR 0\r
20\r
21//\r
22// controller register offsets\r
23//\r
24#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
25#define NVME_VER_OFFSET 0x0008 // Version\r
26#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
27#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
28#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
29#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
4ab4497c 30#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset\r
eb290d02
FT		 31#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
32#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
33#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
34#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
35#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
36\r
37//\r
38// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
39// Get the doorbell stride bit shift value from the controller capabilities.\r
40//\r
41#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r
42#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r
43\r
44\r
45#pragma pack(1)\r
46\r
47//\r
48// 3.1.1 Offset 00h: CAP - Controller Capabilities\r
49//\r
50typedef struct {\r
51 UINT16 Mqes; // Maximum Queue Entries Supported\r
52 UINT8 Cqr:1; // Contiguous Queues Required\r
53 UINT8 Ams:2; // Arbitration Mechanism Supported\r
54 UINT8 Rsvd1:5;\r
55 UINT8 To; // Timeout\r
56 UINT16 Dstrd:4;\r
4ab4497c
TF		 57 UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS\r
58 UINT16 Css:4; // Command Sets Supported - Bit 37\r
eb290d02
FT		 59 UINT16 Rsvd3:7;\r
60 UINT8 Mpsmin:4;\r
61 UINT8 Mpsmax:4;\r
62 UINT8 Rsvd4;\r
63} NVME_CAP;\r
64\r
65//\r
66// 3.1.2 Offset 08h: VS - Version\r
67//\r
68typedef struct {\r
69 UINT16 Mnr; // Minor version number\r
70 UINT16 Mjr; // Major version number\r
71} NVME_VER;\r
72\r
73//\r
74// 3.1.5 Offset 14h: CC - Controller Configuration\r
75//\r
76typedef struct {\r
77 UINT16 En:1; // Enable\r
78 UINT16 Rsvd1:3;\r
4ab4497c 79 UINT16 Css:3; // I/O Command Set Selected\r
eb290d02
FT		 80 UINT16 Mps:4; // Memory Page Size\r
81 UINT16 Ams:3; // Arbitration Mechanism Selected\r
82 UINT16 Shn:2; // Shutdown Notification\r
83 UINT8 Iosqes:4; // I/O Submission Queue Entry Size\r
84 UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r
85 UINT8 Rsvd2;\r
86} NVME_CC;\r
87\r
88//\r
89// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
90//\r
91typedef struct {\r
92 UINT32 Rdy:1; // Ready\r
93 UINT32 Cfs:1; // Controller Fatal Status\r
94 UINT32 Shst:2; // Shutdown Status\r
95 UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r
96 UINT32 Rsvd1:27;\r
97} NVME_CSTS;\r
98\r
99//\r
100// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
101//\r
102typedef struct {\r
103 UINT16 Asqs:12; // Submission Queue Size\r
104 UINT16 Rsvd1:4;\r
105 UINT16 Acqs:12; // Completion Queue Size\r
106 UINT16 Rsvd2:4;\r
107} NVME_AQA;\r
108\r
109//\r
110// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
111//\r
112typedef struct {\r
113 UINT64 Rsvd1:12;\r
114 UINT64 Asqb:52; // Admin Submission Queue Base Address\r
115} NVME_ASQ;\r
116\r
117//\r
118// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
119//\r
120typedef struct {\r
121 UINT64 Rsvd1:12;\r
122 UINT64 Acqb:52; // Admin Completion Queue Base Address\r
123} NVME_ACQ;\r
124\r
125//\r
126// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
127//\r
128typedef struct {\r
129 UINT16 Sqt;\r
130 UINT16 Rsvd1;\r
131} NVME_SQTDBL;\r
132\r
133//\r
134// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r
135//\r
136typedef struct {\r
137 UINT16 Cqh;\r
138 UINT16 Rsvd1;\r
139} NVME_CQHDBL;\r
140\r
141//\r
142// NVM command set structures\r
143//\r
144// Read Command\r
145//\r
146typedef struct {\r
147 //\r
148 // CDW 10, 11\r
149 //\r
150 UINT64 Slba; /* Starting Sector Address */\r
151 //\r
152 // CDW 12\r
153 //\r
154 UINT16 Nlb; /* Number of Sectors */\r
155 UINT16 Rsvd1:10;\r
156 UINT16 Prinfo:4; /* Protection Info Check */\r
157 UINT16 Fua:1; /* Force Unit Access */\r
158 UINT16 Lr:1; /* Limited Retry */\r
159 //\r
160 // CDW 13\r
161 //\r
162 UINT32 Af:4; /* Access Frequency */\r
163 UINT32 Al:2; /* Access Latency */\r
164 UINT32 Sr:1; /* Sequential Request */\r
165 UINT32 In:1; /* Incompressible */\r
166 UINT32 Rsvd2:24;\r
167 //\r
168 // CDW 14\r
169 //\r
170 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
171 //\r
172 // CDW 15\r
173 //\r
174 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
175 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
176} NVME_READ;\r
177\r
178//\r
179// Write Command\r
180//\r
181typedef struct {\r
182 //\r
183 // CDW 10, 11\r
184 //\r
185 UINT64 Slba; /* Starting Sector Address */\r
186 //\r
187 // CDW 12\r
188 //\r
189 UINT16 Nlb; /* Number of Sectors */\r
190 UINT16 Rsvd1:10;\r
191 UINT16 Prinfo:4; /* Protection Info Check */\r
192 UINT16 Fua:1; /* Force Unit Access */\r
193 UINT16 Lr:1; /* Limited Retry */\r
194 //\r
195 // CDW 13\r
196 //\r
197 UINT32 Af:4; /* Access Frequency */\r
198 UINT32 Al:2; /* Access Latency */\r
199 UINT32 Sr:1; /* Sequential Request */\r
200 UINT32 In:1; /* Incompressible */\r
201 UINT32 Rsvd2:24;\r
202 //\r
203 // CDW 14\r
204 //\r
205 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
206 //\r
207 // CDW 15\r
208 //\r
209 UINT16 Lbat; /* Logical Block Application Tag */\r
210 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
211} NVME_WRITE;\r
212\r
213//\r
214// Flush\r
215//\r
216typedef struct {\r
217 //\r
218 // CDW 10\r
219 //\r
220 UINT32 Flush; /* Flush */\r
221} NVME_FLUSH;\r
222\r
223//\r
224// Write Uncorrectable command\r
225//\r
226typedef struct {\r
227 //\r
228 // CDW 10, 11\r
229 //\r
230 UINT64 Slba; /* Starting LBA */\r
231 //\r
232 // CDW 12\r
233 //\r
234 UINT32 Nlb:16; /* Number of Logical Blocks */\r
235 UINT32 Rsvd1:16;\r
236} NVME_WRITE_UNCORRECTABLE;\r
237\r
238//\r
239// Write Zeroes command\r
240//\r
241typedef struct {\r
242 //\r
243 // CDW 10, 11\r
244 //\r
245 UINT64 Slba; /* Starting LBA */\r
246 //\r
247 // CDW 12\r
248 //\r
249 UINT16 Nlb; /* Number of Logical Blocks */\r
250 UINT16 Rsvd1:10;\r
251 UINT16 Prinfo:4; /* Protection Info Check */\r
252 UINT16 Fua:1; /* Force Unit Access */\r
253 UINT16 Lr:1; /* Limited Retry */\r
254 //\r
255 // CDW 13\r
256 //\r
257 UINT32 Rsvd2;\r
258 //\r
259 // CDW 14\r
260 //\r
261 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
262 //\r
263 // CDW 15\r
264 //\r
265 UINT16 Lbat; /* Logical Block Application Tag */\r
266 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
267} NVME_WRITE_ZEROES;\r
268\r
269//\r
270// Compare command\r
271//\r
272typedef struct {\r
273 //\r
274 // CDW 10, 11\r
275 //\r
276 UINT64 Slba; /* Starting LBA */\r
277 //\r
278 // CDW 12\r
279 //\r
280 UINT16 Nlb; /* Number of Logical Blocks */\r
281 UINT16 Rsvd1:10;\r
282 UINT16 Prinfo:4; /* Protection Info Check */\r
283 UINT16 Fua:1; /* Force Unit Access */\r
284 UINT16 Lr:1; /* Limited Retry */\r
285 //\r
286 // CDW 13\r
287 //\r
288 UINT32 Rsvd2;\r
289 //\r
290 // CDW 14\r
291 //\r
292 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
293 //\r
294 // CDW 15\r
295 //\r
296 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
297 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
298} NVME_COMPARE;\r
299\r
300typedef union {\r
301 NVME_READ Read;\r
302 NVME_WRITE Write;\r
303 NVME_FLUSH Flush;\r
304 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;\r
305 NVME_WRITE_ZEROES WriteZeros;\r
306 NVME_COMPARE Compare;\r
307} NVME_CMD;\r
308\r
309typedef struct {\r
310 UINT16 Mp; /* Maximum Power */\r
311 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r
312 UINT8 Mps:1; /* Max Power Scale */\r
313 UINT8 Nops:1; /* Non-Operational State */\r
314 UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */\r
315 UINT32 Enlat; /* Entry Latency */\r
316 UINT32 Exlat; /* Exit Latency */\r
317 UINT8 Rrt:5; /* Relative Read Throughput */\r
318 UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r
319 UINT8 Rrl:5; /* Relative Read Leatency */\r
320 UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r
321 UINT8 Rwt:5; /* Relative Write Throughput */\r
322 UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r
323 UINT8 Rwl:5; /* Relative Write Leatency */\r
324 UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r
325 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
326} NVME_PSDESCRIPTOR;\r
327\r
328//\r
329// Identify Controller Data\r
330//\r
331typedef struct {\r
332 //\r
333 // Controller Capabilities and Features 0-255\r
334 //\r
335 UINT16 Vid; /* PCI Vendor ID */\r
336 UINT16 Ssvid; /* PCI sub-system vendor ID */\r
4ab4497c 337 UINT8 Sn[20]; /* Product serial number */\r
eb290d02
FT		 338\r
339 UINT8 Mn[40]; /* Proeduct model number */\r
340 UINT8 Fr[8]; /* Firmware Revision */\r
341 UINT8 Rab; /* Recommended Arbitration Burst */\r
4ab4497c 342 UINT8 Ieee_oui[3]; /* Organization Unique Identifier */\r
eb290d02
FT		 343 UINT8 Cmic; /* Multi-interface Capabilities */\r
344 UINT8 Mdts; /* Maximum Data Transfer Size */\r
345 UINT8 Cntlid[2]; /* Controller ID */\r
346 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r
347 //\r
348 // Admin Command Set Attributes\r
349 //\r
350 UINT16 Oacs; /* Optional Admin Command Support */\r
351 UINT8 Acl; /* Abort Command Limit */\r
352 UINT8 Aerl; /* Async Event Request Limit */\r
353 UINT8 Frmw; /* Firmware updates */\r
354 UINT8 Lpa; /* Log Page Attributes */\r
355 UINT8 Elpe; /* Error Log Page Entries */\r
356 UINT8 Npss; /* Number of Power States Support */\r
357 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
358 UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
359 UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */\r
360 //\r
361 // NVM Command Set Attributes\r
362 //\r
363 UINT8 Sqes; /* Submission Queue Entry Size */\r
364 UINT8 Cqes; /* Completion Queue Entry Size */\r
365 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r
366 UINT32 Nn; /* Number of Namespaces */\r
367 UINT16 Oncs; /* Optional NVM Command Support */\r
368 UINT16 Fuses; /* Fused Operation Support */\r
369 UINT8 Fna; /* Format NVM Attributes */\r
370 UINT8 Vwc; /* Volatile Write Cache */\r
371 UINT16 Awun; /* Atomic Write Unit Normal */\r
372 UINT16 Awupf; /* Atomic Write Unit Power Fail */\r
373 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r
374 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r
375 UINT16 Acwu; /* Atomic Compare & Write Unit */\r
376 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r
377 UINT32 Sgls; /* SGL Support */\r
378 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
379 //\r
380 // I/O Command set Attributes\r
381 //\r
382 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
383 //\r
384 // Power State Descriptors\r
385 //\r
386 NVME_PSDESCRIPTOR PsDescriptor[32];\r
387\r
388 UINT8 VendorData[1024]; /* Vendor specific data */\r
389} NVME_ADMIN_CONTROLLER_DATA;\r
390\r
391typedef struct {\r
392 UINT16 Ms; /* Metadata Size */\r
393 UINT8 Lbads; /* LBA Data Size */\r
394 UINT8 Rp:2; /* Relative Performance */\r
395 #define LBAF_RP_BEST 00b\r
396 #define LBAF_RP_BETTER 01b\r
397 #define LBAF_RP_GOOD 10b\r
398 #define LBAF_RP_DEGRADED 11b\r
399 UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */\r
400} NVME_LBAFORMAT;\r
401\r
402//\r
403// Identify Namespace Data\r
404//\r
405typedef struct {\r
406 //\r
407 // NVM Command Set Specific\r
408 //\r
409 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r
410 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r
411 UINT64 Nuse; /* Namespace Utilization */\r
412 UINT8 Nsfeat; /* Namespace Features */\r
413 UINT8 Nlbaf; /* Number of LBA Formats */\r
414 UINT8 Flbas; /* Formatted LBA size */\r
415 UINT8 Mc; /* Metadata Capabilities */\r
416 UINT8 Dpc; /* End-to-end Data Protection capabilities */\r
417 UINT8 Dps; /* End-to-end Data Protection Type Settings */\r
418 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
419 UINT8 Rescap; /* Reservation Capabilities */\r
420 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
421 UINT64 Eui64; /* IEEE Extended Unique Identifier */\r
422 //\r
423 // LBA Format\r
424 //\r
425 NVME_LBAFORMAT LbaFormat[16];\r
426\r
427 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r
428 UINT8 VendorData[3712]; /* Vendor specific data */\r
429} NVME_ADMIN_NAMESPACE_DATA;\r
430\r
431//\r
432// NvmExpress Admin Identify Cmd\r
433//\r
434typedef struct {\r
435 //\r
436 // CDW 10\r
437 //\r
438 UINT32 Cns:2;\r
439 UINT32 Rsvd1:30;\r
440} NVME_ADMIN_IDENTIFY;\r
441\r
442//\r
443// NvmExpress Admin Create I/O Completion Queue\r
444//\r
445typedef struct {\r
446 //\r
447 // CDW 10\r
448 //\r
449 UINT32 Qid:16; /* Queue Identifier */\r
450 UINT32 Qsize:16; /* Queue Size */\r
451\r
452 //\r
453 // CDW 11\r
454 //\r
455 UINT32 Pc:1; /* Physically Contiguous */\r
456 UINT32 Ien:1; /* Interrupts Enabled */\r
457 UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */\r
4ab4497c 458 UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/\r
eb290d02
FT		 459} NVME_ADMIN_CRIOCQ;\r
460\r
461//\r
462// NvmExpress Admin Create I/O Submission Queue\r
463//\r
464typedef struct {\r
465 //\r
466 // CDW 10\r
467 //\r
468 UINT32 Qid:16; /* Queue Identifier */\r
469 UINT32 Qsize:16; /* Queue Size */\r
470\r
471 //\r
472 // CDW 11\r
473 //\r
474 UINT32 Pc:1; /* Physically Contiguous */\r
475 UINT32 Qprio:2; /* Queue Priority */\r
476 UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */\r
477 UINT32 Cqid:16; /* Completion Queue ID */\r
478} NVME_ADMIN_CRIOSQ;\r
479\r
480//\r
481// NvmExpress Admin Delete I/O Completion Queue\r
482//\r
483typedef struct {\r
484 //\r
485 // CDW 10\r
486 //\r
487 UINT16 Qid;\r
488 UINT16 Rsvd1;\r
489} NVME_ADMIN_DEIOCQ;\r
490\r
491//\r
492// NvmExpress Admin Delete I/O Submission Queue\r
493//\r
494typedef struct {\r
495 //\r
496 // CDW 10\r
497 //\r
498 UINT16 Qid;\r
499 UINT16 Rsvd1;\r
500} NVME_ADMIN_DEIOSQ;\r
501\r
502//\r
503// NvmExpress Admin Abort Command\r
504//\r
505typedef struct {\r
506 //\r
507 // CDW 10\r
508 //\r
509 UINT32 Sqid:16; /* Submission Queue identifier */\r
510 UINT32 Cid:16; /* Command Identifier */\r
511} NVME_ADMIN_ABORT;\r
512\r
513//\r
514// NvmExpress Admin Firmware Activate Command\r
515//\r
516typedef struct {\r
517 //\r
518 // CDW 10\r
519 //\r
520 UINT32 Fs:3; /* Submission Queue identifier */\r
521 UINT32 Aa:2; /* Command Identifier */\r
522 UINT32 Rsvd1:27;\r
523} NVME_ADMIN_FIRMWARE_ACTIVATE;\r
524\r
525//\r
526// NvmExpress Admin Firmware Image Download Command\r
527//\r
528typedef struct {\r
529 //\r
530 // CDW 10\r
531 //\r
532 UINT32 Numd; /* Number of Dwords */\r
533 //\r
534 // CDW 11\r
535 //\r
536 UINT32 Ofst; /* Offset */\r
537} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r
538\r
539//\r
540// NvmExpress Admin Get Features Command\r
541//\r
542typedef struct {\r
543 //\r
544 // CDW 10\r
545 //\r
546 UINT32 Fid:8; /* Feature Identifier */\r
547 UINT32 Sel:3; /* Select */\r
548 UINT32 Rsvd1:21;\r
549} NVME_ADMIN_GET_FEATURES;\r
550\r
551//\r
552// NvmExpress Admin Get Log Page Command\r
553//\r
554typedef struct {\r
555 //\r
556 // CDW 10\r
557 //\r
558 UINT32 Lid:8; /* Log Page Identifier */\r
559 #define LID_ERROR_INFO\r
560 #define LID_SMART_INFO\r
561 #define LID_FW_SLOT_INFO\r
562 UINT32 Rsvd1:8;\r
563 UINT32 Numd:12; /* Number of Dwords */\r
564 UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */\r
565} NVME_ADMIN_GET_LOG_PAGE;\r
566\r
567//\r
568// NvmExpress Admin Set Features Command\r
569//\r
570typedef struct {\r
571 //\r
572 // CDW 10\r
573 //\r
574 UINT32 Fid:8; /* Feature Identifier */\r
575 UINT32 Rsvd1:23;\r
576 UINT32 Sv:1; /* Save */\r
577} NVME_ADMIN_SET_FEATURES;\r
578\r
579//\r
580// NvmExpress Admin Format NVM Command\r
581//\r
582typedef struct {\r
583 //\r
584 // CDW 10\r
585 //\r
586 UINT32 Lbaf:4; /* LBA Format */\r
587 UINT32 Ms:1; /* Metadata Settings */\r
588 UINT32 Pi:3; /* Protection Information */\r
589 UINT32 Pil:1; /* Protection Information Location */\r
590 UINT32 Ses:3; /* Secure Erase Settings */\r
591 UINT32 Rsvd1:20;\r
592} NVME_ADMIN_FORMAT_NVM;\r
593\r
594//\r
595// NvmExpress Admin Security Receive Command\r
596//\r
597typedef struct {\r
598 //\r
599 // CDW 10\r
600 //\r
601 UINT32 Rsvd1:8;\r
602 UINT32 Spsp:16; /* SP Specific */\r
603 UINT32 Secp:8; /* Security Protocol */\r
604 //\r
605 // CDW 11\r
606 //\r
607 UINT32 Al; /* Allocation Length */\r
608} NVME_ADMIN_SECURITY_RECEIVE;\r
609\r
610//\r
611// NvmExpress Admin Security Send Command\r
612//\r
613typedef struct {\r
614 //\r
615 // CDW 10\r
616 //\r
617 UINT32 Rsvd1:8;\r
618 UINT32 Spsp:16; /* SP Specific */\r
619 UINT32 Secp:8; /* Security Protocol */\r
620 //\r
621 // CDW 11\r
622 //\r
623 UINT32 Tl; /* Transfer Length */\r
624} NVME_ADMIN_SECURITY_SEND;\r
625\r
626typedef union {\r
627 NVME_ADMIN_IDENTIFY Identify;\r
628 NVME_ADMIN_CRIOCQ CrIoCq;\r
629 NVME_ADMIN_CRIOSQ CrIoSq;\r
630 NVME_ADMIN_DEIOCQ DeIoCq;\r
631 NVME_ADMIN_DEIOSQ DeIoSq;\r
632 NVME_ADMIN_ABORT Abort;\r
633 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;\r
634 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;\r
635 NVME_ADMIN_GET_FEATURES GetFeatures;\r
636 NVME_ADMIN_GET_LOG_PAGE GetLogPage;\r
637 NVME_ADMIN_SET_FEATURES SetFeatures;\r
638 NVME_ADMIN_FORMAT_NVM FormatNvm;\r
639 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;\r
640 NVME_ADMIN_SECURITY_SEND SecuritySend;\r
641} NVME_ADMIN_CMD;\r
642\r
643typedef struct {\r
644 UINT32 Cdw10;\r
645 UINT32 Cdw11;\r
646 UINT32 Cdw12;\r
647 UINT32 Cdw13;\r
648 UINT32 Cdw14;\r
649 UINT32 Cdw15;\r
650} NVME_RAW;\r
651\r
652typedef union {\r
653 NVME_ADMIN_CMD Admin; // Union of Admin commands\r
654 NVME_CMD Nvm; // Union of Nvm commands\r
655 NVME_RAW Raw;\r
656} NVME_PAYLOAD;\r
657\r
658//\r
659// Submission Queue\r
660//\r
661typedef struct {\r
662 //\r
663 // CDW 0, Common to all comnmands\r
664 //\r
665 UINT8 Opc; // Opcode\r
666 UINT8 Fuse:2; // Fused Operation\r
667 UINT8 Rsvd1:5;\r
668 UINT8 Psdt:1; // PRP or SGL for Data Transfer\r
669 UINT16 Cid; // Command Identifier\r
670\r
671 //\r
672 // CDW 1\r
673 //\r
674 UINT32 Nsid; // Namespace Identifier\r
675\r
676 //\r
677 // CDW 2,3\r
678 //\r
679 UINT64 Rsvd2;\r
680\r
681 //\r
682 // CDW 4,5\r
683 //\r
684 UINT64 Mptr; // Metadata Pointer\r
685\r
686 //\r
687 // CDW 6-9\r
688 //\r
689 UINT64 Prp[2]; // First and second PRP entries\r
690\r
691 NVME_PAYLOAD Payload;\r
692\r
693} NVME_SQ;\r
694\r
695//\r
696// Completion Queue\r
697//\r
698typedef struct {\r
699 //\r
700 // CDW 0\r
701 //\r
702 UINT32 Dword0;\r
703 //\r
704 // CDW 1\r
705 //\r
706 UINT32 Rsvd1;\r
707 //\r
708 // CDW 2\r
709 //\r
710 UINT16 Sqhd; // Submission Queue Head Pointer\r
711 UINT16 Sqid; // Submission Queue Identifier\r
712 //\r
713 // CDW 3\r
714 //\r
715 UINT16 Cid; // Command Identifier\r
716 UINT16 Pt:1; // Phase Tag\r
717 UINT16 Sc:8; // Status Code\r
718 UINT16 Sct:3; // Status Code Type\r
719 UINT16 Rsvd2:2;\r
720 UINT16 Mo:1; // More\r
4ab4497c 721 UINT16 Dnr:1; // Do Not Retry\r
eb290d02
FT		 722} NVME_CQ;\r
723\r
724//\r
725// Nvm Express Admin cmd opcodes\r
726//\r
727#define NVME_ADMIN_CRIOSQ_OPC 1\r
728#define NVME_ADMIN_CRIOCQ_OPC 5\r
729#define NVME_ADMIN_IDENTIFY_OPC 6\r
730\r
731#define NVME_IO_FLUSH_OPC 0\r
732#define NVME_IO_WRITE_OPC 1\r
733#define NVME_IO_READ_OPC 2\r
734\r
735//\r
736// Offset from the beginning of private data queue buffer\r
737//\r
738#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE\r
739\r
740/**\r
741 Initialize the Nvm Express controller.\r
742\r
743 @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
744\r
745 @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.\r
746 @retval Others A device error occurred while initializing the controller.\r
747\r
748**/\r
749EFI_STATUS\r
750NvmeControllerInit (\r
751 IN NVME_CONTROLLER_PRIVATE_DATA *Private\r
752 );\r
753\r
754/**\r
755 Get identify controller data.\r
756\r
757 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
758 @param Buffer The buffer used to store the identify controller data.\r
759\r
760 @return EFI_SUCCESS Successfully get the identify controller data.\r
761 @return EFI_DEVICE_ERROR Fail to get the identify controller data.\r
762\r
763**/\r
764EFI_STATUS\r
765NvmeIdentifyController (\r
766 IN NVME_CONTROLLER_PRIVATE_DATA *Private,\r
767 IN VOID *Buffer\r
768 );\r
769\r
770/**\r
771 Get specified identify namespace data.\r
772\r
773 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
774 @param NamespaceId The specified namespace identifier.\r
775 @param Buffer The buffer used to store the identify namespace data.\r
776\r
777 @return EFI_SUCCESS Successfully get the identify namespace data.\r
778 @return EFI_DEVICE_ERROR Fail to get the identify namespace data.\r
779\r
780**/\r
781EFI_STATUS\r
782NvmeIdentifyNamespace (\r
783 IN NVME_CONTROLLER_PRIVATE_DATA *Private,\r
784 IN UINT32 NamespaceId,\r
785 IN VOID *Buffer\r
786 );\r
787\r
788#pragma pack()\r
789\r
790#endif\r
791\r
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