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MdeModulePkg/NvmExpressDxe: Check if CSTS.RDY is 0 to wait NVMe Host controller disable
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.h
1 /** @file
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
3 NVM Express specification.
4
5 Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _NVME_HCI_H_
17 #define _NVME_HCI_H_
18
19 #define NVME_BAR 0
20
21 //
22 // controller register offsets
23 //
24 #define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
25 #define NVME_VER_OFFSET 0x0008 // Version
26 #define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
27 #define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
28 #define NVME_CC_OFFSET 0x0014 // Controller Configuration
29 #define NVME_CSTS_OFFSET 0x001c // Controller Status
30 #define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
31 #define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
32 #define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
33 #define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
34 #define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
35 #define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
36
37 //
38 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
39 // Get the doorbell stride bit shift value from the controller capabilities.
40 //
41 #define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
42 #define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
43
44
45 #pragma pack(1)
46
47 //
48 // 3.1.1 Offset 00h: CAP - Controller Capabilities
49 //
50 typedef struct {
51 UINT16 Mqes; // Maximum Queue Entries Supported
52 UINT8 Cqr:1; // Contiguous Queues Required
53 UINT8 Ams:2; // Arbitration Mechanism Supported
54 UINT8 Rsvd1:5;
55 UINT8 To; // Timeout
56 UINT16 Dstrd:4;
57 UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS
58 UINT16 Css:4; // Command Sets Supported - Bit 37
59 UINT16 Rsvd3:7;
60 UINT8 Mpsmin:4;
61 UINT8 Mpsmax:4;
62 UINT8 Rsvd4;
63 } NVME_CAP;
64
65 //
66 // 3.1.2 Offset 08h: VS - Version
67 //
68 typedef struct {
69 UINT16 Mnr; // Minor version number
70 UINT16 Mjr; // Major version number
71 } NVME_VER;
72
73 //
74 // 3.1.5 Offset 14h: CC - Controller Configuration
75 //
76 typedef struct {
77 UINT16 En:1; // Enable
78 UINT16 Rsvd1:3;
79 UINT16 Css:3; // I/O Command Set Selected
80 UINT16 Mps:4; // Memory Page Size
81 UINT16 Ams:3; // Arbitration Mechanism Selected
82 UINT16 Shn:2; // Shutdown Notification
83 UINT8 Iosqes:4; // I/O Submission Queue Entry Size
84 UINT8 Iocqes:4; // I/O Completion Queue Entry Size
85 UINT8 Rsvd2;
86 } NVME_CC;
87
88 //
89 // 3.1.6 Offset 1Ch: CSTS - Controller Status
90 //
91 typedef struct {
92 UINT32 Rdy:1; // Ready
93 UINT32 Cfs:1; // Controller Fatal Status
94 UINT32 Shst:2; // Shutdown Status
95 UINT32 Nssro:1; // NVM Subsystem Reset Occurred
96 UINT32 Rsvd1:27;
97 } NVME_CSTS;
98
99 //
100 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
101 //
102 typedef struct {
103 UINT16 Asqs:12; // Submission Queue Size
104 UINT16 Rsvd1:4;
105 UINT16 Acqs:12; // Completion Queue Size
106 UINT16 Rsvd2:4;
107 } NVME_AQA;
108
109 //
110 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
111 //
112 typedef struct {
113 UINT64 Rsvd1:12;
114 UINT64 Asqb:52; // Admin Submission Queue Base Address
115 } NVME_ASQ;
116
117 //
118 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
119 //
120 typedef struct {
121 UINT64 Rsvd1:12;
122 UINT64 Acqb:52; // Admin Completion Queue Base Address
123 } NVME_ACQ;
124
125 //
126 // 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
127 //
128 typedef struct {
129 UINT16 Sqt;
130 UINT16 Rsvd1;
131 } NVME_SQTDBL;
132
133 //
134 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
135 //
136 typedef struct {
137 UINT16 Cqh;
138 UINT16 Rsvd1;
139 } NVME_CQHDBL;
140
141 //
142 // NVM command set structures
143 //
144 // Read Command
145 //
146 typedef struct {
147 //
148 // CDW 10, 11
149 //
150 UINT64 Slba; /* Starting Sector Address */
151 //
152 // CDW 12
153 //
154 UINT16 Nlb; /* Number of Sectors */
155 UINT16 Rsvd1:10;
156 UINT16 Prinfo:4; /* Protection Info Check */
157 UINT16 Fua:1; /* Force Unit Access */
158 UINT16 Lr:1; /* Limited Retry */
159 //
160 // CDW 13
161 //
162 UINT32 Af:4; /* Access Frequency */
163 UINT32 Al:2; /* Access Latency */
164 UINT32 Sr:1; /* Sequential Request */
165 UINT32 In:1; /* Incompressible */
166 UINT32 Rsvd2:24;
167 //
168 // CDW 14
169 //
170 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
171 //
172 // CDW 15
173 //
174 UINT16 Elbat; /* Expected Logical Block Application Tag */
175 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
176 } NVME_READ;
177
178 //
179 // Write Command
180 //
181 typedef struct {
182 //
183 // CDW 10, 11
184 //
185 UINT64 Slba; /* Starting Sector Address */
186 //
187 // CDW 12
188 //
189 UINT16 Nlb; /* Number of Sectors */
190 UINT16 Rsvd1:10;
191 UINT16 Prinfo:4; /* Protection Info Check */
192 UINT16 Fua:1; /* Force Unit Access */
193 UINT16 Lr:1; /* Limited Retry */
194 //
195 // CDW 13
196 //
197 UINT32 Af:4; /* Access Frequency */
198 UINT32 Al:2; /* Access Latency */
199 UINT32 Sr:1; /* Sequential Request */
200 UINT32 In:1; /* Incompressible */
201 UINT32 Rsvd2:24;
202 //
203 // CDW 14
204 //
205 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
206 //
207 // CDW 15
208 //
209 UINT16 Lbat; /* Logical Block Application Tag */
210 UINT16 Lbatm; /* Logical Block Application Tag Mask */
211 } NVME_WRITE;
212
213 //
214 // Flush
215 //
216 typedef struct {
217 //
218 // CDW 10
219 //
220 UINT32 Flush; /* Flush */
221 } NVME_FLUSH;
222
223 //
224 // Write Uncorrectable command
225 //
226 typedef struct {
227 //
228 // CDW 10, 11
229 //
230 UINT64 Slba; /* Starting LBA */
231 //
232 // CDW 12
233 //
234 UINT32 Nlb:16; /* Number of Logical Blocks */
235 UINT32 Rsvd1:16;
236 } NVME_WRITE_UNCORRECTABLE;
237
238 //
239 // Write Zeroes command
240 //
241 typedef struct {
242 //
243 // CDW 10, 11
244 //
245 UINT64 Slba; /* Starting LBA */
246 //
247 // CDW 12
248 //
249 UINT16 Nlb; /* Number of Logical Blocks */
250 UINT16 Rsvd1:10;
251 UINT16 Prinfo:4; /* Protection Info Check */
252 UINT16 Fua:1; /* Force Unit Access */
253 UINT16 Lr:1; /* Limited Retry */
254 //
255 // CDW 13
256 //
257 UINT32 Rsvd2;
258 //
259 // CDW 14
260 //
261 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
262 //
263 // CDW 15
264 //
265 UINT16 Lbat; /* Logical Block Application Tag */
266 UINT16 Lbatm; /* Logical Block Application Tag Mask */
267 } NVME_WRITE_ZEROES;
268
269 //
270 // Compare command
271 //
272 typedef struct {
273 //
274 // CDW 10, 11
275 //
276 UINT64 Slba; /* Starting LBA */
277 //
278 // CDW 12
279 //
280 UINT16 Nlb; /* Number of Logical Blocks */
281 UINT16 Rsvd1:10;
282 UINT16 Prinfo:4; /* Protection Info Check */
283 UINT16 Fua:1; /* Force Unit Access */
284 UINT16 Lr:1; /* Limited Retry */
285 //
286 // CDW 13
287 //
288 UINT32 Rsvd2;
289 //
290 // CDW 14
291 //
292 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
293 //
294 // CDW 15
295 //
296 UINT16 Elbat; /* Expected Logical Block Application Tag */
297 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
298 } NVME_COMPARE;
299
300 typedef union {
301 NVME_READ Read;
302 NVME_WRITE Write;
303 NVME_FLUSH Flush;
304 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;
305 NVME_WRITE_ZEROES WriteZeros;
306 NVME_COMPARE Compare;
307 } NVME_CMD;
308
309 typedef struct {
310 UINT16 Mp; /* Maximum Power */
311 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
312 UINT8 Mps:1; /* Max Power Scale */
313 UINT8 Nops:1; /* Non-Operational State */
314 UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */
315 UINT32 Enlat; /* Entry Latency */
316 UINT32 Exlat; /* Exit Latency */
317 UINT8 Rrt:5; /* Relative Read Throughput */
318 UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */
319 UINT8 Rrl:5; /* Relative Read Leatency */
320 UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */
321 UINT8 Rwt:5; /* Relative Write Throughput */
322 UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */
323 UINT8 Rwl:5; /* Relative Write Leatency */
324 UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */
325 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
326 } NVME_PSDESCRIPTOR;
327
328 //
329 // Identify Controller Data
330 //
331 typedef struct {
332 //
333 // Controller Capabilities and Features 0-255
334 //
335 UINT16 Vid; /* PCI Vendor ID */
336 UINT16 Ssvid; /* PCI sub-system vendor ID */
337 UINT8 Sn[20]; /* Product serial number */
338
339 UINT8 Mn[40]; /* Proeduct model number */
340 UINT8 Fr[8]; /* Firmware Revision */
341 UINT8 Rab; /* Recommended Arbitration Burst */
342 UINT8 Ieee_oui[3]; /* Organization Unique Identifier */
343 UINT8 Cmic; /* Multi-interface Capabilities */
344 UINT8 Mdts; /* Maximum Data Transfer Size */
345 UINT8 Cntlid[2]; /* Controller ID */
346 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
347 //
348 // Admin Command Set Attributes
349 //
350 UINT16 Oacs; /* Optional Admin Command Support */
351 UINT8 Acl; /* Abort Command Limit */
352 UINT8 Aerl; /* Async Event Request Limit */
353 UINT8 Frmw; /* Firmware updates */
354 UINT8 Lpa; /* Log Page Attributes */
355 UINT8 Elpe; /* Error Log Page Entries */
356 UINT8 Npss; /* Number of Power States Support */
357 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
358 UINT8 Apsta; /* Autonomous Power State Transition Attributes */
359 UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */
360 //
361 // NVM Command Set Attributes
362 //
363 UINT8 Sqes; /* Submission Queue Entry Size */
364 UINT8 Cqes; /* Completion Queue Entry Size */
365 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
366 UINT32 Nn; /* Number of Namespaces */
367 UINT16 Oncs; /* Optional NVM Command Support */
368 UINT16 Fuses; /* Fused Operation Support */
369 UINT8 Fna; /* Format NVM Attributes */
370 UINT8 Vwc; /* Volatile Write Cache */
371 UINT16 Awun; /* Atomic Write Unit Normal */
372 UINT16 Awupf; /* Atomic Write Unit Power Fail */
373 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
374 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
375 UINT16 Acwu; /* Atomic Compare & Write Unit */
376 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
377 UINT32 Sgls; /* SGL Support */
378 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
379 //
380 // I/O Command set Attributes
381 //
382 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
383 //
384 // Power State Descriptors
385 //
386 NVME_PSDESCRIPTOR PsDescriptor[32];
387
388 UINT8 VendorData[1024]; /* Vendor specific data */
389 } NVME_ADMIN_CONTROLLER_DATA;
390
391 typedef struct {
392 UINT16 Ms; /* Metadata Size */
393 UINT8 Lbads; /* LBA Data Size */
394 UINT8 Rp:2; /* Relative Performance */
395 #define LBAF_RP_BEST 00b
396 #define LBAF_RP_BETTER 01b
397 #define LBAF_RP_GOOD 10b
398 #define LBAF_RP_DEGRADED 11b
399 UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */
400 } NVME_LBAFORMAT;
401
402 //
403 // Identify Namespace Data
404 //
405 typedef struct {
406 //
407 // NVM Command Set Specific
408 //
409 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
410 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
411 UINT64 Nuse; /* Namespace Utilization */
412 UINT8 Nsfeat; /* Namespace Features */
413 UINT8 Nlbaf; /* Number of LBA Formats */
414 UINT8 Flbas; /* Formatted LBA size */
415 UINT8 Mc; /* Metadata Capabilities */
416 UINT8 Dpc; /* End-to-end Data Protection capabilities */
417 UINT8 Dps; /* End-to-end Data Protection Type Settings */
418 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
419 UINT8 Rescap; /* Reservation Capabilities */
420 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
421 UINT64 Eui64; /* IEEE Extended Unique Identifier */
422 //
423 // LBA Format
424 //
425 NVME_LBAFORMAT LbaFormat[16];
426
427 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
428 UINT8 VendorData[3712]; /* Vendor specific data */
429 } NVME_ADMIN_NAMESPACE_DATA;
430
431 //
432 // NvmExpress Admin Identify Cmd
433 //
434 typedef struct {
435 //
436 // CDW 10
437 //
438 UINT32 Cns:2;
439 UINT32 Rsvd1:30;
440 } NVME_ADMIN_IDENTIFY;
441
442 //
443 // NvmExpress Admin Create I/O Completion Queue
444 //
445 typedef struct {
446 //
447 // CDW 10
448 //
449 UINT32 Qid:16; /* Queue Identifier */
450 UINT32 Qsize:16; /* Queue Size */
451
452 //
453 // CDW 11
454 //
455 UINT32 Pc:1; /* Physically Contiguous */
456 UINT32 Ien:1; /* Interrupts Enabled */
457 UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */
458 UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/
459 } NVME_ADMIN_CRIOCQ;
460
461 //
462 // NvmExpress Admin Create I/O Submission Queue
463 //
464 typedef struct {
465 //
466 // CDW 10
467 //
468 UINT32 Qid:16; /* Queue Identifier */
469 UINT32 Qsize:16; /* Queue Size */
470
471 //
472 // CDW 11
473 //
474 UINT32 Pc:1; /* Physically Contiguous */
475 UINT32 Qprio:2; /* Queue Priority */
476 UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */
477 UINT32 Cqid:16; /* Completion Queue ID */
478 } NVME_ADMIN_CRIOSQ;
479
480 //
481 // NvmExpress Admin Delete I/O Completion Queue
482 //
483 typedef struct {
484 //
485 // CDW 10
486 //
487 UINT16 Qid;
488 UINT16 Rsvd1;
489 } NVME_ADMIN_DEIOCQ;
490
491 //
492 // NvmExpress Admin Delete I/O Submission Queue
493 //
494 typedef struct {
495 //
496 // CDW 10
497 //
498 UINT16 Qid;
499 UINT16 Rsvd1;
500 } NVME_ADMIN_DEIOSQ;
501
502 //
503 // NvmExpress Admin Abort Command
504 //
505 typedef struct {
506 //
507 // CDW 10
508 //
509 UINT32 Sqid:16; /* Submission Queue identifier */
510 UINT32 Cid:16; /* Command Identifier */
511 } NVME_ADMIN_ABORT;
512
513 //
514 // NvmExpress Admin Firmware Activate Command
515 //
516 typedef struct {
517 //
518 // CDW 10
519 //
520 UINT32 Fs:3; /* Submission Queue identifier */
521 UINT32 Aa:2; /* Command Identifier */
522 UINT32 Rsvd1:27;
523 } NVME_ADMIN_FIRMWARE_ACTIVATE;
524
525 //
526 // NvmExpress Admin Firmware Image Download Command
527 //
528 typedef struct {
529 //
530 // CDW 10
531 //
532 UINT32 Numd; /* Number of Dwords */
533 //
534 // CDW 11
535 //
536 UINT32 Ofst; /* Offset */
537 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
538
539 //
540 // NvmExpress Admin Get Features Command
541 //
542 typedef struct {
543 //
544 // CDW 10
545 //
546 UINT32 Fid:8; /* Feature Identifier */
547 UINT32 Sel:3; /* Select */
548 UINT32 Rsvd1:21;
549 } NVME_ADMIN_GET_FEATURES;
550
551 //
552 // NvmExpress Admin Get Log Page Command
553 //
554 typedef struct {
555 //
556 // CDW 10
557 //
558 UINT32 Lid:8; /* Log Page Identifier */
559 #define LID_ERROR_INFO
560 #define LID_SMART_INFO
561 #define LID_FW_SLOT_INFO
562 UINT32 Rsvd1:8;
563 UINT32 Numd:12; /* Number of Dwords */
564 UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */
565 } NVME_ADMIN_GET_LOG_PAGE;
566
567 //
568 // NvmExpress Admin Set Features Command
569 //
570 typedef struct {
571 //
572 // CDW 10
573 //
574 UINT32 Fid:8; /* Feature Identifier */
575 UINT32 Rsvd1:23;
576 UINT32 Sv:1; /* Save */
577 } NVME_ADMIN_SET_FEATURES;
578
579 //
580 // NvmExpress Admin Format NVM Command
581 //
582 typedef struct {
583 //
584 // CDW 10
585 //
586 UINT32 Lbaf:4; /* LBA Format */
587 UINT32 Ms:1; /* Metadata Settings */
588 UINT32 Pi:3; /* Protection Information */
589 UINT32 Pil:1; /* Protection Information Location */
590 UINT32 Ses:3; /* Secure Erase Settings */
591 UINT32 Rsvd1:20;
592 } NVME_ADMIN_FORMAT_NVM;
593
594 //
595 // NvmExpress Admin Security Receive Command
596 //
597 typedef struct {
598 //
599 // CDW 10
600 //
601 UINT32 Rsvd1:8;
602 UINT32 Spsp:16; /* SP Specific */
603 UINT32 Secp:8; /* Security Protocol */
604 //
605 // CDW 11
606 //
607 UINT32 Al; /* Allocation Length */
608 } NVME_ADMIN_SECURITY_RECEIVE;
609
610 //
611 // NvmExpress Admin Security Send Command
612 //
613 typedef struct {
614 //
615 // CDW 10
616 //
617 UINT32 Rsvd1:8;
618 UINT32 Spsp:16; /* SP Specific */
619 UINT32 Secp:8; /* Security Protocol */
620 //
621 // CDW 11
622 //
623 UINT32 Tl; /* Transfer Length */
624 } NVME_ADMIN_SECURITY_SEND;
625
626 typedef union {
627 NVME_ADMIN_IDENTIFY Identify;
628 NVME_ADMIN_CRIOCQ CrIoCq;
629 NVME_ADMIN_CRIOSQ CrIoSq;
630 NVME_ADMIN_DEIOCQ DeIoCq;
631 NVME_ADMIN_DEIOSQ DeIoSq;
632 NVME_ADMIN_ABORT Abort;
633 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;
634 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;
635 NVME_ADMIN_GET_FEATURES GetFeatures;
636 NVME_ADMIN_GET_LOG_PAGE GetLogPage;
637 NVME_ADMIN_SET_FEATURES SetFeatures;
638 NVME_ADMIN_FORMAT_NVM FormatNvm;
639 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;
640 NVME_ADMIN_SECURITY_SEND SecuritySend;
641 } NVME_ADMIN_CMD;
642
643 typedef struct {
644 UINT32 Cdw10;
645 UINT32 Cdw11;
646 UINT32 Cdw12;
647 UINT32 Cdw13;
648 UINT32 Cdw14;
649 UINT32 Cdw15;
650 } NVME_RAW;
651
652 typedef union {
653 NVME_ADMIN_CMD Admin; // Union of Admin commands
654 NVME_CMD Nvm; // Union of Nvm commands
655 NVME_RAW Raw;
656 } NVME_PAYLOAD;
657
658 //
659 // Submission Queue
660 //
661 typedef struct {
662 //
663 // CDW 0, Common to all comnmands
664 //
665 UINT8 Opc; // Opcode
666 UINT8 Fuse:2; // Fused Operation
667 UINT8 Rsvd1:5;
668 UINT8 Psdt:1; // PRP or SGL for Data Transfer
669 UINT16 Cid; // Command Identifier
670
671 //
672 // CDW 1
673 //
674 UINT32 Nsid; // Namespace Identifier
675
676 //
677 // CDW 2,3
678 //
679 UINT64 Rsvd2;
680
681 //
682 // CDW 4,5
683 //
684 UINT64 Mptr; // Metadata Pointer
685
686 //
687 // CDW 6-9
688 //
689 UINT64 Prp[2]; // First and second PRP entries
690
691 NVME_PAYLOAD Payload;
692
693 } NVME_SQ;
694
695 //
696 // Completion Queue
697 //
698 typedef struct {
699 //
700 // CDW 0
701 //
702 UINT32 Dword0;
703 //
704 // CDW 1
705 //
706 UINT32 Rsvd1;
707 //
708 // CDW 2
709 //
710 UINT16 Sqhd; // Submission Queue Head Pointer
711 UINT16 Sqid; // Submission Queue Identifier
712 //
713 // CDW 3
714 //
715 UINT16 Cid; // Command Identifier
716 UINT16 Pt:1; // Phase Tag
717 UINT16 Sc:8; // Status Code
718 UINT16 Sct:3; // Status Code Type
719 UINT16 Rsvd2:2;
720 UINT16 Mo:1; // More
721 UINT16 Dnr:1; // Do Not Retry
722 } NVME_CQ;
723
724 //
725 // Nvm Express Admin cmd opcodes
726 //
727 #define NVME_ADMIN_CRIOSQ_OPC 1
728 #define NVME_ADMIN_CRIOCQ_OPC 5
729 #define NVME_ADMIN_IDENTIFY_OPC 6
730
731 #define NVME_IO_FLUSH_OPC 0
732 #define NVME_IO_WRITE_OPC 1
733 #define NVME_IO_READ_OPC 2
734
735 //
736 // Offset from the beginning of private data queue buffer
737 //
738 #define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE
739
740 /**
741 Initialize the Nvm Express controller.
742
743 @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
744
745 @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.
746 @retval Others A device error occurred while initializing the controller.
747
748 **/
749 EFI_STATUS
750 NvmeControllerInit (
751 IN NVME_CONTROLLER_PRIVATE_DATA *Private
752 );
753
754 /**
755 Get identify controller data.
756
757 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
758 @param Buffer The buffer used to store the identify controller data.
759
760 @return EFI_SUCCESS Successfully get the identify controller data.
761 @return EFI_DEVICE_ERROR Fail to get the identify controller data.
762
763 **/
764 EFI_STATUS
765 NvmeIdentifyController (
766 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
767 IN VOID *Buffer
768 );
769
770 /**
771 Get specified identify namespace data.
772
773 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
774 @param NamespaceId The specified namespace identifier.
775 @param Buffer The buffer used to store the identify namespace data.
776
777 @return EFI_SUCCESS Successfully get the identify namespace data.
778 @return EFI_DEVICE_ERROR Fail to get the identify namespace data.
779
780 **/
781 EFI_STATUS
782 NvmeIdentifyNamespace (
783 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
784 IN UINT32 NamespaceId,
785 IN VOID *Buffer
786 );
787
788 #pragma pack()
789
790 #endif
791
EFI Development Kit II mirror for PVE