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1 | /** @file\r |
2 | The NvmExpressPei driver is used to manage non-volatile memory subsystem\r | |
3 | which follows NVM Express specification at PEI phase.\r | |
4 | \r | |
5 | Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r | |
6 | \r | |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions\r | |
9 | of the BSD License which accompanies this distribution. The\r | |
10 | full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #ifndef _NVM_EXPRESS_PEI_H_\r | |
19 | #define _NVM_EXPRESS_PEI_H_\r | |
20 | \r | |
21 | #include <PiPei.h>\r | |
22 | \r | |
23 | #include <IndustryStandard/Nvme.h>\r | |
24 | \r | |
25 | #include <Ppi/NvmExpressHostController.h>\r | |
26 | #include <Ppi/BlockIo.h>\r | |
27 | #include <Ppi/BlockIo2.h>\r | |
28 | #include <Ppi/IoMmu.h>\r | |
29 | #include <Ppi/EndOfPeiPhase.h>\r | |
30 | \r | |
31 | #include <Library/DebugLib.h>\r | |
32 | #include <Library/PeiServicesLib.h>\r | |
33 | #include <Library/MemoryAllocationLib.h>\r | |
34 | #include <Library/BaseMemoryLib.h>\r | |
35 | #include <Library/IoLib.h>\r | |
b8b69433 HW |
36 | #include <Library/TimerLib.h>\r |
37 | \r | |
38 | //\r | |
39 | // Structure forward declarations\r | |
40 | //\r | |
41 | typedef struct _PEI_NVME_NAMESPACE_INFO PEI_NVME_NAMESPACE_INFO;\r | |
42 | typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA PEI_NVME_CONTROLLER_PRIVATE_DATA;\r | |
43 | \r | |
44 | #include "NvmExpressPeiHci.h"\r | |
45 | #include "NvmExpressPeiPassThru.h"\r | |
46 | #include "NvmExpressPeiBlockIo.h"\r | |
47 | \r | |
48 | //\r | |
49 | // NVME PEI driver implementation related definitions\r | |
50 | //\r | |
51 | #define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ\r | |
52 | #define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based\r | |
53 | #define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based\r | |
54 | #define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based\r | |
55 | #define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based\r | |
56 | #define NVME_PRP_SIZE (8) // Pages of PRP list\r | |
57 | \r | |
58 | #define NVME_MEM_MAX_PAGES \\r | |
59 | ( \\r | |
60 | 1 /* ASQ */ + \\r | |
61 | 1 /* ACQ */ + \\r | |
62 | 1 /* SQs */ + \\r | |
63 | 1 /* CQs */ + \\r | |
64 | NVME_PRP_SIZE) /* PRPs */\r | |
65 | \r | |
66 | #define NVME_ADMIN_QUEUE 0x00\r | |
67 | #define NVME_IO_QUEUE 0x01\r | |
68 | #define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit\r | |
69 | #define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit\r | |
70 | \r | |
71 | //\r | |
72 | // Nvme namespace data structure.\r | |
73 | //\r | |
74 | struct _PEI_NVME_NAMESPACE_INFO {\r | |
75 | UINT32 NamespaceId;\r | |
76 | UINT64 NamespaceUuid;\r | |
77 | EFI_PEI_BLOCK_IO2_MEDIA Media;\r | |
78 | \r | |
79 | PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;\r | |
80 | };\r | |
81 | \r | |
82 | //\r | |
83 | // Unique signature for private data structure.\r | |
84 | //\r | |
85 | #define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')\r | |
86 | \r | |
87 | //\r | |
88 | // Nvme controller private data structure.\r | |
89 | //\r | |
90 | struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {\r | |
91 | UINT32 Signature;\r | |
92 | UINTN MmioBase;\r | |
93 | EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;\r | |
94 | EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;\r | |
95 | EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;\r | |
96 | EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;\r | |
97 | EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r | |
98 | \r | |
99 | //\r | |
100 | // Pointer to identify controller data\r | |
101 | //\r | |
102 | NVME_ADMIN_CONTROLLER_DATA *ControllerData;\r | |
103 | \r | |
104 | //\r | |
105 | // (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer\r | |
106 | // 1st 4kB boundary is the start of the admin submission queue\r | |
107 | // 2nd 4kB boundary is the start of the admin completion queue\r | |
108 | // 3rd 4kB boundary is the start of I/O submission queue\r | |
109 | // 4th 4kB boundary is the start of I/O completion queue\r | |
110 | // 5th 4kB boundary is the start of PRP list buffers\r | |
111 | //\r | |
112 | VOID *Buffer;\r | |
113 | VOID *BufferMapping;\r | |
114 | \r | |
115 | //\r | |
116 | // Pointers to 4kB aligned submission & completion queues\r | |
117 | //\r | |
118 | NVME_SQ *SqBuffer[NVME_MAX_QUEUES];\r | |
119 | NVME_CQ *CqBuffer[NVME_MAX_QUEUES];\r | |
120 | \r | |
121 | //\r | |
122 | // Submission and completion queue indices\r | |
123 | //\r | |
124 | NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];\r | |
125 | NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];\r | |
126 | \r | |
127 | UINT8 Pt[NVME_MAX_QUEUES];\r | |
128 | UINT16 Cid[NVME_MAX_QUEUES];\r | |
129 | \r | |
130 | //\r | |
131 | // Nvme controller capabilities\r | |
132 | //\r | |
133 | NVME_CAP Cap;\r | |
134 | \r | |
135 | //\r | |
136 | // Namespaces information on the controller\r | |
137 | //\r | |
138 | UINT32 ActiveNamespaceNum;\r | |
139 | PEI_NVME_NAMESPACE_INFO *NamespaceInfo;\r | |
140 | };\r | |
141 | \r | |
142 | #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \\r | |
143 | CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r | |
144 | #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a) \\r | |
145 | CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r | |
146 | #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \\r | |
147 | CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r | |
148 | \r | |
149 | \r | |
150 | /**\r | |
151 | Initialize IOMMU.\r | |
152 | **/\r | |
153 | VOID\r | |
154 | IoMmuInit (\r | |
155 | VOID\r | |
156 | );\r | |
157 | \r | |
158 | /**\r | |
159 | Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r | |
160 | OperationBusMasterCommonBuffer64 mapping.\r | |
161 | \r | |
162 | @param Pages The number of pages to allocate.\r | |
163 | @param HostAddress A pointer to store the base system memory address of the\r | |
164 | allocated range.\r | |
165 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
166 | access the hosts HostAddress.\r | |
167 | @param Mapping A resulting value to pass to Unmap().\r | |
168 | \r | |
169 | @retval EFI_SUCCESS The requested memory pages were allocated.\r | |
170 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r | |
171 | MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r | |
172 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
173 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r | |
174 | \r | |
175 | **/\r | |
176 | EFI_STATUS\r | |
177 | IoMmuAllocateBuffer (\r | |
178 | IN UINTN Pages,\r | |
179 | OUT VOID **HostAddress,\r | |
180 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
181 | OUT VOID **Mapping\r | |
182 | );\r | |
183 | \r | |
184 | /**\r | |
185 | Frees memory that was allocated with AllocateBuffer().\r | |
186 | \r | |
187 | @param Pages The number of pages to free.\r | |
188 | @param HostAddress The base system memory address of the allocated range.\r | |
189 | @param Mapping The mapping value returned from Map().\r | |
190 | \r | |
191 | @retval EFI_SUCCESS The requested memory pages were freed.\r | |
192 | @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r | |
193 | was not allocated with AllocateBuffer().\r | |
194 | \r | |
195 | **/\r | |
196 | EFI_STATUS\r | |
197 | IoMmuFreeBuffer (\r | |
198 | IN UINTN Pages,\r | |
199 | IN VOID *HostAddress,\r | |
200 | IN VOID *Mapping\r | |
201 | );\r | |
202 | \r | |
203 | /**\r | |
204 | Provides the controller-specific addresses required to access system memory from a\r | |
205 | DMA bus master.\r | |
206 | \r | |
207 | @param Operation Indicates if the bus master is going to read or write to system memory.\r | |
208 | @param HostAddress The system memory address to map to the PCI controller.\r | |
209 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r | |
210 | that were mapped.\r | |
211 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
212 | access the hosts HostAddress.\r | |
213 | @param Mapping A resulting value to pass to Unmap().\r | |
214 | \r | |
215 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r | |
216 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r | |
217 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
218 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
219 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r | |
220 | \r | |
221 | **/\r | |
222 | EFI_STATUS\r | |
223 | IoMmuMap (\r | |
224 | IN EDKII_IOMMU_OPERATION Operation,\r | |
225 | IN VOID *HostAddress,\r | |
226 | IN OUT UINTN *NumberOfBytes,\r | |
227 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
228 | OUT VOID **Mapping\r | |
229 | );\r | |
230 | \r | |
231 | /**\r | |
232 | Completes the Map() operation and releases any corresponding resources.\r | |
233 | \r | |
234 | @param Mapping The mapping value returned from Map().\r | |
235 | \r | |
236 | @retval EFI_SUCCESS The range was unmapped.\r | |
237 | @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r | |
238 | @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r | |
239 | **/\r | |
240 | EFI_STATUS\r | |
241 | IoMmuUnmap (\r | |
242 | IN VOID *Mapping\r | |
243 | );\r | |
244 | \r | |
245 | /**\r | |
246 | One notified function to cleanup the allocated resources at the end of PEI.\r | |
247 | \r | |
248 | @param[in] PeiServices Pointer to PEI Services Table.\r | |
249 | @param[in] NotifyDescriptor Pointer to the descriptor for the Notification\r | |
250 | event that caused this function to execute.\r | |
251 | @param[in] Ppi Pointer to the PPI data associated with this function.\r | |
252 | \r | |
253 | @retval EFI_SUCCESS The function completes successfully\r | |
254 | \r | |
255 | **/\r | |
256 | EFI_STATUS\r | |
257 | EFIAPI\r | |
258 | NvmePeimEndOfPei (\r | |
259 | IN EFI_PEI_SERVICES **PeiServices,\r | |
260 | IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r | |
261 | IN VOID *Ppi\r | |
262 | );\r | |
263 | \r | |
264 | #endif\r |