[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h

/** @file\r
\r
  This file contains the register definition of XHCI host controller.\r
\r
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_XHCI_REG_H_\r
#define _EFI_XHCI_REG_H_\r
\r
#define PCI_IF_XHCI                 0x30\r
\r
//\r
// PCI Configuration Registers\r
//\r
#define XHC_BAR_INDEX               0x00\r
\r
#define XHC_PCI_BAR_OFFSET          0x10       // Memory Bar Register Offset\r
#define XHC_PCI_BAR_MASK            0xFFFF     // Memory Base Address Mask\r
\r
#define XHC_PCI_SBRN_OFFSET         0x60       // Serial Bus Release Number Register Offset\r
\r
#define USB_HUB_CLASS_CODE          0x09\r
#define USB_HUB_SUBCLASS_CODE       0x00\r
\r
#define XHC_CAP_USB_LEGACY          0x01\r
#define XHC_CAP_USB_DEBUG           0x0A\r
\r
//============================================//\r
//           XHCI register offset             //\r
//============================================//\r
\r
//\r
// Capability registers offset\r
//\r
#define XHC_CAPLENGTH_OFFSET               0x00 // Capability register length offset\r
#define XHC_HCIVERSION_OFFSET              0x02 // Interface Version Number 02-03h\r
#define XHC_HCSPARAMS1_OFFSET              0x04 // Structural Parameters 1\r
#define XHC_HCSPARAMS2_OFFSET              0x08 // Structural Parameters 2\r
#define XHC_HCSPARAMS3_OFFSET              0x0c // Structural Parameters 3\r
#define XHC_HCCPARAMS_OFFSET               0x10 // Capability Parameters\r
#define XHC_DBOFF_OFFSET                   0x14 // Doorbell Offset\r
#define XHC_RTSOFF_OFFSET                  0x18 // Runtime Register Space Offset\r
\r
//\r
// Operational registers offset\r
//\r
#define XHC_USBCMD_OFFSET                  0x0000 // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET                  0x0004 // USB Status Register Offset\r
#define XHC_PAGESIZE_OFFSET                0x0008 // USB Page Size Register Offset\r
#define XHC_DNCTRL_OFFSET                  0x0014 // Device Notification Control Register Offset\r
#define XHC_CRCR_OFFSET                    0x0018 // Command Ring Control Register Offset\r
#define XHC_DCBAAP_OFFSET                  0x0030 // Device Context Base Address Array Pointer Register Offset\r
#define XHC_CONFIG_OFFSET                  0x0038 // Configure Register Offset\r
#define XHC_PORTSC_OFFSET                  0x0400 // Port Status and Control Register Offset\r
\r
//\r
// Runtime registers offset\r
//\r
#define XHC_MFINDEX_OFFSET                 0x00 // Microframe Index Register Offset\r
#define XHC_IMAN_OFFSET                    0x20 // Interrupter X Management Register Offset\r
#define XHC_IMOD_OFFSET                    0x24 // Interrupter X Moderation Register Offset\r
#define XHC_ERSTSZ_OFFSET                  0x28 // Event Ring Segment Table Size Register Offset\r
#define XHC_ERSTBA_OFFSET                  0x30 // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET                    0x38 // Event Ring Dequeue Pointer Register Offset\r
\r
//\r
// Debug registers offset\r
//\r
#define XHC_DC_DCCTRL                      0x20\r
\r
#define USBLEGSP_BIOS_SEMAPHORE            BIT16 // HC BIOS Owned Semaphore\r
#define USBLEGSP_OS_SEMAPHORE              BIT24 // HC OS Owned Semaphore\r
\r
#pragma pack (1)\r
typedef struct {\r
  UINT8                   MaxSlots;       // Number of Device Slots\r
  UINT16                  MaxIntrs:11;    // Number of Interrupters\r
  UINT16                  Rsvd:5;\r
  UINT8                   MaxPorts;       // Number of Ports\r
} HCSPARAMS1;\r
\r
//\r
// Structural Parameters 1 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCSPARAMS1              Data;\r
} XHC_HCSPARAMS1;\r
\r
typedef struct {\r
  UINT32                  Ist:4;          // Isochronous Scheduling Threshold\r
  UINT32                  Erst:4;         // Event Ring Segment Table Max\r
  UINT32                  Rsvd:13;\r
  UINT32                  ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
  UINT32                  Spr:1;          // Scratchpad Restore\r
  UINT32                  ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
} HCSPARAMS2;\r
\r
//\r
// Structural Parameters 2 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCSPARAMS2              Data;\r
} XHC_HCSPARAMS2;\r
\r
typedef struct {\r
  UINT16                  Ac64:1;        // 64-bit Addressing Capability\r
  UINT16                  Bnc:1;         // BW Negotiation Capability\r
  UINT16                  Csz:1;         // Context Size\r
  UINT16                  Ppc:1;         // Port Power Control\r
  UINT16                  Pind:1;        // Port Indicators\r
  UINT16                  Lhrc:1;        // Light HC Reset Capability\r
  UINT16                  Ltc:1;         // Latency Tolerance Messaging Capability\r
  UINT16                  Nss:1;         // No Secondary SID Support\r
  UINT16                  Pae:1;         // Parse All Event Data\r
  UINT16                  Rsvd:3;\r
  UINT16                  MaxPsaSize:4;  // Maximum Primary Stream Array Size\r
  UINT16                  ExtCapReg;     // xHCI Extended Capabilities Pointer\r
} HCCPARAMS;\r
\r
//\r
// Capability Parameters Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCCPARAMS               Data;\r
} XHC_HCCPARAMS;\r
\r
#pragma pack ()\r
\r
//\r
// Register Bit Definition\r
//\r
#define XHC_USBCMD_RUN                     BIT0  // Run/Stop\r
#define XHC_USBCMD_RESET                   BIT1  // Host Controller Reset\r
#define XHC_USBCMD_INTE                    BIT2  // Interrupter Enable\r
#define XHC_USBCMD_HSEE                    BIT3  // Host System Error Enable\r
\r
#define XHC_USBSTS_HALT                    BIT0  // Host Controller Halted\r
#define XHC_USBSTS_HSE                     BIT2  // Host System Error\r
#define XHC_USBSTS_EINT                    BIT3  // Event Interrupt\r
#define XHC_USBSTS_PCD                     BIT4  // Port Change Detect\r
#define XHC_USBSTS_SSS                     BIT8  // Save State Status\r
#define XHC_USBSTS_RSS                     BIT9  // Restore State Status\r
#define XHC_USBSTS_SRE                     BIT10 // Save/Restore Error\r
#define XHC_USBSTS_CNR                     BIT11 // Host Controller Not Ready\r
#define XHC_USBSTS_HCE                     BIT12 // Host Controller Error\r
\r
#define XHC_PAGESIZE_MASK                  0xFFFF // Page Size\r
\r
#define XHC_CRCR_RCS                       BIT0  // Ring Cycle State\r
#define XHC_CRCR_CS                        BIT1  // Command Stop\r
#define XHC_CRCR_CA                        BIT2  // Command Abort\r
#define XHC_CRCR_CRR                       BIT3  // Command Ring Running\r
\r
#define XHC_CONFIG_MASK                    0xFF  // Command Ring Running\r
\r
#define XHC_PORTSC_CCS                     BIT0  // Current Connect Status\r
#define XHC_PORTSC_PED                     BIT1  // Port Enabled/Disabled\r
#define XHC_PORTSC_OCA                     BIT3  // Over-current Active\r
#define XHC_PORTSC_RESET                   BIT4  // Port Reset\r
#define XHC_PORTSC_PLS                     (BIT5|BIT6|BIT7|BIT8)     // Port Link State\r
#define XHC_PORTSC_PP                      BIT9  // Port Power\r
#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
#define XHC_PORTSC_LWS                     BIT16 // Port Link State Write Strobe\r
#define XHC_PORTSC_CSC                     BIT17 // Connect Status Change\r
#define XHC_PORTSC_PEC                     BIT18 // Port Enabled/Disabled Change\r
#define XHC_PORTSC_WRC                     BIT19 // Warm Port Reset Change\r
#define XHC_PORTSC_OCC                     BIT20 // Over-Current Change\r
#define XHC_PORTSC_PRC                     BIT21 // Port Reset Change\r
#define XHC_PORTSC_PLC                     BIT22 // Port Link State Change\r
#define XHC_PORTSC_CEC                     BIT23 // Port Config Error Change\r
#define XHC_PORTSC_CAS                     BIT24 // Cold Attach Status\r
\r
#define XHC_HUB_PORTSC_CCS                 BIT0  // Hub's Current Connect Status\r
#define XHC_HUB_PORTSC_PED                 BIT1  // Hub's Port Enabled/Disabled\r
#define XHC_HUB_PORTSC_OCA                 BIT3  // Hub's Over-current Active\r
#define XHC_HUB_PORTSC_RESET               BIT4  // Hub's Port Reset\r
#define XHC_HUB_PORTSC_PP                  BIT9  // Hub's Port Power\r
#define XHC_HUB_PORTSC_CSC                 BIT16 // Hub's Connect Status Change\r
#define XHC_HUB_PORTSC_PEC                 BIT17 // Hub's Port Enabled/Disabled Change\r
#define XHC_HUB_PORTSC_OCC                 BIT19 // Hub's Over-Current Change\r
#define XHC_HUB_PORTSC_PRC                 BIT20 // Hub's Port Reset Change\r
#define XHC_HUB_PORTSC_BHRC                BIT21 // Hub's Port Warm Reset Change\r
#define XHC_IMAN_IP                        BIT0  // Interrupt Pending\r
#define XHC_IMAN_IE                        BIT1  // Interrupt Enable\r
\r
#define XHC_IMODI_MASK                     0x0000FFFF  // Interrupt Moderation Interval\r
#define XHC_IMODC_MASK                     0xFFFF0000  // Interrupt Moderation Counter\r
\r
//\r
//  Hub Class Feature Selector for Clear Port Feature Request\r
//  It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
//  For more details, Please refer to USB 3.0 Spec Table 10-7.\r
//\r
typedef enum {\r
  Usb3PortBHPortReset          = 28,\r
  Usb3PortBHPortResetChange    = 29\r
} XHC_PORT_FEATURE;\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Structure to map the hardware port states to feature selector for clear port feature request.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  Selector;\r
} USB_CLEAR_PORT_MAP;\r
\r
/**\r
  Read 1-byte width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 1-byte width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFF.\r
\r
**/\r
UINT8\r
XhcReadCapReg8 (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadCapReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI Operational register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width operational register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadOpReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the 4-bytes width XHCI operational register.\r
\r
  @param  Xhc      The XHCI Instance.\r
  @param  Offset   The offset of the 4-bytes width operational register.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the door bell register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteDoorBellReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcClearOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to be set (or clear).\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit of the register to wait for.\r
  @param  WaitToSet    Wait the bit to set or clear.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT  The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcWaitOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit,\r
  IN BOOLEAN              WaitToSet,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcClearRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Read XHCI extended capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the extended capability register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadExtCapReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Whether the XHCI host controller is halted.\r
\r
  @param  Xhc     The XHCI Instance.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcIsHalt (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  );\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Xhc      The XHCI Instance.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
XhcIsSysError (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  );\r
\r
/**\r
  Reset the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The XHCI host controller is reset.\r
  @return Others       Failed to reset the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcResetHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Halt the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is halt.\r
  @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcHaltHC (\r
  IN USB_XHCI_INSTANCE   *Xhc,\r
  IN UINT32              Timeout\r
  );\r
\r
/**\r
  Set the XHCI host controller to run.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is running.\r
  @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcRunHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Calculate the offset of the XHCI capability.\r
\r
  @param  Xhc     The XHCI Instance.\r
  @param  CapId   The XHCI Capability ID.\r
\r
  @return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
XhcGetCapabilityAddr (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT8                CapId\r
  );\r
\r
#endif\r
Commit	Line	Data
92870c98	1	/** @file\r
	2	\r
	3	This file contains the register definition of XHCI host controller.\r
	4	\r
4a723d3d	5	Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
9d510e61	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
92870c98	7	\r
	8	**/\r
	9	\r
	10	#ifndef _EFI_XHCI_REG_H_\r
	11	#define _EFI_XHCI_REG_H_\r
	12	\r
	13	#define PCI_IF_XHCI 0x30\r
	14	\r
	15	//\r
	16	// PCI Configuration Registers\r
	17	//\r
	18	#define XHC_BAR_INDEX 0x00\r
	19	\r
	20	#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r
	21	#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r
	22	\r
fed6cf25 SZ	23	#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset\r
fed6cf25 SZ	24	\r
92870c98	25	#define USB_HUB_CLASS_CODE 0x09\r
	26	#define USB_HUB_SUBCLASS_CODE 0x00\r
	27	\r
5bcb62a4 EL	28	#define XHC_CAP_USB_LEGACY 0x01\r
	29	#define XHC_CAP_USB_DEBUG 0x0A\r
	30	\r
92870c98	31	//============================================//\r
	32	// XHCI register offset //\r
	33	//============================================//\r
	34	\r
	35	//\r
	36	// Capability registers offset\r
	37	//\r
	38	#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
	39	#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
	40	#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
	41	#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
	42	#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
	43	#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
	44	#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
	45	#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
	46	\r
	47	//\r
	48	// Operational registers offset\r
	49	//\r
	50	#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
	51	#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
	52	#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
	53	#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
	54	#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
	55	#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
	56	#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
	57	#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
	58	\r
	59	//\r
	60	// Runtime registers offset\r
	61	//\r
	62	#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
	63	#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
	64	#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
	65	#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
	66	#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
	67	#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
	68	\r
5bcb62a4 EL	69	//\r
	70	// Debug registers offset\r
	71	//\r
	72	#define XHC_DC_DCCTRL 0x20\r
	73	\r
92870c98	74	#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
	75	#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
	76	\r
	77	#pragma pack (1)\r
a9292c13	78	typedef struct {\r
	79	UINT8 MaxSlots; // Number of Device Slots\r
	80	UINT16 MaxIntrs:11; // Number of Interrupters\r
	81	UINT16 Rsvd:5;\r
	82	UINT8 MaxPorts; // Number of Ports\r
	83	} HCSPARAMS1;\r
	84	\r
92870c98	85	//\r
	86	// Structural Parameters 1 Register Bitmap Definition\r
	87	//\r
a9292c13	88	typedef union {\r
	89	UINT32 Dword;\r
	90	HCSPARAMS1 Data;\r
92870c98	91	} XHC_HCSPARAMS1;\r
92870c98	92	\r
a9292c13	93	typedef struct {\r
	94	UINT32 Ist:4; // Isochronous Scheduling Threshold\r
	95	UINT32 Erst:4; // Event Ring Segment Table Max\r
	96	UINT32 Rsvd:13;\r
	97	UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
	98	UINT32 Spr:1; // Scratchpad Restore\r
	99	UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
	100	} HCSPARAMS2;\r
	101	\r
92870c98	102	//\r
	103	// Structural Parameters 2 Register Bitmap Definition\r
	104	//\r
a9292c13	105	typedef union {\r
	106	UINT32 Dword;\r
	107	HCSPARAMS2 Data;\r
92870c98	108	} XHC_HCSPARAMS2;\r
92870c98	109	\r
a9292c13	110	typedef struct {\r
	111	UINT16 Ac64:1; // 64-bit Addressing Capability\r
	112	UINT16 Bnc:1; // BW Negotiation Capability\r
	113	UINT16 Csz:1; // Context Size\r
	114	UINT16 Ppc:1; // Port Power Control\r
	115	UINT16 Pind:1; // Port Indicators\r
	116	UINT16 Lhrc:1; // Light HC Reset Capability\r
	117	UINT16 Ltc:1; // Latency Tolerance Messaging Capability\r
	118	UINT16 Nss:1; // No Secondary SID Support\r
	119	UINT16 Pae:1; // Parse All Event Data\r
	120	UINT16 Rsvd:3;\r
	121	UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size\r
	122	UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
	123	} HCCPARAMS;\r
	124	\r
92870c98	125	//\r
	126	// Capability Parameters Register Bitmap Definition\r
	127	//\r
a9292c13	128	typedef union {\r
	129	UINT32 Dword;\r
	130	HCCPARAMS Data;\r
92870c98	131	} XHC_HCCPARAMS;\r
	132	\r
	133	#pragma pack ()\r
	134	\r
	135	//\r
	136	// Register Bit Definition\r
	137	//\r
	138	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	139	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	140	#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
	141	#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
	142	\r
	143	#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
	144	#define XHC_USBSTS_HSE BIT2 // Host System Error\r
	145	#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
	146	#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
	147	#define XHC_USBSTS_SSS BIT8 // Save State Status\r
	148	#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
	149	#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
	150	#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
	151	#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
	152	\r
	153	#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
	154	\r
	155	#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
	156	#define XHC_CRCR_CS BIT1 // Command Stop\r
	157	#define XHC_CRCR_CA BIT2 // Command Abort\r
	158	#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
	159	\r
	160	#define XHC_CONFIG_MASK 0xFF // Command Ring Running\r
	161	\r
	162	#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
	163	#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
	164	#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
	165	#define XHC_PORTSC_RESET BIT4 // Port Reset\r
	166	#define XHC_PORTSC_PLS (BIT5\|BIT6\|BIT7\|BIT8) // Port Link State\r
	167	#define XHC_PORTSC_PP BIT9 // Port Power\r
4a723d3d	168	#define XHC_PORTSC_PS (BIT10\|BIT11\|BIT12\|BIT13) // Port Speed\r
92870c98	169	#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
	170	#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
	171	#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
	172	#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
	173	#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
	174	#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
	175	#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
	176	#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
	177	#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
	178	\r
a50f7c4c	179	#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
	180	#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
	181	#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
	182	#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
	183	#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
	184	#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
	185	#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
	186	#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
	187	#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
c3f44a77	188	#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
92870c98	189	#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
	190	#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
	191	\r
	192	#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
	193	#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
	194	\r
c3f44a77 FT	195	//\r
c3f44a77 FT	196	// Hub Class Feature Selector for Clear Port Feature Request\r
8d84dbe9 FT	197	// It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
8d84dbe9 FT	198	// For more details, Please refer to USB 3.0 Spec Table 10-7.\r
c3f44a77	199	//\r
8d84dbe9 FT	200	typedef enum {\r
	201	Usb3PortBHPortReset = 28,\r
	202	Usb3PortBHPortResetChange = 29\r
	203	} XHC_PORT_FEATURE;\r
c3f44a77	204	\r
92870c98	205	//\r
	206	// Structure to map the hardware port states to the\r
	207	// UEFI's port states.\r
	208	//\r
	209	typedef struct {\r
	210	UINT32 HwState;\r
	211	UINT16 UefiState;\r
	212	} USB_PORT_STATE_MAP;\r
	213	\r
c3f44a77 FT	214	//\r
	215	// Structure to map the hardware port states to feature selector for clear port feature request.\r
	216	//\r
	217	typedef struct {\r
	218	UINT32 HwState;\r
	219	UINT16 Selector;\r
	220	} USB_CLEAR_PORT_MAP;\r
	221	\r
92870c98	222	/**\r
	223	Read 1-byte width XHCI capability register.\r
	224	\r
a9292c13	225	@param Xhc The XHCI Instance.\r
92870c98	226	@param Offset The offset of the 1-byte width capability register.\r
	227	\r
	228	@return The register content read.\r
	229	@retval If err, return 0xFFFF.\r
	230	\r
	231	**/\r
	232	UINT8\r
	233	XhcReadCapReg8 (\r
a9292c13	234	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	235	IN UINT32 Offset\r
	236	);\r
	237	\r
	238	/**\r
	239	Read 4-bytes width XHCI capability register.\r
	240	\r
a9292c13	241	@param Xhc The XHCI Instance.\r
92870c98	242	@param Offset The offset of the 4-bytes width capability register.\r
	243	\r
	244	@return The register content read.\r
	245	@retval If err, return 0xFFFFFFFF.\r
	246	\r
	247	**/\r
	248	UINT32\r
	249	XhcReadCapReg (\r
a9292c13	250	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	251	IN UINT32 Offset\r
	252	);\r
	253	\r
	254	/**\r
	255	Read 4-bytes width XHCI Operational register.\r
	256	\r
a9292c13	257	@param Xhc The XHCI Instance.\r
92870c98	258	@param Offset The offset of the 4-bytes width operational register.\r
	259	\r
	260	@return The register content read.\r
	261	@retval If err, return 0xFFFFFFFF.\r
	262	\r
	263	**/\r
	264	UINT32\r
	265	XhcReadOpReg (\r
a9292c13	266	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	267	IN UINT32 Offset\r
	268	);\r
	269	\r
	270	/**\r
	271	Write the data to the 4-bytes width XHCI operational register.\r
	272	\r
a9292c13	273	@param Xhc The XHCI Instance.\r
92870c98	274	@param Offset The offset of the 4-bytes width operational register.\r
	275	@param Data The data to write.\r
	276	\r
	277	**/\r
	278	VOID\r
	279	XhcWriteOpReg (\r
a9292c13	280	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	281	IN UINT32 Offset,\r
	282	IN UINT32 Data\r
	283	);\r
	284	\r
92870c98	285	\r
92870c98	286	/**\r
	287	Read XHCI runtime register.\r
	288	\r
a9292c13	289	@param Xhc The XHCI Instance.\r
92870c98	290	@param Offset The offset of the runtime register.\r
	291	\r
	292	@return The register content read\r
	293	\r
	294	**/\r
	295	UINT32\r
	296	XhcReadRuntimeReg (\r
a9292c13	297	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	298	IN UINT32 Offset\r
	299	);\r
	300	\r
92870c98	301	/**\r
	302	Write the data to the XHCI runtime register.\r
	303	\r
a9292c13	304	@param Xhc The XHCI Instance.\r
92870c98	305	@param Offset The offset of the runtime register.\r
	306	@param Data The data to write.\r
	307	\r
	308	**/\r
	309	VOID\r
	310	XhcWriteRuntimeReg (\r
a9292c13	311	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	312	IN UINT32 Offset,\r
	313	IN UINT32 Data\r
	314	);\r
	315	\r
92870c98	316	\r
	317	/**\r
	318	Write the data to the XHCI door bell register.\r
	319	\r
a9292c13	320	@param Xhc The XHCI Instance.\r
92870c98	321	@param Offset The offset of the door bell register.\r
	322	@param Data The data to write.\r
	323	\r
	324	**/\r
	325	VOID\r
	326	XhcWriteDoorBellReg (\r
a9292c13	327	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	328	IN UINT32 Offset,\r
	329	IN UINT32 Data\r
	330	);\r
	331	\r
	332	/**\r
	333	Set one bit of the operational register while keeping other bits.\r
	334	\r
a9292c13	335	@param Xhc The XHCI Instance.\r
92870c98	336	@param Offset The offset of the operational register.\r
	337	@param Bit The bit mask of the register to set.\r
	338	\r
	339	**/\r
	340	VOID\r
	341	XhcSetOpRegBit (\r
a9292c13	342	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	343	IN UINT32 Offset,\r
	344	IN UINT32 Bit\r
	345	);\r
	346	\r
	347	/**\r
	348	Clear one bit of the operational register while keeping other bits.\r
	349	\r
a9292c13	350	@param Xhc The XHCI Instance.\r
92870c98	351	@param Offset The offset of the operational register.\r
	352	@param Bit The bit mask of the register to clear.\r
	353	\r
	354	**/\r
	355	VOID\r
	356	XhcClearOpRegBit (\r
a9292c13	357	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	358	IN UINT32 Offset,\r
	359	IN UINT32 Bit\r
	360	);\r
	361	\r
	362	/**\r
	363	Wait the operation register's bit as specified by Bit\r
	364	to be set (or clear).\r
	365	\r
a9292c13	366	@param Xhc The XHCI Instance.\r
92870c98	367	@param Offset The offset of the operational register.\r
	368	@param Bit The bit of the register to wait for.\r
	369	@param WaitToSet Wait the bit to set or clear.\r
2f6ef874	370	@param Timeout The time to wait before abort (in millisecond, ms).\r
92870c98	371	\r
	372	@retval EFI_SUCCESS The bit successfully changed by host controller.\r
	373	@retval EFI_TIMEOUT The time out occurred.\r
	374	\r
	375	**/\r
	376	EFI_STATUS\r
	377	XhcWaitOpRegBit (\r
a9292c13	378	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	379	IN UINT32 Offset,\r
	380	IN UINT32 Bit,\r
	381	IN BOOLEAN WaitToSet,\r
	382	IN UINT32 Timeout\r
	383	);\r
	384	\r
	385	/**\r
	386	Read XHCI runtime register.\r
	387	\r
a9292c13	388	@param Xhc The XHCI Instance.\r
92870c98	389	@param Offset The offset of the runtime register.\r
	390	\r
	391	@return The register content read\r
	392	\r
	393	**/\r
	394	UINT32\r
	395	XhcReadRuntimeReg (\r
a9292c13	396	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	397	IN UINT32 Offset\r
	398	);\r
	399	\r
	400	/**\r
	401	Write the data to the XHCI runtime register.\r
	402	\r
a9292c13	403	@param Xhc The XHCI Instance.\r
92870c98	404	@param Offset The offset of the runtime register.\r
	405	@param Data The data to write.\r
	406	\r
	407	**/\r
	408	VOID\r
	409	XhcWriteRuntimeReg (\r
a9292c13	410	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	411	IN UINT32 Offset,\r
	412	IN UINT32 Data\r
	413	);\r
	414	\r
	415	/**\r
	416	Set one bit of the runtime register while keeping other bits.\r
	417	\r
a9292c13	418	@param Xhc The XHCI Instance.\r
92870c98	419	@param Offset The offset of the runtime register.\r
	420	@param Bit The bit mask of the register to set.\r
	421	\r
	422	**/\r
	423	VOID\r
	424	XhcSetRuntimeRegBit (\r
a9292c13	425	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	426	IN UINT32 Offset,\r
	427	IN UINT32 Bit\r
	428	);\r
	429	\r
	430	/**\r
	431	Clear one bit of the runtime register while keeping other bits.\r
	432	\r
a9292c13	433	@param Xhc The XHCI Instance.\r
92870c98	434	@param Offset The offset of the runtime register.\r
	435	@param Bit The bit mask of the register to set.\r
	436	\r
	437	**/\r
	438	VOID\r
	439	XhcClearRuntimeRegBit (\r
a9292c13	440	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	441	IN UINT32 Offset,\r
	442	IN UINT32 Bit\r
	443	);\r
	444	\r
5bcb62a4 EL	445	/**\r
	446	Read XHCI extended capability register.\r
	447	\r
	448	@param Xhc The XHCI Instance.\r
	449	@param Offset The offset of the extended capability register.\r
	450	\r
	451	@return The register content read\r
	452	\r
	453	**/\r
	454	UINT32\r
	455	XhcReadExtCapReg (\r
	456	IN USB_XHCI_INSTANCE *Xhc,\r
	457	IN UINT32 Offset\r
	458	);\r
	459	\r
92870c98	460	/**\r
	461	Whether the XHCI host controller is halted.\r
	462	\r
a9292c13	463	@param Xhc The XHCI Instance.\r
92870c98	464	\r
	465	@retval TRUE The controller is halted.\r
	466	@retval FALSE It isn't halted.\r
	467	\r
	468	**/\r
	469	BOOLEAN\r
	470	XhcIsHalt (\r
a9292c13	471	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	472	);\r
	473	\r
	474	/**\r
	475	Whether system error occurred.\r
	476	\r
a9292c13	477	@param Xhc The XHCI Instance.\r
92870c98	478	\r
	479	@retval TRUE System error happened.\r
	480	@retval FALSE No system error.\r
	481	\r
	482	**/\r
	483	BOOLEAN\r
	484	XhcIsSysError (\r
a9292c13	485	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	486	);\r
	487	\r
	488	/**\r
	489	Reset the XHCI host controller.\r
	490	\r
a9292c13	491	@param Xhc The XHCI Instance.\r
2f6ef874	492	@param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98	493	\r
	494	@retval EFI_SUCCESS The XHCI host controller is reset.\r
	495	@return Others Failed to reset the XHCI before Timeout.\r
	496	\r
	497	**/\r
	498	EFI_STATUS\r
	499	XhcResetHC (\r
a9292c13	500	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	501	IN UINT32 Timeout\r
	502	);\r
	503	\r
	504	/**\r
	505	Halt the XHCI host controller.\r
	506	\r
a9292c13	507	@param Xhc The XHCI Instance.\r
2f6ef874	508	@param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98	509	\r
	510	@return EFI_SUCCESS The XHCI host controller is halt.\r
	511	@return EFI_TIMEOUT Failed to halt the XHCI before Timeout.\r
	512	\r
	513	**/\r
	514	EFI_STATUS\r
	515	XhcHaltHC (\r
a9292c13	516	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	517	IN UINT32 Timeout\r
	518	);\r
	519	\r
	520	/**\r
	521	Set the XHCI host controller to run.\r
	522	\r
a9292c13	523	@param Xhc The XHCI Instance.\r
2f6ef874	524	@param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98	525	\r
	526	@return EFI_SUCCESS The XHCI host controller is running.\r
	527	@return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.\r
	528	\r
	529	**/\r
	530	EFI_STATUS\r
	531	XhcRunHC (\r
a9292c13	532	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	533	IN UINT32 Timeout\r
	534	);\r
	535	\r
	536	/**\r
5bcb62a4	537	Calculate the offset of the XHCI capability.\r
92870c98	538	\r
a9292c13	539	@param Xhc The XHCI Instance.\r
5bcb62a4	540	@param CapId The XHCI Capability ID.\r
92870c98	541	\r
	542	@return The offset of XHCI legacy support capability register.\r
	543	\r
	544	**/\r
	545	UINT32\r
5bcb62a4 EL	546	XhcGetCapabilityAddr (\r
	547	IN USB_XHCI_INSTANCE *Xhc,\r
	548	IN UINT8 CapId\r
92870c98	549	);\r
	550	\r
	551	#endif\r