[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h

/** @file\r
\r
  This file contains the register definition of XHCI host controller.\r
\r
Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_XHCI_REG_H_\r
#define _EFI_XHCI_REG_H_\r
\r
#define PCI_IF_XHCI                 0x30\r
\r
//\r
// PCI Configuration Registers\r
//\r
#define XHC_BAR_INDEX               0x00\r
\r
#define XHC_PCI_BAR_OFFSET          0x10       // Memory Bar Register Offset\r
#define XHC_PCI_BAR_MASK            0xFFFF     // Memory Base Address Mask\r
\r
#define USB_HUB_CLASS_CODE          0x09\r
#define USB_HUB_SUBCLASS_CODE       0x00\r
\r
#define XHC_CAP_USB_LEGACY          0x01\r
#define XHC_CAP_USB_DEBUG           0x0A\r
\r
//============================================//\r
//           XHCI register offset             //\r
//============================================//\r
\r
//\r
// Capability registers offset\r
//\r
#define XHC_CAPLENGTH_OFFSET               0x00 // Capability register length offset\r
#define XHC_HCIVERSION_OFFSET              0x02 // Interface Version Number 02-03h\r
#define XHC_HCSPARAMS1_OFFSET              0x04 // Structural Parameters 1\r
#define XHC_HCSPARAMS2_OFFSET              0x08 // Structural Parameters 2\r
#define XHC_HCSPARAMS3_OFFSET              0x0c // Structural Parameters 3\r
#define XHC_HCCPARAMS_OFFSET               0x10 // Capability Parameters\r
#define XHC_DBOFF_OFFSET                   0x14 // Doorbell Offset\r
#define XHC_RTSOFF_OFFSET                  0x18 // Runtime Register Space Offset\r
\r
//\r
// Operational registers offset\r
//\r
#define XHC_USBCMD_OFFSET                  0x0000 // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET                  0x0004 // USB Status Register Offset\r
#define XHC_PAGESIZE_OFFSET                0x0008 // USB Page Size Register Offset\r
#define XHC_DNCTRL_OFFSET                  0x0014 // Device Notification Control Register Offset\r
#define XHC_CRCR_OFFSET                    0x0018 // Command Ring Control Register Offset\r
#define XHC_DCBAAP_OFFSET                  0x0030 // Device Context Base Address Array Pointer Register Offset\r
#define XHC_CONFIG_OFFSET                  0x0038 // Configure Register Offset\r
#define XHC_PORTSC_OFFSET                  0x0400 // Port Status and Control Register Offset\r
\r
//\r
// Runtime registers offset\r
//\r
#define XHC_MFINDEX_OFFSET                 0x00 // Microframe Index Register Offset\r
#define XHC_IMAN_OFFSET                    0x20 // Interrupter X Management Register Offset\r
#define XHC_IMOD_OFFSET                    0x24 // Interrupter X Moderation Register Offset\r
#define XHC_ERSTSZ_OFFSET                  0x28 // Event Ring Segment Table Size Register Offset\r
#define XHC_ERSTBA_OFFSET                  0x30 // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET                    0x38 // Event Ring Dequeue Pointer Register Offset\r
\r
//\r
// Debug registers offset\r
//\r
#define XHC_DC_DCCTRL                      0x20\r
\r
#define USBLEGSP_BIOS_SEMAPHORE            BIT16 // HC BIOS Owned Semaphore\r
#define USBLEGSP_OS_SEMAPHORE              BIT24 // HC OS Owned Semaphore\r
\r
#pragma pack (1)\r
typedef struct {\r
  UINT8                   MaxSlots;       // Number of Device Slots\r
  UINT16                  MaxIntrs:11;    // Number of Interrupters\r
  UINT16                  Rsvd:5;\r
  UINT8                   MaxPorts;       // Number of Ports\r
} HCSPARAMS1;\r
\r
//\r
// Structural Parameters 1 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCSPARAMS1              Data;\r
} XHC_HCSPARAMS1;\r
\r
typedef struct {\r
  UINT32                  Ist:4;          // Isochronous Scheduling Threshold\r
  UINT32                  Erst:4;         // Event Ring Segment Table Max\r
  UINT32                  Rsvd:13;\r
  UINT32                  ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
  UINT32                  Spr:1;          // Scratchpad Restore\r
  UINT32                  ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
} HCSPARAMS2;\r
\r
//\r
// Structural Parameters 2 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCSPARAMS2              Data;\r
} XHC_HCSPARAMS2;\r
\r
typedef struct {\r
  UINT16                  Ac64:1;        // 64-bit Addressing Capability\r
  UINT16                  Bnc:1;         // BW Negotiation Capability\r
  UINT16                  Csz:1;         // Context Size\r
  UINT16                  Ppc:1;         // Port Power Control\r
  UINT16                  Pind:1;        // Port Indicators\r
  UINT16                  Lhrc:1;        // Light HC Reset Capability\r
  UINT16                  Ltc:1;         // Latency Tolerance Messaging Capability\r
  UINT16                  Nss:1;         // No Secondary SID Support\r
  UINT16                  Pae:1;         // Parse All Event Data\r
  UINT16                  Rsvd:3;\r
  UINT16                  MaxPsaSize:4;  // Maximum Primary Stream Array Size\r
  UINT16                  ExtCapReg;     // xHCI Extended Capabilities Pointer\r
} HCCPARAMS;\r
\r
//\r
// Capability Parameters Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCCPARAMS               Data;\r
} XHC_HCCPARAMS;\r
\r
#pragma pack ()\r
\r
//\r
// Register Bit Definition\r
//\r
#define XHC_USBCMD_RUN                     BIT0  // Run/Stop\r
#define XHC_USBCMD_RESET                   BIT1  // Host Controller Reset\r
#define XHC_USBCMD_INTE                    BIT2  // Interrupter Enable\r
#define XHC_USBCMD_HSEE                    BIT3  // Host System Error Enable\r
\r
#define XHC_USBSTS_HALT                    BIT0  // Host Controller Halted\r
#define XHC_USBSTS_HSE                     BIT2  // Host System Error\r
#define XHC_USBSTS_EINT                    BIT3  // Event Interrupt\r
#define XHC_USBSTS_PCD                     BIT4  // Port Change Detect\r
#define XHC_USBSTS_SSS                     BIT8  // Save State Status\r
#define XHC_USBSTS_RSS                     BIT9  // Restore State Status\r
#define XHC_USBSTS_SRE                     BIT10 // Save/Restore Error\r
#define XHC_USBSTS_CNR                     BIT11 // Host Controller Not Ready\r
#define XHC_USBSTS_HCE                     BIT12 // Host Controller Error\r
\r
#define XHC_PAGESIZE_MASK                  0xFFFF // Page Size\r
\r
#define XHC_CRCR_RCS                       BIT0  // Ring Cycle State\r
#define XHC_CRCR_CS                        BIT1  // Command Stop\r
#define XHC_CRCR_CA                        BIT2  // Command Abort\r
#define XHC_CRCR_CRR                       BIT3  // Command Ring Running\r
\r
#define XHC_CONFIG_MASK                    0xFF  // Command Ring Running\r
\r
#define XHC_PORTSC_CCS                     BIT0  // Current Connect Status\r
#define XHC_PORTSC_PED                     BIT1  // Port Enabled/Disabled\r
#define XHC_PORTSC_OCA                     BIT3  // Over-current Active\r
#define XHC_PORTSC_RESET                   BIT4  // Port Reset\r
#define XHC_PORTSC_PLS                     (BIT5|BIT6|BIT7|BIT8)     // Port Link State\r
#define XHC_PORTSC_PP                      BIT9  // Port Power\r
#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
#define XHC_PORTSC_LWS                     BIT16 // Port Link State Write Strobe\r
#define XHC_PORTSC_CSC                     BIT17 // Connect Status Change\r
#define XHC_PORTSC_PEC                     BIT18 // Port Enabled/Disabled Change\r
#define XHC_PORTSC_WRC                     BIT19 // Warm Port Reset Change\r
#define XHC_PORTSC_OCC                     BIT20 // Over-Current Change\r
#define XHC_PORTSC_PRC                     BIT21 // Port Reset Change\r
#define XHC_PORTSC_PLC                     BIT22 // Port Link State Change\r
#define XHC_PORTSC_CEC                     BIT23 // Port Config Error Change\r
#define XHC_PORTSC_CAS                     BIT24 // Cold Attach Status\r
\r
#define XHC_HUB_PORTSC_CCS                 BIT0  // Hub's Current Connect Status\r
#define XHC_HUB_PORTSC_PED                 BIT1  // Hub's Port Enabled/Disabled\r
#define XHC_HUB_PORTSC_OCA                 BIT3  // Hub's Over-current Active\r
#define XHC_HUB_PORTSC_RESET               BIT4  // Hub's Port Reset\r
#define XHC_HUB_PORTSC_PP                  BIT9  // Hub's Port Power\r
#define XHC_HUB_PORTSC_CSC                 BIT16 // Hub's Connect Status Change\r
#define XHC_HUB_PORTSC_PEC                 BIT17 // Hub's Port Enabled/Disabled Change\r
#define XHC_HUB_PORTSC_OCC                 BIT19 // Hub's Over-Current Change\r
#define XHC_HUB_PORTSC_PRC                 BIT20 // Hub's Port Reset Change\r
#define XHC_IMAN_IP                        BIT0  // Interrupt Pending\r
#define XHC_IMAN_IE                        BIT1  // Interrupt Enable\r
\r
#define XHC_IMODI_MASK                     0x0000FFFF  // Interrupt Moderation Interval\r
#define XHC_IMODC_MASK                     0xFFFF0000  // Interrupt Moderation Counter\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
/**\r
  Read 1-byte width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 1-byte width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFF.\r
\r
**/\r
UINT8\r
XhcReadCapReg8 (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadCapReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI Operational register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width operational register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadOpReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the 4-bytes width XHCI operational register.\r
\r
  @param  Xhc      The XHCI Instance.\r
  @param  Offset   The offset of the 4-bytes width operational register.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Write the data to the 2-bytes width XHCI operational register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 2-bytes width operational register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg16 (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT16               Data\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Read XHCI door bell register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the door bell register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadDoorBellReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the door bell register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteDoorBellReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcClearOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to be set (or clear).\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit of the register to wait for.\r
  @param  WaitToSet    Wait the bit to set or clear.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT  The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcWaitOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit,\r
  IN BOOLEAN              WaitToSet,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcClearRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Read XHCI extended capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the extended capability register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadExtCapReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Whether the XHCI host controller is halted.\r
\r
  @param  Xhc     The XHCI Instance.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcIsHalt (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  );\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Xhc      The XHCI Instance.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
XhcIsSysError (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  );\r
\r
/**\r
  Reset the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The XHCI host controller is reset.\r
  @return Others       Failed to reset the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcResetHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Halt the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is halt.\r
  @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcHaltHC (\r
  IN USB_XHCI_INSTANCE   *Xhc,\r
  IN UINT32              Timeout\r
  );\r
\r
/**\r
  Set the XHCI host controller to run.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is running.\r
  @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcRunHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Calculate the offset of the XHCI capability.\r
\r
  @param  Xhc     The XHCI Instance.\r
  @param  CapId   The XHCI Capability ID.\r
\r
  @return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
XhcGetCapabilityAddr (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT8                CapId\r
  );\r
\r
#endif\r
Commit	Line	Data
92870c98	1	/** @file\r
	2	\r
	3	This file contains the register definition of XHCI host controller.\r
	4	\r
a50f7c4c	5	Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r
92870c98	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef _EFI_XHCI_REG_H_\r
	17	#define _EFI_XHCI_REG_H_\r
	18	\r
	19	#define PCI_IF_XHCI 0x30\r
	20	\r
	21	//\r
	22	// PCI Configuration Registers\r
	23	//\r
	24	#define XHC_BAR_INDEX 0x00\r
	25	\r
	26	#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r
	27	#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r
	28	\r
	29	#define USB_HUB_CLASS_CODE 0x09\r
	30	#define USB_HUB_SUBCLASS_CODE 0x00\r
	31	\r
5bcb62a4 EL	32	#define XHC_CAP_USB_LEGACY 0x01\r
	33	#define XHC_CAP_USB_DEBUG 0x0A\r
	34	\r
92870c98	35	//============================================//\r
	36	// XHCI register offset //\r
	37	//============================================//\r
	38	\r
	39	//\r
	40	// Capability registers offset\r
	41	//\r
	42	#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
	43	#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
	44	#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
	45	#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
	46	#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
	47	#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
	48	#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
	49	#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
	50	\r
	51	//\r
	52	// Operational registers offset\r
	53	//\r
	54	#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
	55	#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
	56	#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
	57	#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
	58	#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
	59	#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
	60	#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
	61	#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
	62	\r
	63	//\r
	64	// Runtime registers offset\r
	65	//\r
	66	#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
	67	#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
	68	#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
	69	#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
	70	#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
	71	#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
	72	\r
5bcb62a4 EL	73	//\r
	74	// Debug registers offset\r
	75	//\r
	76	#define XHC_DC_DCCTRL 0x20\r
	77	\r
92870c98	78	#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
	79	#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
	80	\r
	81	#pragma pack (1)\r
a9292c13	82	typedef struct {\r
	83	UINT8 MaxSlots; // Number of Device Slots\r
	84	UINT16 MaxIntrs:11; // Number of Interrupters\r
	85	UINT16 Rsvd:5;\r
	86	UINT8 MaxPorts; // Number of Ports\r
	87	} HCSPARAMS1;\r
	88	\r
92870c98	89	//\r
	90	// Structural Parameters 1 Register Bitmap Definition\r
	91	//\r
a9292c13	92	typedef union {\r
	93	UINT32 Dword;\r
	94	HCSPARAMS1 Data;\r
92870c98	95	} XHC_HCSPARAMS1;\r
92870c98	96	\r
a9292c13	97	typedef struct {\r
	98	UINT32 Ist:4; // Isochronous Scheduling Threshold\r
	99	UINT32 Erst:4; // Event Ring Segment Table Max\r
	100	UINT32 Rsvd:13;\r
	101	UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
	102	UINT32 Spr:1; // Scratchpad Restore\r
	103	UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
	104	} HCSPARAMS2;\r
	105	\r
92870c98	106	//\r
	107	// Structural Parameters 2 Register Bitmap Definition\r
	108	//\r
a9292c13	109	typedef union {\r
	110	UINT32 Dword;\r
	111	HCSPARAMS2 Data;\r
92870c98	112	} XHC_HCSPARAMS2;\r
92870c98	113	\r
a9292c13	114	typedef struct {\r
	115	UINT16 Ac64:1; // 64-bit Addressing Capability\r
	116	UINT16 Bnc:1; // BW Negotiation Capability\r
	117	UINT16 Csz:1; // Context Size\r
	118	UINT16 Ppc:1; // Port Power Control\r
	119	UINT16 Pind:1; // Port Indicators\r
	120	UINT16 Lhrc:1; // Light HC Reset Capability\r
	121	UINT16 Ltc:1; // Latency Tolerance Messaging Capability\r
	122	UINT16 Nss:1; // No Secondary SID Support\r
	123	UINT16 Pae:1; // Parse All Event Data\r
	124	UINT16 Rsvd:3;\r
	125	UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size\r
	126	UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
	127	} HCCPARAMS;\r
	128	\r
92870c98	129	//\r
	130	// Capability Parameters Register Bitmap Definition\r
	131	//\r
a9292c13	132	typedef union {\r
	133	UINT32 Dword;\r
	134	HCCPARAMS Data;\r
92870c98	135	} XHC_HCCPARAMS;\r
	136	\r
	137	#pragma pack ()\r
	138	\r
	139	//\r
	140	// Register Bit Definition\r
	141	//\r
	142	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	143	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	144	#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
	145	#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
	146	\r
	147	#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
	148	#define XHC_USBSTS_HSE BIT2 // Host System Error\r
	149	#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
	150	#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
	151	#define XHC_USBSTS_SSS BIT8 // Save State Status\r
	152	#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
	153	#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
	154	#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
	155	#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
	156	\r
	157	#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
	158	\r
	159	#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
	160	#define XHC_CRCR_CS BIT1 // Command Stop\r
	161	#define XHC_CRCR_CA BIT2 // Command Abort\r
	162	#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
	163	\r
	164	#define XHC_CONFIG_MASK 0xFF // Command Ring Running\r
	165	\r
	166	#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
	167	#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
	168	#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
	169	#define XHC_PORTSC_RESET BIT4 // Port Reset\r
	170	#define XHC_PORTSC_PLS (BIT5\|BIT6\|BIT7\|BIT8) // Port Link State\r
	171	#define XHC_PORTSC_PP BIT9 // Port Power\r
	172	#define XHC_PORTSC_PS (BIT10\|BIT11\|BIT12\|BIT13) // Port Speed\r
	173	#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
	174	#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
	175	#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
	176	#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
	177	#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
	178	#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
	179	#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
	180	#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
	181	#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
	182	\r
a50f7c4c	183	#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
	184	#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
	185	#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
	186	#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
	187	#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
	188	#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
	189	#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
	190	#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
	191	#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
92870c98	192	#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
	193	#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
	194	\r
	195	#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
	196	#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
	197	\r
	198	//\r
	199	// Structure to map the hardware port states to the\r
	200	// UEFI's port states.\r
	201	//\r
	202	typedef struct {\r
	203	UINT32 HwState;\r
	204	UINT16 UefiState;\r
	205	} USB_PORT_STATE_MAP;\r
	206	\r
	207	/**\r
	208	Read 1-byte width XHCI capability register.\r
	209	\r
a9292c13	210	@param Xhc The XHCI Instance.\r
92870c98	211	@param Offset The offset of the 1-byte width capability register.\r
	212	\r
	213	@return The register content read.\r
	214	@retval If err, return 0xFFFF.\r
	215	\r
	216	**/\r
	217	UINT8\r
	218	XhcReadCapReg8 (\r
a9292c13	219	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	220	IN UINT32 Offset\r
	221	);\r
	222	\r
	223	/**\r
	224	Read 4-bytes width XHCI capability register.\r
	225	\r
a9292c13	226	@param Xhc The XHCI Instance.\r
92870c98	227	@param Offset The offset of the 4-bytes width capability register.\r
	228	\r
	229	@return The register content read.\r
	230	@retval If err, return 0xFFFFFFFF.\r
	231	\r
	232	**/\r
	233	UINT32\r
	234	XhcReadCapReg (\r
a9292c13	235	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	236	IN UINT32 Offset\r
	237	);\r
	238	\r
	239	/**\r
	240	Read 4-bytes width XHCI Operational register.\r
	241	\r
a9292c13	242	@param Xhc The XHCI Instance.\r
92870c98	243	@param Offset The offset of the 4-bytes width operational register.\r
	244	\r
	245	@return The register content read.\r
	246	@retval If err, return 0xFFFFFFFF.\r
	247	\r
	248	**/\r
	249	UINT32\r
	250	XhcReadOpReg (\r
a9292c13	251	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	252	IN UINT32 Offset\r
	253	);\r
	254	\r
	255	/**\r
	256	Write the data to the 4-bytes width XHCI operational register.\r
	257	\r
a9292c13	258	@param Xhc The XHCI Instance.\r
92870c98	259	@param Offset The offset of the 4-bytes width operational register.\r
	260	@param Data The data to write.\r
	261	\r
	262	**/\r
	263	VOID\r
	264	XhcWriteOpReg (\r
a9292c13	265	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	266	IN UINT32 Offset,\r
	267	IN UINT32 Data\r
	268	);\r
	269	\r
	270	/**\r
	271	Write the data to the 2-bytes width XHCI operational register.\r
	272	\r
a9292c13	273	@param Xhc The XHCI Instance.\r
92870c98	274	@param Offset The offset of the 2-bytes width operational register.\r
	275	@param Data The data to write.\r
	276	\r
	277	**/\r
	278	VOID\r
	279	XhcWriteOpReg16 (\r
a9292c13	280	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	281	IN UINT32 Offset,\r
	282	IN UINT16 Data\r
	283	);\r
	284	\r
92870c98	285	/**\r
	286	Read XHCI runtime register.\r
	287	\r
a9292c13	288	@param Xhc The XHCI Instance.\r
92870c98	289	@param Offset The offset of the runtime register.\r
	290	\r
	291	@return The register content read\r
	292	\r
	293	**/\r
	294	UINT32\r
	295	XhcReadRuntimeReg (\r
a9292c13	296	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	297	IN UINT32 Offset\r
	298	);\r
	299	\r
92870c98	300	/**\r
	301	Write the data to the XHCI runtime register.\r
	302	\r
a9292c13	303	@param Xhc The XHCI Instance.\r
92870c98	304	@param Offset The offset of the runtime register.\r
	305	@param Data The data to write.\r
	306	\r
	307	**/\r
	308	VOID\r
	309	XhcWriteRuntimeReg (\r
a9292c13	310	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	311	IN UINT32 Offset,\r
	312	IN UINT32 Data\r
	313	);\r
	314	\r
92870c98	315	/**\r
	316	Read XHCI door bell register.\r
	317	\r
a9292c13	318	@param Xhc The XHCI Instance.\r
92870c98	319	@param Offset The offset of the door bell register.\r
	320	\r
	321	@return The register content read\r
	322	\r
	323	**/\r
	324	UINT32\r
	325	XhcReadDoorBellReg (\r
a9292c13	326	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	327	IN UINT32 Offset\r
	328	);\r
	329	\r
	330	/**\r
	331	Write the data to the XHCI door bell register.\r
	332	\r
a9292c13	333	@param Xhc The XHCI Instance.\r
92870c98	334	@param Offset The offset of the door bell register.\r
	335	@param Data The data to write.\r
	336	\r
	337	**/\r
	338	VOID\r
	339	XhcWriteDoorBellReg (\r
a9292c13	340	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	341	IN UINT32 Offset,\r
	342	IN UINT32 Data\r
	343	);\r
	344	\r
	345	/**\r
	346	Set one bit of the operational register while keeping other bits.\r
	347	\r
a9292c13	348	@param Xhc The XHCI Instance.\r
92870c98	349	@param Offset The offset of the operational register.\r
	350	@param Bit The bit mask of the register to set.\r
	351	\r
	352	**/\r
	353	VOID\r
	354	XhcSetOpRegBit (\r
a9292c13	355	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	356	IN UINT32 Offset,\r
	357	IN UINT32 Bit\r
	358	);\r
	359	\r
	360	/**\r
	361	Clear one bit of the operational register while keeping other bits.\r
	362	\r
a9292c13	363	@param Xhc The XHCI Instance.\r
92870c98	364	@param Offset The offset of the operational register.\r
	365	@param Bit The bit mask of the register to clear.\r
	366	\r
	367	**/\r
	368	VOID\r
	369	XhcClearOpRegBit (\r
a9292c13	370	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	371	IN UINT32 Offset,\r
	372	IN UINT32 Bit\r
	373	);\r
	374	\r
	375	/**\r
	376	Wait the operation register's bit as specified by Bit\r
	377	to be set (or clear).\r
	378	\r
a9292c13	379	@param Xhc The XHCI Instance.\r
92870c98	380	@param Offset The offset of the operational register.\r
	381	@param Bit The bit of the register to wait for.\r
	382	@param WaitToSet Wait the bit to set or clear.\r
	383	@param Timeout The time to wait before abort (in millisecond, ms).\r
	384	\r
	385	@retval EFI_SUCCESS The bit successfully changed by host controller.\r
	386	@retval EFI_TIMEOUT The time out occurred.\r
	387	\r
	388	**/\r
	389	EFI_STATUS\r
	390	XhcWaitOpRegBit (\r
a9292c13	391	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	392	IN UINT32 Offset,\r
	393	IN UINT32 Bit,\r
	394	IN BOOLEAN WaitToSet,\r
	395	IN UINT32 Timeout\r
	396	);\r
	397	\r
	398	/**\r
	399	Read XHCI runtime register.\r
	400	\r
a9292c13	401	@param Xhc The XHCI Instance.\r
92870c98	402	@param Offset The offset of the runtime register.\r
	403	\r
	404	@return The register content read\r
	405	\r
	406	**/\r
	407	UINT32\r
	408	XhcReadRuntimeReg (\r
a9292c13	409	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	410	IN UINT32 Offset\r
	411	);\r
	412	\r
	413	/**\r
	414	Write the data to the XHCI runtime register.\r
	415	\r
a9292c13	416	@param Xhc The XHCI Instance.\r
92870c98	417	@param Offset The offset of the runtime register.\r
	418	@param Data The data to write.\r
	419	\r
	420	**/\r
	421	VOID\r
	422	XhcWriteRuntimeReg (\r
a9292c13	423	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	424	IN UINT32 Offset,\r
	425	IN UINT32 Data\r
	426	);\r
	427	\r
	428	/**\r
	429	Set one bit of the runtime register while keeping other bits.\r
	430	\r
a9292c13	431	@param Xhc The XHCI Instance.\r
92870c98	432	@param Offset The offset of the runtime register.\r
	433	@param Bit The bit mask of the register to set.\r
	434	\r
	435	**/\r
	436	VOID\r
	437	XhcSetRuntimeRegBit (\r
a9292c13	438	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	439	IN UINT32 Offset,\r
	440	IN UINT32 Bit\r
	441	);\r
	442	\r
	443	/**\r
	444	Clear one bit of the runtime register while keeping other bits.\r
	445	\r
a9292c13	446	@param Xhc The XHCI Instance.\r
92870c98	447	@param Offset The offset of the runtime register.\r
	448	@param Bit The bit mask of the register to set.\r
	449	\r
	450	**/\r
	451	VOID\r
	452	XhcClearRuntimeRegBit (\r
a9292c13	453	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	454	IN UINT32 Offset,\r
	455	IN UINT32 Bit\r
	456	);\r
	457	\r
5bcb62a4 EL	458	/**\r
	459	Read XHCI extended capability register.\r
	460	\r
	461	@param Xhc The XHCI Instance.\r
	462	@param Offset The offset of the extended capability register.\r
	463	\r
	464	@return The register content read\r
	465	\r
	466	**/\r
	467	UINT32\r
	468	XhcReadExtCapReg (\r
	469	IN USB_XHCI_INSTANCE *Xhc,\r
	470	IN UINT32 Offset\r
	471	);\r
	472	\r
92870c98	473	/**\r
	474	Whether the XHCI host controller is halted.\r
	475	\r
a9292c13	476	@param Xhc The XHCI Instance.\r
92870c98	477	\r
	478	@retval TRUE The controller is halted.\r
	479	@retval FALSE It isn't halted.\r
	480	\r
	481	**/\r
	482	BOOLEAN\r
	483	XhcIsHalt (\r
a9292c13	484	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	485	);\r
	486	\r
	487	/**\r
	488	Whether system error occurred.\r
	489	\r
a9292c13	490	@param Xhc The XHCI Instance.\r
92870c98	491	\r
	492	@retval TRUE System error happened.\r
	493	@retval FALSE No system error.\r
	494	\r
	495	**/\r
	496	BOOLEAN\r
	497	XhcIsSysError (\r
a9292c13	498	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	499	);\r
	500	\r
	501	/**\r
	502	Reset the XHCI host controller.\r
	503	\r
a9292c13	504	@param Xhc The XHCI Instance.\r
92870c98	505	@param Timeout Time to wait before abort (in millisecond, ms).\r
	506	\r
	507	@retval EFI_SUCCESS The XHCI host controller is reset.\r
	508	@return Others Failed to reset the XHCI before Timeout.\r
	509	\r
	510	**/\r
	511	EFI_STATUS\r
	512	XhcResetHC (\r
a9292c13	513	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	514	IN UINT32 Timeout\r
	515	);\r
	516	\r
	517	/**\r
	518	Halt the XHCI host controller.\r
	519	\r
a9292c13	520	@param Xhc The XHCI Instance.\r
92870c98	521	@param Timeout Time to wait before abort (in millisecond, ms).\r
	522	\r
	523	@return EFI_SUCCESS The XHCI host controller is halt.\r
	524	@return EFI_TIMEOUT Failed to halt the XHCI before Timeout.\r
	525	\r
	526	**/\r
	527	EFI_STATUS\r
	528	XhcHaltHC (\r
a9292c13	529	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	530	IN UINT32 Timeout\r
	531	);\r
	532	\r
	533	/**\r
	534	Set the XHCI host controller to run.\r
	535	\r
a9292c13	536	@param Xhc The XHCI Instance.\r
92870c98	537	@param Timeout Time to wait before abort (in millisecond, ms).\r
	538	\r
	539	@return EFI_SUCCESS The XHCI host controller is running.\r
	540	@return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.\r
	541	\r
	542	**/\r
	543	EFI_STATUS\r
	544	XhcRunHC (\r
a9292c13	545	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	546	IN UINT32 Timeout\r
	547	);\r
	548	\r
	549	/**\r
5bcb62a4	550	Calculate the offset of the XHCI capability.\r
92870c98	551	\r
a9292c13	552	@param Xhc The XHCI Instance.\r
5bcb62a4	553	@param CapId The XHCI Capability ID.\r
92870c98	554	\r
	555	@return The offset of XHCI legacy support capability register.\r
	556	\r
	557	**/\r
	558	UINT32\r
5bcb62a4 EL	559	XhcGetCapabilityAddr (\r
	560	IN USB_XHCI_INSTANCE *Xhc,\r
	561	IN UINT8 CapId\r
92870c98	562	);\r
	563	\r
	564	#endif\r