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MdeModulePkg XhciDxe: Extract new XhciInsertAsyncIntTransfer function
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.h
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92870c98 1/** @file\r
2\r
3 This file contains the definition for XHCI host controller schedule routines.\r
4\r
d1102dba 5Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
92870c98 6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _EFI_XHCI_SCHED_H_\r
17#define _EFI_XHCI_SCHED_H_\r
18\r
19#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
20\r
21//\r
22// Transfer types, used in URB to identify the transfer type\r
23//\r
24#define XHC_CTRL_TRANSFER 0x01\r
25#define XHC_BULK_TRANSFER 0x02\r
26#define XHC_INT_TRANSFER_SYNC 0x04\r
27#define XHC_INT_TRANSFER_ASYNC 0x08\r
28#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
29\r
30//\r
31// 6.4.6 TRB Types\r
32//\r
33#define TRB_TYPE_NORMAL 1\r
34#define TRB_TYPE_SETUP_STAGE 2\r
35#define TRB_TYPE_DATA_STAGE 3\r
36#define TRB_TYPE_STATUS_STAGE 4\r
37#define TRB_TYPE_ISOCH 5\r
38#define TRB_TYPE_LINK 6\r
39#define TRB_TYPE_EVENT_DATA 7\r
40#define TRB_TYPE_NO_OP 8\r
41#define TRB_TYPE_EN_SLOT 9\r
42#define TRB_TYPE_DIS_SLOT 10\r
43#define TRB_TYPE_ADDRESS_DEV 11\r
44#define TRB_TYPE_CON_ENDPOINT 12\r
45#define TRB_TYPE_EVALU_CONTXT 13\r
46#define TRB_TYPE_RESET_ENDPOINT 14\r
47#define TRB_TYPE_STOP_ENDPOINT 15\r
48#define TRB_TYPE_SET_TR_DEQUE 16\r
49#define TRB_TYPE_RESET_DEV 17\r
50#define TRB_TYPE_GET_PORT_BANW 21\r
51#define TRB_TYPE_FORCE_HEADER 22\r
52#define TRB_TYPE_NO_OP_COMMAND 23\r
53#define TRB_TYPE_TRANS_EVENT 32\r
54#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
55#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
56#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
57#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
58#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
59\r
60//\r
61// Endpoint Type (EP Type).\r
62//\r
63#define ED_NOT_VALID 0\r
64#define ED_ISOCH_OUT 1\r
65#define ED_BULK_OUT 2\r
66#define ED_INTERRUPT_OUT 3\r
67#define ED_CONTROL_BIDIR 4\r
68#define ED_ISOCH_IN 5\r
69#define ED_BULK_IN 6\r
70#define ED_INTERRUPT_IN 7\r
71\r
72//\r
73// 6.4.5 TRB Completion Codes\r
74//\r
75#define TRB_COMPLETION_INVALID 0\r
76#define TRB_COMPLETION_SUCCESS 1\r
77#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
78#define TRB_COMPLETION_BABBLE_ERROR 3\r
79#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
80#define TRB_COMPLETION_TRB_ERROR 5\r
81#define TRB_COMPLETION_STALL_ERROR 6\r
82#define TRB_COMPLETION_SHORT_PACKET 13\r
49be9c3c
RN		 83#define TRB_COMPLETION_STOPPED 26\r
84#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27\r
92870c98 85\r
86//\r
a9292c13 87// The topology string used to present usb device location\r
92870c98 88//\r
a9292c13 89typedef struct _USB_DEV_TOPOLOGY {\r
90 //\r
91 // The tier concatenation of down stream port.\r
92 //\r
93 UINT32 RouteString:20;\r
94 //\r
95 // The root port number of the chain.\r
96 //\r
97 UINT32 RootPortNum:8;\r
98 //\r
99 // The Tier the device reside.\r
100 //\r
101 UINT32 TierNum:4;\r
102} USB_DEV_TOPOLOGY;\r
103\r
104//\r
105// USB Device's RouteChart\r
106//\r
107typedef union _USB_DEV_ROUTE {\r
108 UINT32 Dword;\r
109 USB_DEV_TOPOLOGY Route;\r
92870c98 110} USB_DEV_ROUTE;\r
111\r
112//\r
113// Endpoint address and its capabilities\r
114//\r
115typedef struct _USB_ENDPOINT {\r
6b4483cd 116 //\r
117 // Store logical device address assigned by UsbBus\r
118 // It's because some XHCI host controllers may assign the same physcial device\r
119 // address for those devices inserted at different root port.\r
120 //\r
121 UINT8 BusAddr;\r
92870c98 122 UINT8 DevAddr;\r
123 UINT8 EpAddr;\r
124 EFI_USB_DATA_DIRECTION Direction;\r
125 UINT8 DevSpeed;\r
126 UINTN MaxPacket;\r
127 UINTN Type;\r
128} USB_ENDPOINT;\r
129\r
130//\r
a9292c13 131// TRB Template\r
92870c98 132//\r
a9292c13 133typedef struct _TRB_TEMPLATE {\r
134 UINT32 Parameter1;\r
135\r
136 UINT32 Parameter2;\r
137\r
138 UINT32 Status;\r
139\r
92870c98 140 UINT32 CycleBit:1;\r
141 UINT32 RsvdZ1:9;\r
142 UINT32 Type:6;\r
a9292c13 143 UINT32 Control:16;\r
144} TRB_TEMPLATE;\r
92870c98 145\r
146typedef struct _TRANSFER_RING {\r
147 VOID *RingSeg0;\r
148 UINTN TrbNumber;\r
a9292c13 149 TRB_TEMPLATE *RingEnqueue;\r
150 TRB_TEMPLATE *RingDequeue;\r
92870c98 151 UINT32 RingPCS;\r
152} TRANSFER_RING;\r
153\r
154typedef struct _EVENT_RING {\r
92870c98 155 VOID *ERSTBase;\r
156 VOID *EventRingSeg0;\r
157 UINTN TrbNumber;\r
a9292c13 158 TRB_TEMPLATE *EventRingEnqueue;\r
159 TRB_TEMPLATE *EventRingDequeue;\r
92870c98 160 UINT32 EventRingCCS;\r
161} EVENT_RING;\r
162\r
163//\r
164// URB (Usb Request Block) contains information for all kinds of\r
165// usb requests.\r
166//\r
167typedef struct _URB {\r
168 UINT32 Signature;\r
169 LIST_ENTRY UrbList;\r
170 //\r
171 // Usb Device URB related information\r
172 //\r
173 USB_ENDPOINT Ep;\r
174 EFI_USB_DEVICE_REQUEST *Request;\r
175 VOID *Data;\r
176 UINTN DataLen;\r
1847ed0b
EL		 177 VOID *DataPhy;\r
178 VOID *DataMap;\r
92870c98 179 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
180 VOID *Context;\r
181 //\r
182 // Execute result\r
183 //\r
184 UINT32 Result;\r
185 //\r
186 // completed data length\r
187 //\r
188 UINTN Completed;\r
189 //\r
190 // Command/Tranfer Ring info\r
191 //\r
192 TRANSFER_RING *Ring;\r
a9292c13 193 TRB_TEMPLATE *TrbStart;\r
194 TRB_TEMPLATE *TrbEnd;\r
92870c98 195 UINTN TrbNum;\r
a50f7c4c 196 BOOLEAN StartDone;\r
197 BOOLEAN EndDone;\r
198 BOOLEAN Finished;\r
199\r
200 TRB_TEMPLATE *EvtTrb;\r
92870c98 201} URB;\r
202\r
92870c98 203//\r
204// 6.5 Event Ring Segment Table\r
205// The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r
206// expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r
207// Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r
208// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r
209//\r
210typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
211 UINT32 PtrLo;\r
212 UINT32 PtrHi;\r
213 UINT32 RingTrbSize:16;\r
214 UINT32 RsvdZ1:16;\r
215 UINT32 RsvdZ2;\r
216} EVENT_RING_SEG_TABLE_ENTRY;\r
217\r
218//\r
219// 6.4.1.1 Normal TRB\r
220// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
221// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
222// Rings, and to define the Data stage information for Control Transfer Rings.\r
223//\r
224typedef struct _TRANSFER_TRB_NORMAL {\r
225 UINT32 TRBPtrLo;\r
a9292c13 226\r
92870c98 227 UINT32 TRBPtrHi;\r
a9292c13 228\r
39e97c39 229 UINT32 Length:17;\r
92870c98 230 UINT32 TDSize:5;\r
231 UINT32 IntTarget:10;\r
a9292c13 232\r
92870c98 233 UINT32 CycleBit:1;\r
234 UINT32 ENT:1;\r
235 UINT32 ISP:1;\r
236 UINT32 NS:1;\r
237 UINT32 CH:1;\r
238 UINT32 IOC:1;\r
239 UINT32 IDT:1;\r
240 UINT32 RsvdZ1:2;\r
241 UINT32 BEI:1;\r
242 UINT32 Type:6;\r
243 UINT32 RsvdZ2:16;\r
244} TRANSFER_TRB_NORMAL;\r
245\r
246//\r
247// 6.4.1.2.1 Setup Stage TRB\r
248// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r
249//\r
a9292c13 250typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r
92870c98 251 UINT32 bmRequestType:8;\r
252 UINT32 bRequest:8;\r
253 UINT32 wValue:16;\r
254\r
255 UINT32 wIndex:16;\r
256 UINT32 wLength:16;\r
257\r
39e97c39 258 UINT32 Length:17;\r
92870c98 259 UINT32 RsvdZ1:5;\r
260 UINT32 IntTarget:10;\r
261\r
262 UINT32 CycleBit:1;\r
263 UINT32 RsvdZ2:4;\r
264 UINT32 IOC:1;\r
265 UINT32 IDT:1;\r
266 UINT32 RsvdZ3:3;\r
267 UINT32 Type:6;\r
268 UINT32 TRT:2;\r
269 UINT32 RsvdZ4:14;\r
270} TRANSFER_TRB_CONTROL_SETUP;\r
271\r
272//\r
273// 6.4.1.2.2 Data Stage TRB\r
274// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
275//\r
276typedef struct _TRANSFER_TRB_CONTROL_DATA {\r
277 UINT32 TRBPtrLo;\r
a9292c13 278\r
92870c98 279 UINT32 TRBPtrHi;\r
a9292c13 280\r
39e97c39 281 UINT32 Length:17;\r
92870c98 282 UINT32 TDSize:5;\r
283 UINT32 IntTarget:10;\r
a9292c13 284\r
92870c98 285 UINT32 CycleBit:1;\r
286 UINT32 ENT:1;\r
287 UINT32 ISP:1;\r
288 UINT32 NS:1;\r
289 UINT32 CH:1;\r
290 UINT32 IOC:1;\r
291 UINT32 IDT:1;\r
292 UINT32 RsvdZ1:3;\r
293 UINT32 Type:6;\r
294 UINT32 DIR:1;\r
295 UINT32 RsvdZ2:15;\r
296} TRANSFER_TRB_CONTROL_DATA;\r
297\r
298//\r
299// 6.4.1.2.2 Data Stage TRB\r
300// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
301//\r
302typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r
303 UINT32 RsvdZ1;\r
304 UINT32 RsvdZ2;\r
a9292c13 305\r
92870c98 306 UINT32 RsvdZ3:22;\r
307 UINT32 IntTarget:10;\r
a9292c13 308\r
92870c98 309 UINT32 CycleBit:1;\r
310 UINT32 ENT:1;\r
311 UINT32 RsvdZ4:2;\r
312 UINT32 CH:1;\r
313 UINT32 IOC:1;\r
314 UINT32 RsvdZ5:4;\r
315 UINT32 Type:6;\r
316 UINT32 DIR:1;\r
317 UINT32 RsvdZ6:15;\r
318} TRANSFER_TRB_CONTROL_STATUS;\r
319\r
320//\r
321// 6.4.2.1 Transfer Event TRB\r
322// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
323// for more information on the use and operation of Transfer Events.\r
324//\r
325typedef struct _EVT_TRB_TRANSFER {\r
326 UINT32 TRBPtrLo;\r
a9292c13 327\r
92870c98 328 UINT32 TRBPtrHi;\r
a9292c13 329\r
39e97c39 330 UINT32 Length:24;\r
a9292c13 331 UINT32 Completecode:8;\r
332\r
92870c98 333 UINT32 CycleBit:1;\r
334 UINT32 RsvdZ1:1;\r
335 UINT32 ED:1;\r
336 UINT32 RsvdZ2:7;\r
337 UINT32 Type:6;\r
a9292c13 338 UINT32 EndpointId:5;\r
92870c98 339 UINT32 RsvdZ3:3;\r
340 UINT32 SlotId:8;\r
341} EVT_TRB_TRANSFER;\r
342\r
343//\r
344// 6.4.2.2 Command Completion Event TRB\r
345// A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r
346// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r
347//\r
a9292c13 348typedef struct _EVT_TRB_COMMAND_COMPLETION {\r
92870c98 349 UINT32 TRBPtrLo;\r
a9292c13 350\r
92870c98 351 UINT32 TRBPtrHi;\r
a9292c13 352\r
92870c98 353 UINT32 RsvdZ2:24;\r
a9292c13 354 UINT32 Completecode:8;\r
355\r
92870c98 356 UINT32 CycleBit:1;\r
357 UINT32 RsvdZ3:9;\r
358 UINT32 Type:6;\r
359 UINT32 VFID:8;\r
360 UINT32 SlotId:8;\r
a9292c13 361} EVT_TRB_COMMAND_COMPLETION;\r
362\r
363typedef union _TRB {\r
364 TRB_TEMPLATE TrbTemplate;\r
365 TRANSFER_TRB_NORMAL TrbNormal;\r
366 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r
367 TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r
368 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r
369} TRB;\r
92870c98 370\r
371//\r
372// 6.4.3.1 No Op Command TRB\r
373// The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r
a9292c13 374// mechanisms offered by the xHCI.\r
92870c98 375//\r
376typedef struct _CMD_TRB_NO_OP {\r
377 UINT32 RsvdZ0;\r
378 UINT32 RsvdZ1;\r
379 UINT32 RsvdZ2;\r
a9292c13 380\r
92870c98 381 UINT32 CycleBit:1;\r
382 UINT32 RsvdZ3:9;\r
383 UINT32 Type:6;\r
384 UINT32 RsvdZ4:16;\r
385} CMD_TRB_NO_OP;\r
386\r
387//\r
388// 6.4.3.2 Enable Slot Command TRB\r
389// The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r
390// selected slot to the host in a Command Completion Event.\r
391//\r
a9292c13 392typedef struct _CMD_TRB_ENABLE_SLOT {\r
92870c98 393 UINT32 RsvdZ0;\r
394 UINT32 RsvdZ1;\r
395 UINT32 RsvdZ2;\r
a9292c13 396\r
92870c98 397 UINT32 CycleBit:1;\r
398 UINT32 RsvdZ3:9;\r
399 UINT32 Type:6;\r
400 UINT32 RsvdZ4:16;\r
a9292c13 401} CMD_TRB_ENABLE_SLOT;\r
92870c98 402\r
403//\r
404// 6.4.3.3 Disable Slot Command TRB\r
405// The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r
406// internal xHC resources assigned to the slot.\r
407//\r
a9292c13 408typedef struct _CMD_TRB_DISABLE_SLOT {\r
92870c98 409 UINT32 RsvdZ0;\r
410 UINT32 RsvdZ1;\r
411 UINT32 RsvdZ2;\r
a9292c13 412\r
92870c98 413 UINT32 CycleBit:1;\r
414 UINT32 RsvdZ3:9;\r
415 UINT32 Type:6;\r
416 UINT32 RsvdZ4:8;\r
417 UINT32 SlotId:8;\r
a9292c13 418} CMD_TRB_DISABLE_SLOT;\r
92870c98 419\r
420//\r
421// 6.4.3.4 Address Device Command TRB\r
422// The Address Device Command TRB transitions the selected Device Context from the Default to the\r
423// Addressed state and causes the xHC to select an address for the USB device in the Default State and\r
424// issue a SET_ADDRESS request to the USB device.\r
425//\r
a9292c13 426typedef struct _CMD_TRB_ADDRESS_DEVICE {\r
92870c98 427 UINT32 PtrLo;\r
a9292c13 428\r
92870c98 429 UINT32 PtrHi;\r
a9292c13 430\r
92870c98 431 UINT32 RsvdZ1;\r
a9292c13 432\r
92870c98 433 UINT32 CycleBit:1;\r
434 UINT32 RsvdZ2:8;\r
435 UINT32 BSR:1;\r
436 UINT32 Type:6;\r
437 UINT32 RsvdZ3:8;\r
438 UINT32 SlotId:8;\r
a9292c13 439} CMD_TRB_ADDRESS_DEVICE;\r
92870c98 440\r
441//\r
442// 6.4.3.5 Configure Endpoint Command TRB\r
443// The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r
444// endpoints selected by the command.\r
445//\r
a9292c13 446typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r
92870c98 447 UINT32 PtrLo;\r
a9292c13 448\r
92870c98 449 UINT32 PtrHi;\r
a9292c13 450\r
92870c98 451 UINT32 RsvdZ1;\r
a9292c13 452\r
92870c98 453 UINT32 CycleBit:1;\r
454 UINT32 RsvdZ2:8;\r
455 UINT32 DC:1;\r
456 UINT32 Type:6;\r
457 UINT32 RsvdZ3:8;\r
458 UINT32 SlotId:8;\r
a9292c13 459} CMD_TRB_CONFIG_ENDPOINT;\r
92870c98 460\r
461//\r
462// 6.4.3.6 Evaluate Context Command TRB\r
463// The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r
464// Context data structures in the Device Context have been modified by system software and that the xHC\r
465// shall evaluate any changes\r
466//\r
a9292c13 467typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r
92870c98 468 UINT32 PtrLo;\r
a9292c13 469\r
92870c98 470 UINT32 PtrHi;\r
a9292c13 471\r
92870c98 472 UINT32 RsvdZ1;\r
a9292c13 473\r
92870c98 474 UINT32 CycleBit:1;\r
475 UINT32 RsvdZ2:9;\r
476 UINT32 Type:6;\r
477 UINT32 RsvdZ3:8;\r
478 UINT32 SlotId:8;\r
a9292c13 479} CMD_TRB_EVALUATE_CONTEXT;\r
92870c98 480\r
481//\r
482// 6.4.3.7 Reset Endpoint Command TRB\r
483// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r
484//\r
a9292c13 485typedef struct _CMD_TRB_RESET_ENDPOINT {\r
92870c98 486 UINT32 RsvdZ0;\r
487 UINT32 RsvdZ1;\r
488 UINT32 RsvdZ2;\r
a9292c13 489\r
92870c98 490 UINT32 CycleBit:1;\r
491 UINT32 RsvdZ3:8;\r
492 UINT32 TSP:1;\r
493 UINT32 Type:6;\r
494 UINT32 EDID:5;\r
495 UINT32 RsvdZ4:3;\r
496 UINT32 SlotId:8;\r
a9292c13 497} CMD_TRB_RESET_ENDPOINT;\r
92870c98 498\r
499//\r
500// 6.4.3.8 Stop Endpoint Command TRB\r
501// The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r
502// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r
503//\r
a9292c13 504typedef struct _CMD_TRB_STOP_ENDPOINT {\r
92870c98 505 UINT32 RsvdZ0;\r
506 UINT32 RsvdZ1;\r
507 UINT32 RsvdZ2;\r
a9292c13 508\r
92870c98 509 UINT32 CycleBit:1;\r
510 UINT32 RsvdZ3:9;\r
511 UINT32 Type:6;\r
512 UINT32 EDID:5;\r
513 UINT32 RsvdZ4:2;\r
514 UINT32 SP:1;\r
515 UINT32 SlotId:8;\r
a9292c13 516} CMD_TRB_STOP_ENDPOINT;\r
92870c98 517\r
518//\r
519// 6.4.3.9 Set TR Dequeue Pointer Command TRB\r
520// The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r
521// Pointer and DCS fields of an Endpoint or Stream Context.\r
522//\r
a9292c13 523typedef struct _CMD_SET_TR_DEQ_POINTER {\r
92870c98 524 UINT32 PtrLo;\r
a9292c13 525\r
92870c98 526 UINT32 PtrHi;\r
a9292c13 527\r
92870c98 528 UINT32 RsvdZ1:16;\r
529 UINT32 StreamID:16;\r
a9292c13 530\r
92870c98 531 UINT32 CycleBit:1;\r
532 UINT32 RsvdZ2:9;\r
533 UINT32 Type:6;\r
534 UINT32 Endpoint:5;\r
535 UINT32 RsvdZ3:3;\r
536 UINT32 SlotId:8;\r
a9292c13 537} CMD_SET_TR_DEQ_POINTER;\r
92870c98 538\r
539//\r
a9292c13 540// 6.4.4.1 Link TRB\r
92870c98 541// A Link TRB provides support for non-contiguous TRB Rings.\r
542//\r
a9292c13 543typedef struct _LINK_TRB {\r
92870c98 544 UINT32 PtrLo;\r
a9292c13 545\r
92870c98 546 UINT32 PtrHi;\r
a9292c13 547\r
92870c98 548 UINT32 RsvdZ1:22;\r
549 UINT32 InterTarget:10;\r
a9292c13 550\r
92870c98 551 UINT32 CycleBit:1;\r
552 UINT32 TC:1;\r
553 UINT32 RsvdZ2:2;\r
554 UINT32 CH:1;\r
555 UINT32 IOC:1;\r
556 UINT32 RsvdZ3:4;\r
557 UINT32 Type:6;\r
558 UINT32 RsvdZ4:16;\r
a9292c13 559} LINK_TRB;\r
92870c98 560\r
561//\r
562// 6.2.2 Slot Context\r
563//\r
564typedef struct _SLOT_CONTEXT {\r
a9292c13 565 UINT32 RouteString:20;\r
92870c98 566 UINT32 Speed:4;\r
567 UINT32 RsvdZ1:1;\r
568 UINT32 MTT:1;\r
569 UINT32 Hub:1;\r
570 UINT32 ContextEntries:5;\r
571\r
572 UINT32 MaxExitLatency:16;\r
573 UINT32 RootHubPortNum:8;\r
574 UINT32 PortNum:8;\r
575\r
576 UINT32 TTHubSlotId:8;\r
577 UINT32 TTPortNum:8;\r
578 UINT32 TTT:2;\r
579 UINT32 RsvdZ2:4;\r
580 UINT32 InterTarget:10;\r
581\r
582 UINT32 DeviceAddress:8;\r
583 UINT32 RsvdZ3:19;\r
584 UINT32 SlotState:5;\r
585\r
586 UINT32 RsvdZ4;\r
587 UINT32 RsvdZ5;\r
588 UINT32 RsvdZ6;\r
589 UINT32 RsvdZ7;\r
590} SLOT_CONTEXT;\r
591\r
6b4483cd 592typedef struct _SLOT_CONTEXT_64 {\r
593 UINT32 RouteString:20;\r
594 UINT32 Speed:4;\r
595 UINT32 RsvdZ1:1;\r
596 UINT32 MTT:1;\r
597 UINT32 Hub:1;\r
598 UINT32 ContextEntries:5;\r
599\r
600 UINT32 MaxExitLatency:16;\r
601 UINT32 RootHubPortNum:8;\r
602 UINT32 PortNum:8;\r
603\r
604 UINT32 TTHubSlotId:8;\r
605 UINT32 TTPortNum:8;\r
606 UINT32 TTT:2;\r
607 UINT32 RsvdZ2:4;\r
608 UINT32 InterTarget:10;\r
609\r
610 UINT32 DeviceAddress:8;\r
611 UINT32 RsvdZ3:19;\r
612 UINT32 SlotState:5;\r
613\r
614 UINT32 RsvdZ4;\r
615 UINT32 RsvdZ5;\r
616 UINT32 RsvdZ6;\r
617 UINT32 RsvdZ7;\r
618\r
619 UINT32 RsvdZ8;\r
620 UINT32 RsvdZ9;\r
621 UINT32 RsvdZ10;\r
622 UINT32 RsvdZ11;\r
d1102dba 623\r
6b4483cd 624 UINT32 RsvdZ12;\r
625 UINT32 RsvdZ13;\r
626 UINT32 RsvdZ14;\r
627 UINT32 RsvdZ15;\r
628\r
629} SLOT_CONTEXT_64;\r
630\r
631\r
92870c98 632//\r
633// 6.2.3 Endpoint Context\r
634//\r
635typedef struct _ENDPOINT_CONTEXT {\r
636 UINT32 EPState:3;\r
637 UINT32 RsvdZ1:5;\r
638 UINT32 Mult:2;\r
639 UINT32 MaxPStreams:5;\r
640 UINT32 LSA:1;\r
641 UINT32 Interval:8;\r
642 UINT32 RsvdZ2:8;\r
643\r
644 UINT32 RsvdZ3:1;\r
645 UINT32 CErr:2;\r
646 UINT32 EPType:3;\r
647 UINT32 RsvdZ4:1;\r
648 UINT32 HID:1;\r
649 UINT32 MaxBurstSize:8;\r
650 UINT32 MaxPacketSize:16;\r
651\r
652 UINT32 PtrLo;\r
653\r
654 UINT32 PtrHi;\r
655\r
656 UINT32 AverageTRBLength:16;\r
657 UINT32 MaxESITPayload:16;\r
658\r
659 UINT32 RsvdZ5;\r
660 UINT32 RsvdZ6;\r
661 UINT32 RsvdZ7;\r
662} ENDPOINT_CONTEXT;\r
663\r
6b4483cd 664typedef struct _ENDPOINT_CONTEXT_64 {\r
665 UINT32 EPState:3;\r
666 UINT32 RsvdZ1:5;\r
667 UINT32 Mult:2;\r
668 UINT32 MaxPStreams:5;\r
669 UINT32 LSA:1;\r
670 UINT32 Interval:8;\r
671 UINT32 RsvdZ2:8;\r
672\r
673 UINT32 RsvdZ3:1;\r
674 UINT32 CErr:2;\r
675 UINT32 EPType:3;\r
676 UINT32 RsvdZ4:1;\r
677 UINT32 HID:1;\r
678 UINT32 MaxBurstSize:8;\r
679 UINT32 MaxPacketSize:16;\r
680\r
681 UINT32 PtrLo;\r
682\r
683 UINT32 PtrHi;\r
684\r
685 UINT32 AverageTRBLength:16;\r
686 UINT32 MaxESITPayload:16;\r
687\r
688 UINT32 RsvdZ5;\r
689 UINT32 RsvdZ6;\r
690 UINT32 RsvdZ7;\r
d1102dba 691\r
6b4483cd 692 UINT32 RsvdZ8;\r
693 UINT32 RsvdZ9;\r
694 UINT32 RsvdZ10;\r
695 UINT32 RsvdZ11;\r
d1102dba 696\r
6b4483cd 697 UINT32 RsvdZ12;\r
698 UINT32 RsvdZ13;\r
699 UINT32 RsvdZ14;\r
700 UINT32 RsvdZ15;\r
701\r
702} ENDPOINT_CONTEXT_64;\r
703\r
704\r
92870c98 705//\r
706// 6.2.5.1 Input Control Context\r
707//\r
708typedef struct _INPUT_CONTRL_CONTEXT {\r
709 UINT32 Dword1;\r
710 UINT32 Dword2;\r
711 UINT32 RsvdZ1;\r
712 UINT32 RsvdZ2;\r
713 UINT32 RsvdZ3;\r
714 UINT32 RsvdZ4;\r
715 UINT32 RsvdZ5;\r
716 UINT32 RsvdZ6;\r
717} INPUT_CONTRL_CONTEXT;\r
718\r
6b4483cd 719typedef struct _INPUT_CONTRL_CONTEXT_64 {\r
720 UINT32 Dword1;\r
721 UINT32 Dword2;\r
722 UINT32 RsvdZ1;\r
723 UINT32 RsvdZ2;\r
724 UINT32 RsvdZ3;\r
725 UINT32 RsvdZ4;\r
726 UINT32 RsvdZ5;\r
727 UINT32 RsvdZ6;\r
728 UINT32 RsvdZ7;\r
729 UINT32 RsvdZ8;\r
730 UINT32 RsvdZ9;\r
731 UINT32 RsvdZ10;\r
732 UINT32 RsvdZ11;\r
733 UINT32 RsvdZ12;\r
734 UINT32 RsvdZ13;\r
735 UINT32 RsvdZ14;\r
736} INPUT_CONTRL_CONTEXT_64;\r
737\r
92870c98 738//\r
739// 6.2.1 Device Context\r
740//\r
741typedef struct _DEVICE_CONTEXT {\r
742 SLOT_CONTEXT Slot;\r
743 ENDPOINT_CONTEXT EP[31];\r
744} DEVICE_CONTEXT;\r
745\r
6b4483cd 746typedef struct _DEVICE_CONTEXT_64 {\r
747 SLOT_CONTEXT_64 Slot;\r
748 ENDPOINT_CONTEXT_64 EP[31];\r
749} DEVICE_CONTEXT_64;\r
750\r
92870c98 751//\r
752// 6.2.5 Input Context\r
753//\r
754typedef struct _INPUT_CONTEXT {\r
755 INPUT_CONTRL_CONTEXT InputControlContext;\r
756 SLOT_CONTEXT Slot;\r
757 ENDPOINT_CONTEXT EP[31];\r
758} INPUT_CONTEXT;\r
759\r
6b4483cd 760typedef struct _INPUT_CONTEXT_64 {\r
761 INPUT_CONTRL_CONTEXT_64 InputControlContext;\r
762 SLOT_CONTEXT_64 Slot;\r
763 ENDPOINT_CONTEXT_64 EP[31];\r
764} INPUT_CONTEXT_64;\r
765\r
766\r
92870c98 767/**\r
768 Initialize the XHCI host controller for schedule.\r
769\r
a9292c13 770 @param Xhc The XHCI Instance to be initialized.\r
92870c98 771\r
772**/\r
773VOID\r
774XhcInitSched (\r
a9292c13 775 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 776 );\r
777\r
778/**\r
779 Free the resouce allocated at initializing schedule.\r
780\r
a9292c13 781 @param Xhc The XHCI Instance.\r
92870c98 782\r
783**/\r
784VOID\r
785XhcFreeSched (\r
a9292c13 786 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 787 );\r
788\r
789/**\r
790 Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r
791\r
a9292c13 792 @param Xhc The XHCI Instance.\r
92870c98 793 @param Urb The URB to be rung.\r
794\r
795 @retval EFI_SUCCESS Successfully ring the door bell.\r
796\r
797**/\r
798EFI_STATUS\r
799RingIntTransferDoorBell (\r
a9292c13 800 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 801 IN URB *Urb\r
802 );\r
803\r
804/**\r
805 Execute the transfer by polling the URB. This is a synchronous operation.\r
806\r
a9292c13 807 @param Xhc The XHCI Instance.\r
92870c98 808 @param CmdTransfer The executed URB is for cmd transfer or not.\r
809 @param Urb The URB to execute.\r
a9292c13 810 @param Timeout The time to wait before abort, in millisecond.\r
92870c98 811\r
812 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
813 @return EFI_TIMEOUT The transfer failed due to time out.\r
814 @return EFI_SUCCESS The transfer finished OK.\r
815\r
816**/\r
817EFI_STATUS\r
818XhcExecTransfer (\r
a9292c13 819 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 820 IN BOOLEAN CmdTransfer,\r
821 IN URB *Urb,\r
a9292c13 822 IN UINTN Timeout\r
92870c98 823 );\r
824\r
825/**\r
826 Delete a single asynchronous interrupt transfer for\r
827 the device and endpoint.\r
828\r
a9292c13 829 @param Xhc The XHCI Instance.\r
6b4483cd 830 @param BusAddr The logical device address assigned by UsbBus driver.\r
92870c98 831 @param EpNum The endpoint of the target.\r
832\r
833 @retval EFI_SUCCESS An asynchronous transfer is removed.\r
834 @retval EFI_NOT_FOUND No transfer for the device is found.\r
835\r
836**/\r
837EFI_STATUS\r
838XhciDelAsyncIntTransfer (\r
a9292c13 839 IN USB_XHCI_INSTANCE *Xhc,\r
6b4483cd 840 IN UINT8 BusAddr,\r
92870c98 841 IN UINT8 EpNum\r
842 );\r
843\r
844/**\r
845 Remove all the asynchronous interrupt transfers.\r
846\r
a9292c13 847 @param Xhc The XHCI Instance.\r
92870c98 848\r
849**/\r
850VOID\r
851XhciDelAllAsyncIntTransfers (\r
a9292c13 852 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 853 );\r
854\r
6681582d
SZ		 855/**\r
856 Insert a single asynchronous interrupt transfer for\r
857 the device and endpoint.\r
858\r
859 @param Xhc The XHCI Instance\r
860 @param BusAddr The logical device address assigned by UsbBus driver\r
861 @param EpAddr Endpoint addrress\r
862 @param DevSpeed The device speed\r
863 @param MaxPacket The max packet length of the endpoint\r
864 @param DataLen The length of data buffer\r
865 @param Callback The function to call when data is transferred\r
866 @param Context The context to the callback\r
867\r
868 @return Created URB or NULL\r
869\r
870**/\r
871URB *\r
872XhciInsertAsyncIntTransfer (\r
873 IN USB_XHCI_INSTANCE *Xhc,\r
874 IN UINT8 BusAddr,\r
875 IN UINT8 EpAddr,\r
876 IN UINT8 DevSpeed,\r
877 IN UINTN MaxPacket,\r
878 IN UINTN DataLen,\r
879 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
880 IN VOID *Context\r
881 );\r
882\r
92870c98 883/**\r
884 Set Bios Ownership\r
885\r
a9292c13 886 @param Xhc The XHCI Instance.\r
92870c98 887\r
888**/\r
889VOID\r
890XhcSetBiosOwnership (\r
a9292c13 891 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 892 );\r
893\r
894/**\r
895 Clear Bios Ownership\r
896\r
a9292c13 897 @param Xhc The XHCI Instance.\r
92870c98 898\r
899**/\r
900VOID\r
901XhcClearBiosOwnership (\r
a9292c13 902 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 903 );\r
904\r
92870c98 905/**\r
906 Find out the slot id according to the device's route string.\r
907\r
a9292c13 908 @param Xhc The XHCI Instance.\r
909 @param RouteString The route string described the device location.\r
92870c98 910\r
911 @return The slot id used by the device.\r
912\r
913**/\r
914UINT8\r
915EFIAPI\r
916XhcRouteStringToSlotId (\r
a9292c13 917 IN USB_XHCI_INSTANCE *Xhc,\r
918 IN USB_DEV_ROUTE RouteString\r
92870c98 919 );\r
920\r
921/**\r
922 Calculate the device context index by endpoint address and direction.\r
923\r
924 @param EpAddr The target endpoint number.\r
925 @param Direction The direction of the target endpoint.\r
926\r
927 @return The device context index of endpoint.\r
928\r
929**/\r
930UINT8\r
931XhcEndpointToDci (\r
932 IN UINT8 EpAddr,\r
933 IN UINT8 Direction\r
934 );\r
935\r
936/**\r
937 Ring the door bell to notify XHCI there is a transaction to be executed.\r
938\r
a9292c13 939 @param Xhc The XHCI Instance.\r
92870c98 940 @param SlotId The slot id of the target device.\r
941 @param Dci The device context index of the target slot or endpoint.\r
942\r
943 @retval EFI_SUCCESS Successfully ring the door bell.\r
944\r
945**/\r
946EFI_STATUS\r
947EFIAPI\r
948XhcRingDoorBell (\r
a9292c13 949 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 950 IN UINT8 SlotId,\r
951 IN UINT8 Dci\r
952 );\r
953\r
954/**\r
955 Interrupt transfer periodic check handler.\r
956\r
957 @param Event Interrupt event.\r
a9292c13 958 @param Context Pointer to USB_XHCI_INSTANCE.\r
92870c98 959\r
960**/\r
961VOID\r
962EFIAPI\r
963XhcMonitorAsyncRequests (\r
964 IN EFI_EVENT Event,\r
965 IN VOID *Context\r
966 );\r
967\r
968/**\r
969 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r
970\r
a9292c13 971 @param Xhc The XHCI Instance.\r
92870c98 972 @param ParentRouteChart The route string pointed to the parent device if it exists.\r
973 @param Port The port to be polled.\r
974 @param PortState The port state.\r
975\r
976 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r
977 @retval Others Should not appear.\r
978\r
979**/\r
980EFI_STATUS\r
981EFIAPI\r
982XhcPollPortStatusChange (\r
a9292c13 983 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 984 IN USB_DEV_ROUTE ParentRouteChart,\r
985 IN UINT8 Port,\r
986 IN EFI_USB_PORT_STATUS *PortState\r
987 );\r
988\r
989/**\r
990 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
991\r
a9292c13 992 @param Xhc The XHCI Instance.\r
92870c98 993 @param SlotId The slot id to be configured.\r
994 @param PortNum The total number of downstream port supported by the hub.\r
995 @param TTT The TT think time of the hub device.\r
996 @param MTT The multi-TT of the hub device.\r
997\r
998 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
999\r
1000**/\r
1001EFI_STATUS\r
1002XhcConfigHubContext (\r
a9292c13 1003 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1004 IN UINT8 SlotId,\r
1005 IN UINT8 PortNum,\r
1006 IN UINT8 TTT,\r
1007 IN UINT8 MTT\r
1008 );\r
1009\r
6b4483cd 1010\r
1011/**\r
1012 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
1013\r
1014 @param Xhc The XHCI Instance.\r
1015 @param SlotId The slot id to be configured.\r
1016 @param PortNum The total number of downstream port supported by the hub.\r
1017 @param TTT The TT think time of the hub device.\r
1018 @param MTT The multi-TT of the hub device.\r
1019\r
1020 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
1021\r
1022**/\r
1023EFI_STATUS\r
1024XhcConfigHubContext64 (\r
1025 IN USB_XHCI_INSTANCE *Xhc,\r
1026 IN UINT8 SlotId,\r
1027 IN UINT8 PortNum,\r
1028 IN UINT8 TTT,\r
1029 IN UINT8 MTT\r
1030 );\r
1031\r
1032\r
92870c98 1033/**\r
1034 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
1035\r
a9292c13 1036 @param Xhc The XHCI Instance.\r
92870c98 1037 @param SlotId The slot id to be configured.\r
1038 @param DeviceSpeed The device's speed.\r
1039 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1040\r
1041 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
1042\r
1043**/\r
1044EFI_STATUS\r
1045EFIAPI\r
1046XhcSetConfigCmd (\r
a9292c13 1047 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1048 IN UINT8 SlotId,\r
1049 IN UINT8 DeviceSpeed,\r
1050 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
1051 );\r
1052\r
6b4483cd 1053\r
1054/**\r
1055 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
1056\r
1057 @param Xhc The XHCI Instance.\r
1058 @param SlotId The slot id to be configured.\r
1059 @param DeviceSpeed The device's speed.\r
1060 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1061\r
1062 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
1063\r
1064**/\r
1065EFI_STATUS\r
1066EFIAPI\r
1067XhcSetConfigCmd64 (\r
1068 IN USB_XHCI_INSTANCE *Xhc,\r
1069 IN UINT8 SlotId,\r
1070 IN UINT8 DeviceSpeed,\r
1071 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
1072 );\r
1073\r
e1f2dfec
SZ		 1074/**\r
1075 Set interface through XHCI's Configure_Endpoint cmd.\r
1076\r
1077 @param Xhc The XHCI Instance.\r
1078 @param SlotId The slot id to be configured.\r
1079 @param DeviceSpeed The device's speed.\r
1080 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1081 @param Request USB device request to send.\r
1082\r
1083 @retval EFI_SUCCESS Successfully set interface.\r
1084\r
1085**/\r
1086EFI_STATUS\r
1087EFIAPI\r
1088XhcSetInterface (\r
1089 IN USB_XHCI_INSTANCE *Xhc,\r
1090 IN UINT8 SlotId,\r
1091 IN UINT8 DeviceSpeed,\r
1092 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
1093 IN EFI_USB_DEVICE_REQUEST *Request\r
1094 );\r
1095\r
1096/**\r
1097 Set interface through XHCI's Configure_Endpoint cmd.\r
1098\r
1099 @param Xhc The XHCI Instance.\r
1100 @param SlotId The slot id to be configured.\r
1101 @param DeviceSpeed The device's speed.\r
1102 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1103 @param Request USB device request to send.\r
1104\r
1105 @retval EFI_SUCCESS Successfully set interface.\r
1106\r
1107**/\r
1108EFI_STATUS\r
1109EFIAPI\r
1110XhcSetInterface64 (\r
1111 IN USB_XHCI_INSTANCE *Xhc,\r
1112 IN UINT8 SlotId,\r
1113 IN UINT8 DeviceSpeed,\r
1114 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
1115 IN EFI_USB_DEVICE_REQUEST *Request\r
1116 );\r
6b4483cd 1117\r
92870c98 1118/**\r
1119 Find out the actual device address according to the requested device address from UsbBus.\r
1120\r
a9292c13 1121 @param Xhc The XHCI Instance.\r
1122 @param BusDevAddr The requested device address by UsbBus upper driver.\r
92870c98 1123\r
1124 @return The actual device address assigned to the device.\r
1125\r
1126**/\r
1127UINT8\r
1128EFIAPI\r
1129XhcBusDevAddrToSlotId (\r
a9292c13 1130 IN USB_XHCI_INSTANCE *Xhc,\r
1131 IN UINT8 BusDevAddr\r
92870c98 1132 );\r
1133\r
1134/**\r
1135 Assign and initialize the device slot for a new device.\r
1136\r
a9292c13 1137 @param Xhc The XHCI Instance.\r
92870c98 1138 @param ParentRouteChart The route string pointed to the parent device.\r
1139 @param ParentPort The port at which the device is located.\r
1140 @param RouteChart The route string pointed to the device.\r
1141 @param DeviceSpeed The device speed.\r
1142\r
1143 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1144\r
1145**/\r
1146EFI_STATUS\r
1147EFIAPI\r
1148XhcInitializeDeviceSlot (\r
a9292c13 1149 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1150 IN USB_DEV_ROUTE ParentRouteChart,\r
1151 IN UINT16 ParentPort,\r
1152 IN USB_DEV_ROUTE RouteChart,\r
1153 IN UINT8 DeviceSpeed\r
1154 );\r
1155\r
6b4483cd 1156/**\r
1157 Assign and initialize the device slot for a new device.\r
1158\r
1159 @param Xhc The XHCI Instance.\r
1160 @param ParentRouteChart The route string pointed to the parent device.\r
1161 @param ParentPort The port at which the device is located.\r
1162 @param RouteChart The route string pointed to the device.\r
1163 @param DeviceSpeed The device speed.\r
1164\r
1165 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1166\r
1167**/\r
1168EFI_STATUS\r
1169EFIAPI\r
1170XhcInitializeDeviceSlot64 (\r
1171 IN USB_XHCI_INSTANCE *Xhc,\r
1172 IN USB_DEV_ROUTE ParentRouteChart,\r
1173 IN UINT16 ParentPort,\r
1174 IN USB_DEV_ROUTE RouteChart,\r
1175 IN UINT8 DeviceSpeed\r
1176 );\r
1177\r
92870c98 1178/**\r
1179 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
1180\r
a9292c13 1181 @param Xhc The XHCI Instance.\r
92870c98 1182 @param SlotId The slot id to be evaluated.\r
1183 @param MaxPacketSize The max packet size supported by the device control transfer.\r
1184\r
1185 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
1186\r
1187**/\r
1188EFI_STATUS\r
1189EFIAPI\r
1190XhcEvaluateContext (\r
a9292c13 1191 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1192 IN UINT8 SlotId,\r
1193 IN UINT32 MaxPacketSize\r
1194 );\r
1195\r
6b4483cd 1196\r
1197/**\r
1198 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
1199\r
1200 @param Xhc The XHCI Instance.\r
1201 @param SlotId The slot id to be evaluated.\r
1202 @param MaxPacketSize The max packet size supported by the device control transfer.\r
1203\r
1204 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
1205\r
1206**/\r
1207EFI_STATUS\r
1208EFIAPI\r
1209XhcEvaluateContext64 (\r
1210 IN USB_XHCI_INSTANCE *Xhc,\r
1211 IN UINT8 SlotId,\r
1212 IN UINT32 MaxPacketSize\r
1213 );\r
1214\r
1215\r
92870c98 1216/**\r
1217 Disable the specified device slot.\r
1218\r
a9292c13 1219 @param Xhc The XHCI Instance.\r
92870c98 1220 @param SlotId The slot id to be disabled.\r
1221\r
1222 @retval EFI_SUCCESS Successfully disable the device slot.\r
1223\r
1224**/\r
1225EFI_STATUS\r
1226EFIAPI\r
1227XhcDisableSlotCmd (\r
a9292c13 1228 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1229 IN UINT8 SlotId\r
1230 );\r
1231\r
6b4483cd 1232\r
1233/**\r
1234 Disable the specified device slot.\r
1235\r
1236 @param Xhc The XHCI Instance.\r
1237 @param SlotId The slot id to be disabled.\r
1238\r
1239 @retval EFI_SUCCESS Successfully disable the device slot.\r
1240\r
1241**/\r
1242EFI_STATUS\r
1243EFIAPI\r
1244XhcDisableSlotCmd64 (\r
1245 IN USB_XHCI_INSTANCE *Xhc,\r
1246 IN UINT8 SlotId\r
1247 );\r
1248\r
1249\r
92870c98 1250/**\r
1251 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
1252\r
a9292c13 1253 @param Xhc The XHCI Instance.\r
92870c98 1254 @param TrsRing The transfer ring to sync.\r
1255\r
1256 @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r
1257\r
1258**/\r
1259EFI_STATUS\r
1260EFIAPI\r
1261XhcSyncTrsRing (\r
a9292c13 1262 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1263 TRANSFER_RING *TrsRing\r
1264 );\r
1265\r
1266/**\r
1267 Synchronize the specified event ring to update the enqueue and dequeue pointer.\r
1268\r
a9292c13 1269 @param Xhc The XHCI Instance.\r
92870c98 1270 @param EvtRing The event ring to sync.\r
1271\r
1272 @retval EFI_SUCCESS The event ring is synchronized successfully.\r
1273\r
1274**/\r
1275EFI_STATUS\r
1276EFIAPI\r
1277XhcSyncEventRing (\r
a9292c13 1278 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1279 EVENT_RING *EvtRing\r
1280 );\r
1281\r
1282/**\r
1283 Check if there is a new generated event.\r
1284\r
a9292c13 1285 @param Xhc The XHCI Instance.\r
92870c98 1286 @param EvtRing The event ring to check.\r
1287 @param NewEvtTrb The new event TRB found.\r
1288\r
1289 @retval EFI_SUCCESS Found a new event TRB at the event ring.\r
1290 @retval EFI_NOT_READY The event ring has no new event.\r
1291\r
1292**/\r
1293EFI_STATUS\r
1294EFIAPI\r
1295XhcCheckNewEvent (\r
a9292c13 1296 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1297 IN EVENT_RING *EvtRing,\r
a9292c13 1298 OUT TRB_TEMPLATE **NewEvtTrb\r
92870c98 1299 );\r
1300\r
1301/**\r
1302 Create XHCI transfer ring.\r
1303\r
a9292c13 1304 @param Xhc The XHCI Instance.\r
92870c98 1305 @param TrbNum The number of TRB in the ring.\r
1306 @param TransferRing The created transfer ring.\r
1307\r
1308**/\r
1309VOID\r
1310CreateTransferRing (\r
a9292c13 1311 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1312 IN UINTN TrbNum,\r
1313 OUT TRANSFER_RING *TransferRing\r
1314 );\r
1315\r
1316/**\r
1317 Create XHCI event ring.\r
1318\r
a9292c13 1319 @param Xhc The XHCI Instance.\r
92870c98 1320 @param EventRing The created event ring.\r
1321\r
1322**/\r
1323VOID\r
1324CreateEventRing (\r
a9292c13 1325 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1326 OUT EVENT_RING *EventRing\r
1327 );\r
1328\r
1329/**\r
1330 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r
1331 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r
1332 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r
1333 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r
1334 Stopped to the Running state.\r
1335\r
a9292c13 1336 @param Xhc The XHCI Instance.\r
92870c98 1337 @param Urb The urb which makes the endpoint halted.\r
1338\r
1339 @retval EFI_SUCCESS The recovery is successful.\r
1340 @retval Others Failed to recovery halted endpoint.\r
1341\r
1342**/\r
1343EFI_STATUS\r
1344EFIAPI\r
1345XhcRecoverHaltedEndpoint (\r
a9292c13 1346 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1347 IN URB *Urb\r
1348 );\r
1349\r
12e6c738
FT		 1350/**\r
1351 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r
1352 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r
1353 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r
1354 state.\r
1355\r
1356 @param Xhc The XHCI Instance.\r
1357 @param Urb The urb which doesn't get completed in a specified timeout range.\r
1358\r
1359 @retval EFI_SUCCESS The dequeuing of the TDs is successful.\r
1360 @retval Others Failed to stop the endpoint and dequeue the TDs.\r
1361\r
1362**/\r
1363EFI_STATUS\r
1364EFIAPI\r
1365XhcDequeueTrbFromEndpoint (\r
1366 IN USB_XHCI_INSTANCE *Xhc,\r
1367 IN URB *Urb\r
1368 );\r
1369\r
1370/**\r
1371 Stop endpoint through XHCI's Stop_Endpoint cmd.\r
1372\r
1373 @param Xhc The XHCI Instance.\r
1374 @param SlotId The slot id to be configured.\r
1375 @param Dci The device context index of endpoint.\r
49be9c3c 1376 @param PendingUrb The pending URB to check completion status when stopping the end point.\r
12e6c738
FT		 1377\r
1378 @retval EFI_SUCCESS Stop endpoint successfully.\r
1379 @retval Others Failed to stop endpoint.\r
1380\r
1381**/\r
1382EFI_STATUS\r
1383EFIAPI\r
1384XhcStopEndpoint (\r
1385 IN USB_XHCI_INSTANCE *Xhc,\r
1386 IN UINT8 SlotId,\r
49be9c3c
RN		 1387 IN UINT8 Dci,\r
1388 IN URB *PendingUrb OPTIONAL\r
12e6c738
FT		 1389 );\r
1390\r
1391/**\r
1392 Reset endpoint through XHCI's Reset_Endpoint cmd.\r
1393\r
1394 @param Xhc The XHCI Instance.\r
1395 @param SlotId The slot id to be configured.\r
1396 @param Dci The device context index of endpoint.\r
1397\r
1398 @retval EFI_SUCCESS Reset endpoint successfully.\r
1399 @retval Others Failed to reset endpoint.\r
1400\r
1401**/\r
1402EFI_STATUS\r
1403EFIAPI\r
1404XhcResetEndpoint (\r
1405 IN USB_XHCI_INSTANCE *Xhc,\r
1406 IN UINT8 SlotId,\r
1407 IN UINT8 Dci\r
1408 );\r
1409\r
1410/**\r
1411 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r
1412\r
1413 @param Xhc The XHCI Instance.\r
1414 @param SlotId The slot id to be configured.\r
1415 @param Dci The device context index of endpoint.\r
1416 @param Urb The dequeue pointer of the transfer ring specified\r
1417 by the urb to be updated.\r
1418\r
1419 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.\r
1420 @retval Others Failed to set transfer ring dequeue pointer.\r
1421\r
1422**/\r
1423EFI_STATUS\r
1424EFIAPI\r
1425XhcSetTrDequeuePointer (\r
1426 IN USB_XHCI_INSTANCE *Xhc,\r
1427 IN UINT8 SlotId,\r
1428 IN UINT8 Dci,\r
1429 IN URB *Urb\r
1430 );\r
1431\r
92870c98 1432/**\r
1433 Create a new URB for a new transaction.\r
1434\r
a9292c13 1435 @param Xhc The XHCI Instance\r
92870c98 1436 @param DevAddr The device address\r
1437 @param EpAddr Endpoint addrress\r
1438 @param DevSpeed The device speed\r
1439 @param MaxPacket The max packet length of the endpoint\r
1440 @param Type The transaction type\r
1441 @param Request The standard USB request for control transfer\r
1442 @param Data The user data to transfer\r
1443 @param DataLen The length of data buffer\r
1444 @param Callback The function to call when data is transferred\r
1445 @param Context The context to the callback\r
1446\r
1447 @return Created URB or NULL\r
1448\r
1449**/\r
1450URB*\r
1451XhcCreateUrb (\r
a9292c13 1452 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1453 IN UINT8 DevAddr,\r
1454 IN UINT8 EpAddr,\r
1455 IN UINT8 DevSpeed,\r
1456 IN UINTN MaxPacket,\r
1457 IN UINTN Type,\r
1458 IN EFI_USB_DEVICE_REQUEST *Request,\r
1459 IN VOID *Data,\r
1460 IN UINTN DataLen,\r
1461 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
1462 IN VOID *Context\r
1463 );\r
1464\r
1847ed0b
EL		 1465/**\r
1466 Free an allocated URB.\r
1467\r
1468 @param Xhc The XHCI device.\r
1469 @param Urb The URB to free.\r
1470\r
1471**/\r
1472VOID\r
1473XhcFreeUrb (\r
1474 IN USB_XHCI_INSTANCE *Xhc,\r
1475 IN URB *Urb\r
1476 );\r
1477\r
92870c98 1478/**\r
1479 Create a transfer TRB.\r
1480\r
a9292c13 1481 @param Xhc The XHCI Instance\r
92870c98 1482 @param Urb The urb used to construct the transfer TRB.\r
1483\r
1484 @return Created TRB or NULL\r
1485\r
1486**/\r
1487EFI_STATUS\r
1488XhcCreateTransferTrb (\r
a9292c13 1489 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1490 IN URB *Urb\r
1491 );\r
1492\r
1493#endif\r
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