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Revert "EhciDxe: Use common buffer for AsyncInterruptTransfer"
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.h
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92870c98 1/** @file\r
2\r
3 This file contains the definition for XHCI host controller schedule routines.\r
4\r
d1102dba 5Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
92870c98 6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _EFI_XHCI_SCHED_H_\r
17#define _EFI_XHCI_SCHED_H_\r
18\r
19#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
20\r
21//\r
22// Transfer types, used in URB to identify the transfer type\r
23//\r
24#define XHC_CTRL_TRANSFER 0x01\r
25#define XHC_BULK_TRANSFER 0x02\r
26#define XHC_INT_TRANSFER_SYNC 0x04\r
27#define XHC_INT_TRANSFER_ASYNC 0x08\r
28#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
29\r
30//\r
31// 6.4.6 TRB Types\r
32//\r
33#define TRB_TYPE_NORMAL 1\r
34#define TRB_TYPE_SETUP_STAGE 2\r
35#define TRB_TYPE_DATA_STAGE 3\r
36#define TRB_TYPE_STATUS_STAGE 4\r
37#define TRB_TYPE_ISOCH 5\r
38#define TRB_TYPE_LINK 6\r
39#define TRB_TYPE_EVENT_DATA 7\r
40#define TRB_TYPE_NO_OP 8\r
41#define TRB_TYPE_EN_SLOT 9\r
42#define TRB_TYPE_DIS_SLOT 10\r
43#define TRB_TYPE_ADDRESS_DEV 11\r
44#define TRB_TYPE_CON_ENDPOINT 12\r
45#define TRB_TYPE_EVALU_CONTXT 13\r
46#define TRB_TYPE_RESET_ENDPOINT 14\r
47#define TRB_TYPE_STOP_ENDPOINT 15\r
48#define TRB_TYPE_SET_TR_DEQUE 16\r
49#define TRB_TYPE_RESET_DEV 17\r
50#define TRB_TYPE_GET_PORT_BANW 21\r
51#define TRB_TYPE_FORCE_HEADER 22\r
52#define TRB_TYPE_NO_OP_COMMAND 23\r
53#define TRB_TYPE_TRANS_EVENT 32\r
54#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
55#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
56#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
57#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
58#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
59\r
60//\r
61// Endpoint Type (EP Type).\r
62//\r
63#define ED_NOT_VALID 0\r
64#define ED_ISOCH_OUT 1\r
65#define ED_BULK_OUT 2\r
66#define ED_INTERRUPT_OUT 3\r
67#define ED_CONTROL_BIDIR 4\r
68#define ED_ISOCH_IN 5\r
69#define ED_BULK_IN 6\r
70#define ED_INTERRUPT_IN 7\r
71\r
72//\r
73// 6.4.5 TRB Completion Codes\r
74//\r
75#define TRB_COMPLETION_INVALID 0\r
76#define TRB_COMPLETION_SUCCESS 1\r
77#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
78#define TRB_COMPLETION_BABBLE_ERROR 3\r
79#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
80#define TRB_COMPLETION_TRB_ERROR 5\r
81#define TRB_COMPLETION_STALL_ERROR 6\r
82#define TRB_COMPLETION_SHORT_PACKET 13\r
49be9c3c
RN		 83#define TRB_COMPLETION_STOPPED 26\r
84#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27\r
92870c98 85\r
86//\r
a9292c13 87// The topology string used to present usb device location\r
92870c98 88//\r
a9292c13 89typedef struct _USB_DEV_TOPOLOGY {\r
90 //\r
91 // The tier concatenation of down stream port.\r
92 //\r
93 UINT32 RouteString:20;\r
94 //\r
95 // The root port number of the chain.\r
96 //\r
97 UINT32 RootPortNum:8;\r
98 //\r
99 // The Tier the device reside.\r
100 //\r
101 UINT32 TierNum:4;\r
102} USB_DEV_TOPOLOGY;\r
103\r
104//\r
105// USB Device's RouteChart\r
106//\r
107typedef union _USB_DEV_ROUTE {\r
108 UINT32 Dword;\r
109 USB_DEV_TOPOLOGY Route;\r
92870c98 110} USB_DEV_ROUTE;\r
111\r
112//\r
113// Endpoint address and its capabilities\r
114//\r
115typedef struct _USB_ENDPOINT {\r
6b4483cd 116 //\r
117 // Store logical device address assigned by UsbBus\r
118 // It's because some XHCI host controllers may assign the same physcial device\r
119 // address for those devices inserted at different root port.\r
120 //\r
121 UINT8 BusAddr;\r
92870c98 122 UINT8 DevAddr;\r
123 UINT8 EpAddr;\r
124 EFI_USB_DATA_DIRECTION Direction;\r
125 UINT8 DevSpeed;\r
126 UINTN MaxPacket;\r
127 UINTN Type;\r
128} USB_ENDPOINT;\r
129\r
130//\r
a9292c13 131// TRB Template\r
92870c98 132//\r
a9292c13 133typedef struct _TRB_TEMPLATE {\r
134 UINT32 Parameter1;\r
135\r
136 UINT32 Parameter2;\r
137\r
138 UINT32 Status;\r
139\r
92870c98 140 UINT32 CycleBit:1;\r
141 UINT32 RsvdZ1:9;\r
142 UINT32 Type:6;\r
a9292c13 143 UINT32 Control:16;\r
144} TRB_TEMPLATE;\r
92870c98 145\r
146typedef struct _TRANSFER_RING {\r
147 VOID *RingSeg0;\r
148 UINTN TrbNumber;\r
a9292c13 149 TRB_TEMPLATE *RingEnqueue;\r
150 TRB_TEMPLATE *RingDequeue;\r
92870c98 151 UINT32 RingPCS;\r
152} TRANSFER_RING;\r
153\r
154typedef struct _EVENT_RING {\r
92870c98 155 VOID *ERSTBase;\r
156 VOID *EventRingSeg0;\r
157 UINTN TrbNumber;\r
a9292c13 158 TRB_TEMPLATE *EventRingEnqueue;\r
159 TRB_TEMPLATE *EventRingDequeue;\r
92870c98 160 UINT32 EventRingCCS;\r
161} EVENT_RING;\r
162\r
163//\r
164// URB (Usb Request Block) contains information for all kinds of\r
165// usb requests.\r
166//\r
167typedef struct _URB {\r
168 UINT32 Signature;\r
169 LIST_ENTRY UrbList;\r
170 //\r
171 // Usb Device URB related information\r
172 //\r
173 USB_ENDPOINT Ep;\r
174 EFI_USB_DEVICE_REQUEST *Request;\r
77792099 175 BOOLEAN AllocateCommonBuffer;\r
92870c98 176 VOID *Data;\r
177 UINTN DataLen;\r
1847ed0b
EL		 178 VOID *DataPhy;\r
179 VOID *DataMap;\r
92870c98 180 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
181 VOID *Context;\r
182 //\r
183 // Execute result\r
184 //\r
185 UINT32 Result;\r
186 //\r
187 // completed data length\r
188 //\r
189 UINTN Completed;\r
190 //\r
191 // Command/Tranfer Ring info\r
192 //\r
193 TRANSFER_RING *Ring;\r
a9292c13 194 TRB_TEMPLATE *TrbStart;\r
195 TRB_TEMPLATE *TrbEnd;\r
92870c98 196 UINTN TrbNum;\r
a50f7c4c 197 BOOLEAN StartDone;\r
198 BOOLEAN EndDone;\r
199 BOOLEAN Finished;\r
200\r
201 TRB_TEMPLATE *EvtTrb;\r
92870c98 202} URB;\r
203\r
92870c98 204//\r
205// 6.5 Event Ring Segment Table\r
206// The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r
207// expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r
208// Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r
209// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r
210//\r
211typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
212 UINT32 PtrLo;\r
213 UINT32 PtrHi;\r
214 UINT32 RingTrbSize:16;\r
215 UINT32 RsvdZ1:16;\r
216 UINT32 RsvdZ2;\r
217} EVENT_RING_SEG_TABLE_ENTRY;\r
218\r
219//\r
220// 6.4.1.1 Normal TRB\r
221// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
222// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
223// Rings, and to define the Data stage information for Control Transfer Rings.\r
224//\r
225typedef struct _TRANSFER_TRB_NORMAL {\r
226 UINT32 TRBPtrLo;\r
a9292c13 227\r
92870c98 228 UINT32 TRBPtrHi;\r
a9292c13 229\r
39e97c39 230 UINT32 Length:17;\r
92870c98 231 UINT32 TDSize:5;\r
232 UINT32 IntTarget:10;\r
a9292c13 233\r
92870c98 234 UINT32 CycleBit:1;\r
235 UINT32 ENT:1;\r
236 UINT32 ISP:1;\r
237 UINT32 NS:1;\r
238 UINT32 CH:1;\r
239 UINT32 IOC:1;\r
240 UINT32 IDT:1;\r
241 UINT32 RsvdZ1:2;\r
242 UINT32 BEI:1;\r
243 UINT32 Type:6;\r
244 UINT32 RsvdZ2:16;\r
245} TRANSFER_TRB_NORMAL;\r
246\r
247//\r
248// 6.4.1.2.1 Setup Stage TRB\r
249// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r
250//\r
a9292c13 251typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r
92870c98 252 UINT32 bmRequestType:8;\r
253 UINT32 bRequest:8;\r
254 UINT32 wValue:16;\r
255\r
256 UINT32 wIndex:16;\r
257 UINT32 wLength:16;\r
258\r
39e97c39 259 UINT32 Length:17;\r
92870c98 260 UINT32 RsvdZ1:5;\r
261 UINT32 IntTarget:10;\r
262\r
263 UINT32 CycleBit:1;\r
264 UINT32 RsvdZ2:4;\r
265 UINT32 IOC:1;\r
266 UINT32 IDT:1;\r
267 UINT32 RsvdZ3:3;\r
268 UINT32 Type:6;\r
269 UINT32 TRT:2;\r
270 UINT32 RsvdZ4:14;\r
271} TRANSFER_TRB_CONTROL_SETUP;\r
272\r
273//\r
274// 6.4.1.2.2 Data Stage TRB\r
275// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
276//\r
277typedef struct _TRANSFER_TRB_CONTROL_DATA {\r
278 UINT32 TRBPtrLo;\r
a9292c13 279\r
92870c98 280 UINT32 TRBPtrHi;\r
a9292c13 281\r
39e97c39 282 UINT32 Length:17;\r
92870c98 283 UINT32 TDSize:5;\r
284 UINT32 IntTarget:10;\r
a9292c13 285\r
92870c98 286 UINT32 CycleBit:1;\r
287 UINT32 ENT:1;\r
288 UINT32 ISP:1;\r
289 UINT32 NS:1;\r
290 UINT32 CH:1;\r
291 UINT32 IOC:1;\r
292 UINT32 IDT:1;\r
293 UINT32 RsvdZ1:3;\r
294 UINT32 Type:6;\r
295 UINT32 DIR:1;\r
296 UINT32 RsvdZ2:15;\r
297} TRANSFER_TRB_CONTROL_DATA;\r
298\r
299//\r
300// 6.4.1.2.2 Data Stage TRB\r
301// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
302//\r
303typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r
304 UINT32 RsvdZ1;\r
305 UINT32 RsvdZ2;\r
a9292c13 306\r
92870c98 307 UINT32 RsvdZ3:22;\r
308 UINT32 IntTarget:10;\r
a9292c13 309\r
92870c98 310 UINT32 CycleBit:1;\r
311 UINT32 ENT:1;\r
312 UINT32 RsvdZ4:2;\r
313 UINT32 CH:1;\r
314 UINT32 IOC:1;\r
315 UINT32 RsvdZ5:4;\r
316 UINT32 Type:6;\r
317 UINT32 DIR:1;\r
318 UINT32 RsvdZ6:15;\r
319} TRANSFER_TRB_CONTROL_STATUS;\r
320\r
321//\r
322// 6.4.2.1 Transfer Event TRB\r
323// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
324// for more information on the use and operation of Transfer Events.\r
325//\r
326typedef struct _EVT_TRB_TRANSFER {\r
327 UINT32 TRBPtrLo;\r
a9292c13 328\r
92870c98 329 UINT32 TRBPtrHi;\r
a9292c13 330\r
39e97c39 331 UINT32 Length:24;\r
a9292c13 332 UINT32 Completecode:8;\r
333\r
92870c98 334 UINT32 CycleBit:1;\r
335 UINT32 RsvdZ1:1;\r
336 UINT32 ED:1;\r
337 UINT32 RsvdZ2:7;\r
338 UINT32 Type:6;\r
a9292c13 339 UINT32 EndpointId:5;\r
92870c98 340 UINT32 RsvdZ3:3;\r
341 UINT32 SlotId:8;\r
342} EVT_TRB_TRANSFER;\r
343\r
344//\r
345// 6.4.2.2 Command Completion Event TRB\r
346// A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r
347// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r
348//\r
a9292c13 349typedef struct _EVT_TRB_COMMAND_COMPLETION {\r
92870c98 350 UINT32 TRBPtrLo;\r
a9292c13 351\r
92870c98 352 UINT32 TRBPtrHi;\r
a9292c13 353\r
92870c98 354 UINT32 RsvdZ2:24;\r
a9292c13 355 UINT32 Completecode:8;\r
356\r
92870c98 357 UINT32 CycleBit:1;\r
358 UINT32 RsvdZ3:9;\r
359 UINT32 Type:6;\r
360 UINT32 VFID:8;\r
361 UINT32 SlotId:8;\r
a9292c13 362} EVT_TRB_COMMAND_COMPLETION;\r
363\r
364typedef union _TRB {\r
365 TRB_TEMPLATE TrbTemplate;\r
366 TRANSFER_TRB_NORMAL TrbNormal;\r
367 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r
368 TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r
369 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r
370} TRB;\r
92870c98 371\r
372//\r
373// 6.4.3.1 No Op Command TRB\r
374// The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r
a9292c13 375// mechanisms offered by the xHCI.\r
92870c98 376//\r
377typedef struct _CMD_TRB_NO_OP {\r
378 UINT32 RsvdZ0;\r
379 UINT32 RsvdZ1;\r
380 UINT32 RsvdZ2;\r
a9292c13 381\r
92870c98 382 UINT32 CycleBit:1;\r
383 UINT32 RsvdZ3:9;\r
384 UINT32 Type:6;\r
385 UINT32 RsvdZ4:16;\r
386} CMD_TRB_NO_OP;\r
387\r
388//\r
389// 6.4.3.2 Enable Slot Command TRB\r
390// The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r
391// selected slot to the host in a Command Completion Event.\r
392//\r
a9292c13 393typedef struct _CMD_TRB_ENABLE_SLOT {\r
92870c98 394 UINT32 RsvdZ0;\r
395 UINT32 RsvdZ1;\r
396 UINT32 RsvdZ2;\r
a9292c13 397\r
92870c98 398 UINT32 CycleBit:1;\r
399 UINT32 RsvdZ3:9;\r
400 UINT32 Type:6;\r
401 UINT32 RsvdZ4:16;\r
a9292c13 402} CMD_TRB_ENABLE_SLOT;\r
92870c98 403\r
404//\r
405// 6.4.3.3 Disable Slot Command TRB\r
406// The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r
407// internal xHC resources assigned to the slot.\r
408//\r
a9292c13 409typedef struct _CMD_TRB_DISABLE_SLOT {\r
92870c98 410 UINT32 RsvdZ0;\r
411 UINT32 RsvdZ1;\r
412 UINT32 RsvdZ2;\r
a9292c13 413\r
92870c98 414 UINT32 CycleBit:1;\r
415 UINT32 RsvdZ3:9;\r
416 UINT32 Type:6;\r
417 UINT32 RsvdZ4:8;\r
418 UINT32 SlotId:8;\r
a9292c13 419} CMD_TRB_DISABLE_SLOT;\r
92870c98 420\r
421//\r
422// 6.4.3.4 Address Device Command TRB\r
423// The Address Device Command TRB transitions the selected Device Context from the Default to the\r
424// Addressed state and causes the xHC to select an address for the USB device in the Default State and\r
425// issue a SET_ADDRESS request to the USB device.\r
426//\r
a9292c13 427typedef struct _CMD_TRB_ADDRESS_DEVICE {\r
92870c98 428 UINT32 PtrLo;\r
a9292c13 429\r
92870c98 430 UINT32 PtrHi;\r
a9292c13 431\r
92870c98 432 UINT32 RsvdZ1;\r
a9292c13 433\r
92870c98 434 UINT32 CycleBit:1;\r
435 UINT32 RsvdZ2:8;\r
436 UINT32 BSR:1;\r
437 UINT32 Type:6;\r
438 UINT32 RsvdZ3:8;\r
439 UINT32 SlotId:8;\r
a9292c13 440} CMD_TRB_ADDRESS_DEVICE;\r
92870c98 441\r
442//\r
443// 6.4.3.5 Configure Endpoint Command TRB\r
444// The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r
445// endpoints selected by the command.\r
446//\r
a9292c13 447typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r
92870c98 448 UINT32 PtrLo;\r
a9292c13 449\r
92870c98 450 UINT32 PtrHi;\r
a9292c13 451\r
92870c98 452 UINT32 RsvdZ1;\r
a9292c13 453\r
92870c98 454 UINT32 CycleBit:1;\r
455 UINT32 RsvdZ2:8;\r
456 UINT32 DC:1;\r
457 UINT32 Type:6;\r
458 UINT32 RsvdZ3:8;\r
459 UINT32 SlotId:8;\r
a9292c13 460} CMD_TRB_CONFIG_ENDPOINT;\r
92870c98 461\r
462//\r
463// 6.4.3.6 Evaluate Context Command TRB\r
464// The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r
465// Context data structures in the Device Context have been modified by system software and that the xHC\r
466// shall evaluate any changes\r
467//\r
a9292c13 468typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r
92870c98 469 UINT32 PtrLo;\r
a9292c13 470\r
92870c98 471 UINT32 PtrHi;\r
a9292c13 472\r
92870c98 473 UINT32 RsvdZ1;\r
a9292c13 474\r
92870c98 475 UINT32 CycleBit:1;\r
476 UINT32 RsvdZ2:9;\r
477 UINT32 Type:6;\r
478 UINT32 RsvdZ3:8;\r
479 UINT32 SlotId:8;\r
a9292c13 480} CMD_TRB_EVALUATE_CONTEXT;\r
92870c98 481\r
482//\r
483// 6.4.3.7 Reset Endpoint Command TRB\r
484// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r
485//\r
a9292c13 486typedef struct _CMD_TRB_RESET_ENDPOINT {\r
92870c98 487 UINT32 RsvdZ0;\r
488 UINT32 RsvdZ1;\r
489 UINT32 RsvdZ2;\r
a9292c13 490\r
92870c98 491 UINT32 CycleBit:1;\r
492 UINT32 RsvdZ3:8;\r
493 UINT32 TSP:1;\r
494 UINT32 Type:6;\r
495 UINT32 EDID:5;\r
496 UINT32 RsvdZ4:3;\r
497 UINT32 SlotId:8;\r
a9292c13 498} CMD_TRB_RESET_ENDPOINT;\r
92870c98 499\r
500//\r
501// 6.4.3.8 Stop Endpoint Command TRB\r
502// The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r
503// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r
504//\r
a9292c13 505typedef struct _CMD_TRB_STOP_ENDPOINT {\r
92870c98 506 UINT32 RsvdZ0;\r
507 UINT32 RsvdZ1;\r
508 UINT32 RsvdZ2;\r
a9292c13 509\r
92870c98 510 UINT32 CycleBit:1;\r
511 UINT32 RsvdZ3:9;\r
512 UINT32 Type:6;\r
513 UINT32 EDID:5;\r
514 UINT32 RsvdZ4:2;\r
515 UINT32 SP:1;\r
516 UINT32 SlotId:8;\r
a9292c13 517} CMD_TRB_STOP_ENDPOINT;\r
92870c98 518\r
519//\r
520// 6.4.3.9 Set TR Dequeue Pointer Command TRB\r
521// The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r
522// Pointer and DCS fields of an Endpoint or Stream Context.\r
523//\r
a9292c13 524typedef struct _CMD_SET_TR_DEQ_POINTER {\r
92870c98 525 UINT32 PtrLo;\r
a9292c13 526\r
92870c98 527 UINT32 PtrHi;\r
a9292c13 528\r
92870c98 529 UINT32 RsvdZ1:16;\r
530 UINT32 StreamID:16;\r
a9292c13 531\r
92870c98 532 UINT32 CycleBit:1;\r
533 UINT32 RsvdZ2:9;\r
534 UINT32 Type:6;\r
535 UINT32 Endpoint:5;\r
536 UINT32 RsvdZ3:3;\r
537 UINT32 SlotId:8;\r
a9292c13 538} CMD_SET_TR_DEQ_POINTER;\r
92870c98 539\r
540//\r
a9292c13 541// 6.4.4.1 Link TRB\r
92870c98 542// A Link TRB provides support for non-contiguous TRB Rings.\r
543//\r
a9292c13 544typedef struct _LINK_TRB {\r
92870c98 545 UINT32 PtrLo;\r
a9292c13 546\r
92870c98 547 UINT32 PtrHi;\r
a9292c13 548\r
92870c98 549 UINT32 RsvdZ1:22;\r
550 UINT32 InterTarget:10;\r
a9292c13 551\r
92870c98 552 UINT32 CycleBit:1;\r
553 UINT32 TC:1;\r
554 UINT32 RsvdZ2:2;\r
555 UINT32 CH:1;\r
556 UINT32 IOC:1;\r
557 UINT32 RsvdZ3:4;\r
558 UINT32 Type:6;\r
559 UINT32 RsvdZ4:16;\r
a9292c13 560} LINK_TRB;\r
92870c98 561\r
562//\r
563// 6.2.2 Slot Context\r
564//\r
565typedef struct _SLOT_CONTEXT {\r
a9292c13 566 UINT32 RouteString:20;\r
92870c98 567 UINT32 Speed:4;\r
568 UINT32 RsvdZ1:1;\r
569 UINT32 MTT:1;\r
570 UINT32 Hub:1;\r
571 UINT32 ContextEntries:5;\r
572\r
573 UINT32 MaxExitLatency:16;\r
574 UINT32 RootHubPortNum:8;\r
575 UINT32 PortNum:8;\r
576\r
577 UINT32 TTHubSlotId:8;\r
578 UINT32 TTPortNum:8;\r
579 UINT32 TTT:2;\r
580 UINT32 RsvdZ2:4;\r
581 UINT32 InterTarget:10;\r
582\r
583 UINT32 DeviceAddress:8;\r
584 UINT32 RsvdZ3:19;\r
585 UINT32 SlotState:5;\r
586\r
587 UINT32 RsvdZ4;\r
588 UINT32 RsvdZ5;\r
589 UINT32 RsvdZ6;\r
590 UINT32 RsvdZ7;\r
591} SLOT_CONTEXT;\r
592\r
6b4483cd 593typedef struct _SLOT_CONTEXT_64 {\r
594 UINT32 RouteString:20;\r
595 UINT32 Speed:4;\r
596 UINT32 RsvdZ1:1;\r
597 UINT32 MTT:1;\r
598 UINT32 Hub:1;\r
599 UINT32 ContextEntries:5;\r
600\r
601 UINT32 MaxExitLatency:16;\r
602 UINT32 RootHubPortNum:8;\r
603 UINT32 PortNum:8;\r
604\r
605 UINT32 TTHubSlotId:8;\r
606 UINT32 TTPortNum:8;\r
607 UINT32 TTT:2;\r
608 UINT32 RsvdZ2:4;\r
609 UINT32 InterTarget:10;\r
610\r
611 UINT32 DeviceAddress:8;\r
612 UINT32 RsvdZ3:19;\r
613 UINT32 SlotState:5;\r
614\r
615 UINT32 RsvdZ4;\r
616 UINT32 RsvdZ5;\r
617 UINT32 RsvdZ6;\r
618 UINT32 RsvdZ7;\r
619\r
620 UINT32 RsvdZ8;\r
621 UINT32 RsvdZ9;\r
622 UINT32 RsvdZ10;\r
623 UINT32 RsvdZ11;\r
d1102dba 624\r
6b4483cd 625 UINT32 RsvdZ12;\r
626 UINT32 RsvdZ13;\r
627 UINT32 RsvdZ14;\r
628 UINT32 RsvdZ15;\r
629\r
630} SLOT_CONTEXT_64;\r
631\r
632\r
92870c98 633//\r
634// 6.2.3 Endpoint Context\r
635//\r
636typedef struct _ENDPOINT_CONTEXT {\r
637 UINT32 EPState:3;\r
638 UINT32 RsvdZ1:5;\r
639 UINT32 Mult:2;\r
640 UINT32 MaxPStreams:5;\r
641 UINT32 LSA:1;\r
642 UINT32 Interval:8;\r
643 UINT32 RsvdZ2:8;\r
644\r
645 UINT32 RsvdZ3:1;\r
646 UINT32 CErr:2;\r
647 UINT32 EPType:3;\r
648 UINT32 RsvdZ4:1;\r
649 UINT32 HID:1;\r
650 UINT32 MaxBurstSize:8;\r
651 UINT32 MaxPacketSize:16;\r
652\r
653 UINT32 PtrLo;\r
654\r
655 UINT32 PtrHi;\r
656\r
657 UINT32 AverageTRBLength:16;\r
658 UINT32 MaxESITPayload:16;\r
659\r
660 UINT32 RsvdZ5;\r
661 UINT32 RsvdZ6;\r
662 UINT32 RsvdZ7;\r
663} ENDPOINT_CONTEXT;\r
664\r
6b4483cd 665typedef struct _ENDPOINT_CONTEXT_64 {\r
666 UINT32 EPState:3;\r
667 UINT32 RsvdZ1:5;\r
668 UINT32 Mult:2;\r
669 UINT32 MaxPStreams:5;\r
670 UINT32 LSA:1;\r
671 UINT32 Interval:8;\r
672 UINT32 RsvdZ2:8;\r
673\r
674 UINT32 RsvdZ3:1;\r
675 UINT32 CErr:2;\r
676 UINT32 EPType:3;\r
677 UINT32 RsvdZ4:1;\r
678 UINT32 HID:1;\r
679 UINT32 MaxBurstSize:8;\r
680 UINT32 MaxPacketSize:16;\r
681\r
682 UINT32 PtrLo;\r
683\r
684 UINT32 PtrHi;\r
685\r
686 UINT32 AverageTRBLength:16;\r
687 UINT32 MaxESITPayload:16;\r
688\r
689 UINT32 RsvdZ5;\r
690 UINT32 RsvdZ6;\r
691 UINT32 RsvdZ7;\r
d1102dba 692\r
6b4483cd 693 UINT32 RsvdZ8;\r
694 UINT32 RsvdZ9;\r
695 UINT32 RsvdZ10;\r
696 UINT32 RsvdZ11;\r
d1102dba 697\r
6b4483cd 698 UINT32 RsvdZ12;\r
699 UINT32 RsvdZ13;\r
700 UINT32 RsvdZ14;\r
701 UINT32 RsvdZ15;\r
702\r
703} ENDPOINT_CONTEXT_64;\r
704\r
705\r
92870c98 706//\r
707// 6.2.5.1 Input Control Context\r
708//\r
709typedef struct _INPUT_CONTRL_CONTEXT {\r
710 UINT32 Dword1;\r
711 UINT32 Dword2;\r
712 UINT32 RsvdZ1;\r
713 UINT32 RsvdZ2;\r
714 UINT32 RsvdZ3;\r
715 UINT32 RsvdZ4;\r
716 UINT32 RsvdZ5;\r
717 UINT32 RsvdZ6;\r
718} INPUT_CONTRL_CONTEXT;\r
719\r
6b4483cd 720typedef struct _INPUT_CONTRL_CONTEXT_64 {\r
721 UINT32 Dword1;\r
722 UINT32 Dword2;\r
723 UINT32 RsvdZ1;\r
724 UINT32 RsvdZ2;\r
725 UINT32 RsvdZ3;\r
726 UINT32 RsvdZ4;\r
727 UINT32 RsvdZ5;\r
728 UINT32 RsvdZ6;\r
729 UINT32 RsvdZ7;\r
730 UINT32 RsvdZ8;\r
731 UINT32 RsvdZ9;\r
732 UINT32 RsvdZ10;\r
733 UINT32 RsvdZ11;\r
734 UINT32 RsvdZ12;\r
735 UINT32 RsvdZ13;\r
736 UINT32 RsvdZ14;\r
737} INPUT_CONTRL_CONTEXT_64;\r
738\r
92870c98 739//\r
740// 6.2.1 Device Context\r
741//\r
742typedef struct _DEVICE_CONTEXT {\r
743 SLOT_CONTEXT Slot;\r
744 ENDPOINT_CONTEXT EP[31];\r
745} DEVICE_CONTEXT;\r
746\r
6b4483cd 747typedef struct _DEVICE_CONTEXT_64 {\r
748 SLOT_CONTEXT_64 Slot;\r
749 ENDPOINT_CONTEXT_64 EP[31];\r
750} DEVICE_CONTEXT_64;\r
751\r
92870c98 752//\r
753// 6.2.5 Input Context\r
754//\r
755typedef struct _INPUT_CONTEXT {\r
756 INPUT_CONTRL_CONTEXT InputControlContext;\r
757 SLOT_CONTEXT Slot;\r
758 ENDPOINT_CONTEXT EP[31];\r
759} INPUT_CONTEXT;\r
760\r
6b4483cd 761typedef struct _INPUT_CONTEXT_64 {\r
762 INPUT_CONTRL_CONTEXT_64 InputControlContext;\r
763 SLOT_CONTEXT_64 Slot;\r
764 ENDPOINT_CONTEXT_64 EP[31];\r
765} INPUT_CONTEXT_64;\r
766\r
767\r
92870c98 768/**\r
769 Initialize the XHCI host controller for schedule.\r
770\r
a9292c13 771 @param Xhc The XHCI Instance to be initialized.\r
92870c98 772\r
773**/\r
774VOID\r
775XhcInitSched (\r
a9292c13 776 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 777 );\r
778\r
779/**\r
780 Free the resouce allocated at initializing schedule.\r
781\r
a9292c13 782 @param Xhc The XHCI Instance.\r
92870c98 783\r
784**/\r
785VOID\r
786XhcFreeSched (\r
a9292c13 787 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 788 );\r
789\r
790/**\r
791 Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r
792\r
a9292c13 793 @param Xhc The XHCI Instance.\r
92870c98 794 @param Urb The URB to be rung.\r
795\r
796 @retval EFI_SUCCESS Successfully ring the door bell.\r
797\r
798**/\r
799EFI_STATUS\r
800RingIntTransferDoorBell (\r
a9292c13 801 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 802 IN URB *Urb\r
803 );\r
804\r
805/**\r
806 Execute the transfer by polling the URB. This is a synchronous operation.\r
807\r
a9292c13 808 @param Xhc The XHCI Instance.\r
92870c98 809 @param CmdTransfer The executed URB is for cmd transfer or not.\r
810 @param Urb The URB to execute.\r
a9292c13 811 @param Timeout The time to wait before abort, in millisecond.\r
92870c98 812\r
813 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
814 @return EFI_TIMEOUT The transfer failed due to time out.\r
815 @return EFI_SUCCESS The transfer finished OK.\r
816\r
817**/\r
818EFI_STATUS\r
819XhcExecTransfer (\r
a9292c13 820 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 821 IN BOOLEAN CmdTransfer,\r
822 IN URB *Urb,\r
a9292c13 823 IN UINTN Timeout\r
92870c98 824 );\r
825\r
826/**\r
827 Delete a single asynchronous interrupt transfer for\r
828 the device and endpoint.\r
829\r
a9292c13 830 @param Xhc The XHCI Instance.\r
6b4483cd 831 @param BusAddr The logical device address assigned by UsbBus driver.\r
92870c98 832 @param EpNum The endpoint of the target.\r
833\r
834 @retval EFI_SUCCESS An asynchronous transfer is removed.\r
835 @retval EFI_NOT_FOUND No transfer for the device is found.\r
836\r
837**/\r
838EFI_STATUS\r
839XhciDelAsyncIntTransfer (\r
a9292c13 840 IN USB_XHCI_INSTANCE *Xhc,\r
6b4483cd 841 IN UINT8 BusAddr,\r
92870c98 842 IN UINT8 EpNum\r
843 );\r
844\r
845/**\r
846 Remove all the asynchronous interrupt transfers.\r
847\r
a9292c13 848 @param Xhc The XHCI Instance.\r
92870c98 849\r
850**/\r
851VOID\r
852XhciDelAllAsyncIntTransfers (\r
a9292c13 853 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 854 );\r
855\r
6681582d
SZ		 856/**\r
857 Insert a single asynchronous interrupt transfer for\r
858 the device and endpoint.\r
859\r
860 @param Xhc The XHCI Instance\r
861 @param BusAddr The logical device address assigned by UsbBus driver\r
862 @param EpAddr Endpoint addrress\r
863 @param DevSpeed The device speed\r
864 @param MaxPacket The max packet length of the endpoint\r
865 @param DataLen The length of data buffer\r
866 @param Callback The function to call when data is transferred\r
867 @param Context The context to the callback\r
868\r
869 @return Created URB or NULL\r
870\r
871**/\r
872URB *\r
873XhciInsertAsyncIntTransfer (\r
874 IN USB_XHCI_INSTANCE *Xhc,\r
875 IN UINT8 BusAddr,\r
876 IN UINT8 EpAddr,\r
877 IN UINT8 DevSpeed,\r
878 IN UINTN MaxPacket,\r
879 IN UINTN DataLen,\r
880 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
881 IN VOID *Context\r
882 );\r
883\r
92870c98 884/**\r
885 Set Bios Ownership\r
886\r
a9292c13 887 @param Xhc The XHCI Instance.\r
92870c98 888\r
889**/\r
890VOID\r
891XhcSetBiosOwnership (\r
a9292c13 892 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 893 );\r
894\r
895/**\r
896 Clear Bios Ownership\r
897\r
a9292c13 898 @param Xhc The XHCI Instance.\r
92870c98 899\r
900**/\r
901VOID\r
902XhcClearBiosOwnership (\r
a9292c13 903 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 904 );\r
905\r
92870c98 906/**\r
907 Find out the slot id according to the device's route string.\r
908\r
a9292c13 909 @param Xhc The XHCI Instance.\r
910 @param RouteString The route string described the device location.\r
92870c98 911\r
912 @return The slot id used by the device.\r
913\r
914**/\r
915UINT8\r
916EFIAPI\r
917XhcRouteStringToSlotId (\r
a9292c13 918 IN USB_XHCI_INSTANCE *Xhc,\r
919 IN USB_DEV_ROUTE RouteString\r
92870c98 920 );\r
921\r
922/**\r
923 Calculate the device context index by endpoint address and direction.\r
924\r
925 @param EpAddr The target endpoint number.\r
926 @param Direction The direction of the target endpoint.\r
927\r
928 @return The device context index of endpoint.\r
929\r
930**/\r
931UINT8\r
932XhcEndpointToDci (\r
933 IN UINT8 EpAddr,\r
934 IN UINT8 Direction\r
935 );\r
936\r
937/**\r
938 Ring the door bell to notify XHCI there is a transaction to be executed.\r
939\r
a9292c13 940 @param Xhc The XHCI Instance.\r
92870c98 941 @param SlotId The slot id of the target device.\r
942 @param Dci The device context index of the target slot or endpoint.\r
943\r
944 @retval EFI_SUCCESS Successfully ring the door bell.\r
945\r
946**/\r
947EFI_STATUS\r
948EFIAPI\r
949XhcRingDoorBell (\r
a9292c13 950 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 951 IN UINT8 SlotId,\r
952 IN UINT8 Dci\r
953 );\r
954\r
955/**\r
956 Interrupt transfer periodic check handler.\r
957\r
958 @param Event Interrupt event.\r
a9292c13 959 @param Context Pointer to USB_XHCI_INSTANCE.\r
92870c98 960\r
961**/\r
962VOID\r
963EFIAPI\r
964XhcMonitorAsyncRequests (\r
965 IN EFI_EVENT Event,\r
966 IN VOID *Context\r
967 );\r
968\r
969/**\r
970 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r
971\r
a9292c13 972 @param Xhc The XHCI Instance.\r
92870c98 973 @param ParentRouteChart The route string pointed to the parent device if it exists.\r
974 @param Port The port to be polled.\r
975 @param PortState The port state.\r
976\r
977 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r
978 @retval Others Should not appear.\r
979\r
980**/\r
981EFI_STATUS\r
982EFIAPI\r
983XhcPollPortStatusChange (\r
a9292c13 984 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 985 IN USB_DEV_ROUTE ParentRouteChart,\r
986 IN UINT8 Port,\r
987 IN EFI_USB_PORT_STATUS *PortState\r
988 );\r
989\r
990/**\r
991 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
992\r
a9292c13 993 @param Xhc The XHCI Instance.\r
92870c98 994 @param SlotId The slot id to be configured.\r
995 @param PortNum The total number of downstream port supported by the hub.\r
996 @param TTT The TT think time of the hub device.\r
997 @param MTT The multi-TT of the hub device.\r
998\r
999 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
1000\r
1001**/\r
1002EFI_STATUS\r
1003XhcConfigHubContext (\r
a9292c13 1004 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1005 IN UINT8 SlotId,\r
1006 IN UINT8 PortNum,\r
1007 IN UINT8 TTT,\r
1008 IN UINT8 MTT\r
1009 );\r
1010\r
6b4483cd 1011\r
1012/**\r
1013 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
1014\r
1015 @param Xhc The XHCI Instance.\r
1016 @param SlotId The slot id to be configured.\r
1017 @param PortNum The total number of downstream port supported by the hub.\r
1018 @param TTT The TT think time of the hub device.\r
1019 @param MTT The multi-TT of the hub device.\r
1020\r
1021 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
1022\r
1023**/\r
1024EFI_STATUS\r
1025XhcConfigHubContext64 (\r
1026 IN USB_XHCI_INSTANCE *Xhc,\r
1027 IN UINT8 SlotId,\r
1028 IN UINT8 PortNum,\r
1029 IN UINT8 TTT,\r
1030 IN UINT8 MTT\r
1031 );\r
1032\r
1033\r
92870c98 1034/**\r
1035 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
1036\r
a9292c13 1037 @param Xhc The XHCI Instance.\r
92870c98 1038 @param SlotId The slot id to be configured.\r
1039 @param DeviceSpeed The device's speed.\r
1040 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1041\r
1042 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
1043\r
1044**/\r
1045EFI_STATUS\r
1046EFIAPI\r
1047XhcSetConfigCmd (\r
a9292c13 1048 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1049 IN UINT8 SlotId,\r
1050 IN UINT8 DeviceSpeed,\r
1051 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
1052 );\r
1053\r
6b4483cd 1054\r
1055/**\r
1056 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
1057\r
1058 @param Xhc The XHCI Instance.\r
1059 @param SlotId The slot id to be configured.\r
1060 @param DeviceSpeed The device's speed.\r
1061 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1062\r
1063 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
1064\r
1065**/\r
1066EFI_STATUS\r
1067EFIAPI\r
1068XhcSetConfigCmd64 (\r
1069 IN USB_XHCI_INSTANCE *Xhc,\r
1070 IN UINT8 SlotId,\r
1071 IN UINT8 DeviceSpeed,\r
1072 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
1073 );\r
1074\r
e1f2dfec
SZ		 1075/**\r
1076 Set interface through XHCI's Configure_Endpoint cmd.\r
1077\r
1078 @param Xhc The XHCI Instance.\r
1079 @param SlotId The slot id to be configured.\r
1080 @param DeviceSpeed The device's speed.\r
1081 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1082 @param Request USB device request to send.\r
1083\r
1084 @retval EFI_SUCCESS Successfully set interface.\r
1085\r
1086**/\r
1087EFI_STATUS\r
1088EFIAPI\r
1089XhcSetInterface (\r
1090 IN USB_XHCI_INSTANCE *Xhc,\r
1091 IN UINT8 SlotId,\r
1092 IN UINT8 DeviceSpeed,\r
1093 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
1094 IN EFI_USB_DEVICE_REQUEST *Request\r
1095 );\r
1096\r
1097/**\r
1098 Set interface through XHCI's Configure_Endpoint cmd.\r
1099\r
1100 @param Xhc The XHCI Instance.\r
1101 @param SlotId The slot id to be configured.\r
1102 @param DeviceSpeed The device's speed.\r
1103 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1104 @param Request USB device request to send.\r
1105\r
1106 @retval EFI_SUCCESS Successfully set interface.\r
1107\r
1108**/\r
1109EFI_STATUS\r
1110EFIAPI\r
1111XhcSetInterface64 (\r
1112 IN USB_XHCI_INSTANCE *Xhc,\r
1113 IN UINT8 SlotId,\r
1114 IN UINT8 DeviceSpeed,\r
1115 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
1116 IN EFI_USB_DEVICE_REQUEST *Request\r
1117 );\r
6b4483cd 1118\r
92870c98 1119/**\r
1120 Find out the actual device address according to the requested device address from UsbBus.\r
1121\r
a9292c13 1122 @param Xhc The XHCI Instance.\r
1123 @param BusDevAddr The requested device address by UsbBus upper driver.\r
92870c98 1124\r
1125 @return The actual device address assigned to the device.\r
1126\r
1127**/\r
1128UINT8\r
1129EFIAPI\r
1130XhcBusDevAddrToSlotId (\r
a9292c13 1131 IN USB_XHCI_INSTANCE *Xhc,\r
1132 IN UINT8 BusDevAddr\r
92870c98 1133 );\r
1134\r
1135/**\r
1136 Assign and initialize the device slot for a new device.\r
1137\r
a9292c13 1138 @param Xhc The XHCI Instance.\r
92870c98 1139 @param ParentRouteChart The route string pointed to the parent device.\r
1140 @param ParentPort The port at which the device is located.\r
1141 @param RouteChart The route string pointed to the device.\r
1142 @param DeviceSpeed The device speed.\r
1143\r
1144 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1145\r
1146**/\r
1147EFI_STATUS\r
1148EFIAPI\r
1149XhcInitializeDeviceSlot (\r
a9292c13 1150 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1151 IN USB_DEV_ROUTE ParentRouteChart,\r
1152 IN UINT16 ParentPort,\r
1153 IN USB_DEV_ROUTE RouteChart,\r
1154 IN UINT8 DeviceSpeed\r
1155 );\r
1156\r
6b4483cd 1157/**\r
1158 Assign and initialize the device slot for a new device.\r
1159\r
1160 @param Xhc The XHCI Instance.\r
1161 @param ParentRouteChart The route string pointed to the parent device.\r
1162 @param ParentPort The port at which the device is located.\r
1163 @param RouteChart The route string pointed to the device.\r
1164 @param DeviceSpeed The device speed.\r
1165\r
1166 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1167\r
1168**/\r
1169EFI_STATUS\r
1170EFIAPI\r
1171XhcInitializeDeviceSlot64 (\r
1172 IN USB_XHCI_INSTANCE *Xhc,\r
1173 IN USB_DEV_ROUTE ParentRouteChart,\r
1174 IN UINT16 ParentPort,\r
1175 IN USB_DEV_ROUTE RouteChart,\r
1176 IN UINT8 DeviceSpeed\r
1177 );\r
1178\r
92870c98 1179/**\r
1180 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
1181\r
a9292c13 1182 @param Xhc The XHCI Instance.\r
92870c98 1183 @param SlotId The slot id to be evaluated.\r
1184 @param MaxPacketSize The max packet size supported by the device control transfer.\r
1185\r
1186 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
1187\r
1188**/\r
1189EFI_STATUS\r
1190EFIAPI\r
1191XhcEvaluateContext (\r
a9292c13 1192 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1193 IN UINT8 SlotId,\r
1194 IN UINT32 MaxPacketSize\r
1195 );\r
1196\r
6b4483cd 1197\r
1198/**\r
1199 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
1200\r
1201 @param Xhc The XHCI Instance.\r
1202 @param SlotId The slot id to be evaluated.\r
1203 @param MaxPacketSize The max packet size supported by the device control transfer.\r
1204\r
1205 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
1206\r
1207**/\r
1208EFI_STATUS\r
1209EFIAPI\r
1210XhcEvaluateContext64 (\r
1211 IN USB_XHCI_INSTANCE *Xhc,\r
1212 IN UINT8 SlotId,\r
1213 IN UINT32 MaxPacketSize\r
1214 );\r
1215\r
1216\r
92870c98 1217/**\r
1218 Disable the specified device slot.\r
1219\r
a9292c13 1220 @param Xhc The XHCI Instance.\r
92870c98 1221 @param SlotId The slot id to be disabled.\r
1222\r
1223 @retval EFI_SUCCESS Successfully disable the device slot.\r
1224\r
1225**/\r
1226EFI_STATUS\r
1227EFIAPI\r
1228XhcDisableSlotCmd (\r
a9292c13 1229 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1230 IN UINT8 SlotId\r
1231 );\r
1232\r
6b4483cd 1233\r
1234/**\r
1235 Disable the specified device slot.\r
1236\r
1237 @param Xhc The XHCI Instance.\r
1238 @param SlotId The slot id to be disabled.\r
1239\r
1240 @retval EFI_SUCCESS Successfully disable the device slot.\r
1241\r
1242**/\r
1243EFI_STATUS\r
1244EFIAPI\r
1245XhcDisableSlotCmd64 (\r
1246 IN USB_XHCI_INSTANCE *Xhc,\r
1247 IN UINT8 SlotId\r
1248 );\r
1249\r
1250\r
92870c98 1251/**\r
1252 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
1253\r
a9292c13 1254 @param Xhc The XHCI Instance.\r
92870c98 1255 @param TrsRing The transfer ring to sync.\r
1256\r
1257 @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r
1258\r
1259**/\r
1260EFI_STATUS\r
1261EFIAPI\r
1262XhcSyncTrsRing (\r
a9292c13 1263 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1264 TRANSFER_RING *TrsRing\r
1265 );\r
1266\r
1267/**\r
1268 Synchronize the specified event ring to update the enqueue and dequeue pointer.\r
1269\r
a9292c13 1270 @param Xhc The XHCI Instance.\r
92870c98 1271 @param EvtRing The event ring to sync.\r
1272\r
1273 @retval EFI_SUCCESS The event ring is synchronized successfully.\r
1274\r
1275**/\r
1276EFI_STATUS\r
1277EFIAPI\r
1278XhcSyncEventRing (\r
a9292c13 1279 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1280 EVENT_RING *EvtRing\r
1281 );\r
1282\r
1283/**\r
1284 Check if there is a new generated event.\r
1285\r
a9292c13 1286 @param Xhc The XHCI Instance.\r
92870c98 1287 @param EvtRing The event ring to check.\r
1288 @param NewEvtTrb The new event TRB found.\r
1289\r
1290 @retval EFI_SUCCESS Found a new event TRB at the event ring.\r
1291 @retval EFI_NOT_READY The event ring has no new event.\r
1292\r
1293**/\r
1294EFI_STATUS\r
1295EFIAPI\r
1296XhcCheckNewEvent (\r
a9292c13 1297 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1298 IN EVENT_RING *EvtRing,\r
a9292c13 1299 OUT TRB_TEMPLATE **NewEvtTrb\r
92870c98 1300 );\r
1301\r
1302/**\r
1303 Create XHCI transfer ring.\r
1304\r
a9292c13 1305 @param Xhc The XHCI Instance.\r
92870c98 1306 @param TrbNum The number of TRB in the ring.\r
1307 @param TransferRing The created transfer ring.\r
1308\r
1309**/\r
1310VOID\r
1311CreateTransferRing (\r
a9292c13 1312 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1313 IN UINTN TrbNum,\r
1314 OUT TRANSFER_RING *TransferRing\r
1315 );\r
1316\r
1317/**\r
1318 Create XHCI event ring.\r
1319\r
a9292c13 1320 @param Xhc The XHCI Instance.\r
92870c98 1321 @param EventRing The created event ring.\r
1322\r
1323**/\r
1324VOID\r
1325CreateEventRing (\r
a9292c13 1326 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1327 OUT EVENT_RING *EventRing\r
1328 );\r
1329\r
1330/**\r
1331 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r
1332 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r
1333 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r
1334 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r
1335 Stopped to the Running state.\r
1336\r
a9292c13 1337 @param Xhc The XHCI Instance.\r
92870c98 1338 @param Urb The urb which makes the endpoint halted.\r
1339\r
1340 @retval EFI_SUCCESS The recovery is successful.\r
1341 @retval Others Failed to recovery halted endpoint.\r
1342\r
1343**/\r
1344EFI_STATUS\r
1345EFIAPI\r
1346XhcRecoverHaltedEndpoint (\r
a9292c13 1347 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1348 IN URB *Urb\r
1349 );\r
1350\r
12e6c738
FT		 1351/**\r
1352 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r
1353 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r
1354 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r
1355 state.\r
1356\r
1357 @param Xhc The XHCI Instance.\r
1358 @param Urb The urb which doesn't get completed in a specified timeout range.\r
1359\r
1360 @retval EFI_SUCCESS The dequeuing of the TDs is successful.\r
1361 @retval Others Failed to stop the endpoint and dequeue the TDs.\r
1362\r
1363**/\r
1364EFI_STATUS\r
1365EFIAPI\r
1366XhcDequeueTrbFromEndpoint (\r
1367 IN USB_XHCI_INSTANCE *Xhc,\r
1368 IN URB *Urb\r
1369 );\r
1370\r
1371/**\r
1372 Stop endpoint through XHCI's Stop_Endpoint cmd.\r
1373\r
1374 @param Xhc The XHCI Instance.\r
1375 @param SlotId The slot id to be configured.\r
1376 @param Dci The device context index of endpoint.\r
49be9c3c 1377 @param PendingUrb The pending URB to check completion status when stopping the end point.\r
12e6c738
FT		 1378\r
1379 @retval EFI_SUCCESS Stop endpoint successfully.\r
1380 @retval Others Failed to stop endpoint.\r
1381\r
1382**/\r
1383EFI_STATUS\r
1384EFIAPI\r
1385XhcStopEndpoint (\r
1386 IN USB_XHCI_INSTANCE *Xhc,\r
1387 IN UINT8 SlotId,\r
49be9c3c
RN		 1388 IN UINT8 Dci,\r
1389 IN URB *PendingUrb OPTIONAL\r
12e6c738
FT		 1390 );\r
1391\r
1392/**\r
1393 Reset endpoint through XHCI's Reset_Endpoint cmd.\r
1394\r
1395 @param Xhc The XHCI Instance.\r
1396 @param SlotId The slot id to be configured.\r
1397 @param Dci The device context index of endpoint.\r
1398\r
1399 @retval EFI_SUCCESS Reset endpoint successfully.\r
1400 @retval Others Failed to reset endpoint.\r
1401\r
1402**/\r
1403EFI_STATUS\r
1404EFIAPI\r
1405XhcResetEndpoint (\r
1406 IN USB_XHCI_INSTANCE *Xhc,\r
1407 IN UINT8 SlotId,\r
1408 IN UINT8 Dci\r
1409 );\r
1410\r
1411/**\r
1412 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r
1413\r
1414 @param Xhc The XHCI Instance.\r
1415 @param SlotId The slot id to be configured.\r
1416 @param Dci The device context index of endpoint.\r
1417 @param Urb The dequeue pointer of the transfer ring specified\r
1418 by the urb to be updated.\r
1419\r
1420 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.\r
1421 @retval Others Failed to set transfer ring dequeue pointer.\r
1422\r
1423**/\r
1424EFI_STATUS\r
1425EFIAPI\r
1426XhcSetTrDequeuePointer (\r
1427 IN USB_XHCI_INSTANCE *Xhc,\r
1428 IN UINT8 SlotId,\r
1429 IN UINT8 Dci,\r
1430 IN URB *Urb\r
1431 );\r
1432\r
92870c98 1433/**\r
1434 Create a new URB for a new transaction.\r
1435\r
77792099
SZ		 1436 @param Xhc The XHCI Instance\r
1437 @param BusAddr The logical device address assigned by UsbBus driver\r
1438 @param EpAddr Endpoint addrress\r
1439 @param DevSpeed The device speed\r
1440 @param MaxPacket The max packet length of the endpoint\r
1441 @param Type The transaction type\r
1442 @param Request The standard USB request for control transfer\r
1443 @param AllocateCommonBuffer Indicate whether need to allocate common buffer for data transfer\r
1444 @param Data The user data to transfer, NULL if AllocateCommonBuffer is TRUE\r
1445 @param DataLen The length of data buffer\r
1446 @param Callback The function to call when data is transferred\r
1447 @param Context The context to the callback\r
92870c98 1448\r
1449 @return Created URB or NULL\r
1450\r
1451**/\r
1452URB*\r
1453XhcCreateUrb (\r
a9292c13 1454 IN USB_XHCI_INSTANCE *Xhc,\r
77792099 1455 IN UINT8 BusAddr,\r
92870c98 1456 IN UINT8 EpAddr,\r
1457 IN UINT8 DevSpeed,\r
1458 IN UINTN MaxPacket,\r
1459 IN UINTN Type,\r
1460 IN EFI_USB_DEVICE_REQUEST *Request,\r
77792099 1461 IN BOOLEAN AllocateCommonBuffer,\r
92870c98 1462 IN VOID *Data,\r
1463 IN UINTN DataLen,\r
1464 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
1465 IN VOID *Context\r
1466 );\r
1467\r
1847ed0b
EL		 1468/**\r
1469 Free an allocated URB.\r
1470\r
1471 @param Xhc The XHCI device.\r
1472 @param Urb The URB to free.\r
1473\r
1474**/\r
1475VOID\r
1476XhcFreeUrb (\r
1477 IN USB_XHCI_INSTANCE *Xhc,\r
1478 IN URB *Urb\r
1479 );\r
1480\r
92870c98 1481/**\r
1482 Create a transfer TRB.\r
1483\r
a9292c13 1484 @param Xhc The XHCI Instance\r
92870c98 1485 @param Urb The urb used to construct the transfer TRB.\r
1486\r
1487 @return Created TRB or NULL\r
1488\r
1489**/\r
1490EFI_STATUS\r
1491XhcCreateTransferTrb (\r
a9292c13 1492 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1493 IN URB *Urb\r
1494 );\r
1495\r
1496#endif\r
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