MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe: Add support for PCD PcdPteMemoryEn...
[mirror_edk2.git] / MdeModulePkg / Universal / Acpi / BootScriptExecutorDxe / X64 / SetIdtEntry.c
CommitLineData
be46cd5f 1/** @file\r
2 Set a IDT entry for debug purpose\r
3\r
4 Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform\r
5\r
c6368abc 6Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
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7Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
8\r
be46cd5f 9\r
10This program and the accompanying materials\r
11are licensed and made available under the terms and conditions of the BSD License\r
12which accompanies this distribution. The full text of the license may be found at\r
13http://opensource.org/licenses/bsd-license.php\r
14\r
15THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18**/\r
19#include "ScriptExecute.h"\r
d0bf5623 20\r
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21//\r
22// 8 extra pages for PF handler.\r
23//\r
24#define EXTRA_PAGE_TABLE_PAGES 8\r
25\r
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26#define IA32_PG_P BIT0\r
27#define IA32_PG_RW BIT1\r
28#define IA32_PG_PS BIT7\r
29\r
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30UINT64 mPhyMask;\r
31VOID *mOriginalHandler;\r
32UINTN mPageFaultBuffer;\r
33UINTN mPageFaultIndex = 0;\r
34//\r
35// Store the uplink information for each page being used.\r
36//\r
37UINT64 *mPageFaultUplink[EXTRA_PAGE_TABLE_PAGES];\r
d0bf5623 38\r
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39/**\r
40 Page fault handler.\r
41\r
42**/\r
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43VOID\r
44EFIAPI\r
45PageFaultHandlerHook (\r
46 VOID\r
47 );\r
48\r
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49/**\r
50 Hook IDT with our page fault handler so that the on-demand paging works on page fault.\r
51\r
52 @param IdtEntry a pointer to IDT entry\r
53\r
54**/\r
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55VOID\r
56HookPageFaultHandler (\r
68cc1ba3 57 IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry\r
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58 )\r
59{\r
60 UINT32 RegEax;\r
59cc677c 61 UINT8 PhysicalAddressBits;\r
73f0127f 62 UINTN PageFaultHandlerHookAddress;\r
d0bf5623 63\r
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64 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
65 if (RegEax >= 0x80000008) {\r
66 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
67 PhysicalAddressBits = (UINT8) RegEax;\r
68 } else {\r
69 PhysicalAddressBits = 36;\r
d0bf5623 70 }\r
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71 mPhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
72 mPhyMask &= (1ull << 48) - SIZE_4KB;\r
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73\r
74 //\r
75 // Set Page Fault entry to catch >4G access\r
76 //\r
73f0127f 77 PageFaultHandlerHookAddress = (UINTN)PageFaultHandlerHook;\r
68cc1ba3 78 mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));\r
73f0127f 79 IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;\r
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SZ
80 IdtEntry->Bits.Selector = (UINT16)AsmReadCs ();\r
81 IdtEntry->Bits.Reserved_0 = 0;\r
82 IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
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83 IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
84 IdtEntry->Bits.OffsetUpper = (UINT32)(PageFaultHandlerHookAddress >> 32);\r
68cc1ba3 85 IdtEntry->Bits.Reserved_1 = 0;\r
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86\r
87 if (mPage1GSupport) {\r
c6368abc 88 mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);\r
d0bf5623 89 }else {\r
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90 mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);\r
91 }\r
92 ZeroMem (mPageFaultUplink, sizeof (mPageFaultUplink));\r
93}\r
94\r
95/**\r
96 The function will check if current waking vector is long mode.\r
97\r
98 @param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT\r
99\r
100 @retval TRUE Current context need long mode waking vector.\r
101 @retval FALSE Current context need not long mode waking vector.\r
102**/\r
103BOOLEAN\r
104IsLongModeWakingVector (\r
105 IN ACPI_S3_CONTEXT *AcpiS3Context\r
106 )\r
107{\r
108 EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs;\r
109\r
110 Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));\r
111 if ((Facs == NULL) ||\r
112 (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||\r
113 ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {\r
114 // Something wrong with FACS\r
115 return FALSE;\r
116 }\r
117 if (Facs->XFirmwareWakingVector != 0) {\r
118 if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&\r
119 ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&\r
120 ((Facs->Flags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {\r
121 // Both BIOS and OS wants 64bit vector\r
122 if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
123 return TRUE;\r
124 }\r
125 }\r
d0bf5623 126 }\r
c6368abc 127 return FALSE;\r
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128}\r
129\r
be46cd5f 130/**\r
131 Set a IDT entry for interrupt vector 3 for debug purpose.\r
132\r
133 @param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT\r
134\r
135**/\r
136VOID\r
137SetIdtEntry (\r
138 IN ACPI_S3_CONTEXT *AcpiS3Context\r
139 )\r
140{\r
68cc1ba3 141 IA32_IDT_GATE_DESCRIPTOR *IdtEntry;\r
be46cd5f 142 IA32_DESCRIPTOR *IdtDescriptor;\r
143 UINTN S3DebugBuffer;\r
57f360f2 144 EFI_STATUS Status;\r
be46cd5f 145\r
146 //\r
147 // Restore IDT for debug\r
148 //\r
149 IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
1e172d6b 150 AsmWriteIdtr (IdtDescriptor);\r
151\r
152 //\r
153 // Setup the default CPU exception handlers\r
154 //\r
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155 Status = InitializeCpuExceptionHandlers (NULL);\r
156 ASSERT_EFI_ERROR (Status);\r
1e172d6b 157\r
f4a25e81 158 DEBUG_CODE (\r
159 //\r
160 // Update IDT entry INT3 if the instruction is valid in it\r
161 //\r
162 S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);\r
163 if (*(UINTN *)S3DebugBuffer != (UINTN) -1) {\r
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164 IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
165 IdtEntry->Bits.OffsetLow = (UINT16)S3DebugBuffer;\r
166 IdtEntry->Bits.Selector = (UINT16)AsmReadCs ();\r
167 IdtEntry->Bits.Reserved_0 = 0;\r
168 IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
169 IdtEntry->Bits.OffsetHigh = (UINT16)(S3DebugBuffer >> 16);\r
170 IdtEntry->Bits.OffsetUpper = (UINT32)(S3DebugBuffer >> 32);\r
171 IdtEntry->Bits.Reserved_1 = 0;\r
f4a25e81 172 }\r
173 );\r
be46cd5f 174\r
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175 //\r
176 // If both BIOS and OS wants long mode waking vector,\r
177 // S3ResumePei should have established 1:1 Virtual to Physical identity mapping page table,\r
178 // no need to hook page fault handler.\r
179 //\r
180 if (!IsLongModeWakingVector (AcpiS3Context)) {\r
181 IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
182 HookPageFaultHandler (IdtEntry);\r
183 }\r
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184}\r
185\r
54e27ada 186/**\r
c6368abc 187 Acquire page for page fault.\r
54e27ada 188\r
c6368abc 189 @param[in, out] Uplink Pointer to up page table entry.\r
54e27ada 190\r
54e27ada 191**/\r
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192VOID\r
193AcquirePage (\r
194 IN OUT UINT64 *Uplink\r
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195 )\r
196{\r
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197 UINTN Address;\r
198\r
199 Address = mPageFaultBuffer + EFI_PAGES_TO_SIZE (mPageFaultIndex);\r
200 ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));\r
201\r
202 //\r
203 // Cut the previous uplink if it exists and wasn't overwritten.\r
204 //\r
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205 if ((mPageFaultUplink[mPageFaultIndex] != NULL) &&\r
206 ((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) == Address)) {\r
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207 *mPageFaultUplink[mPageFaultIndex] = 0;\r
208 }\r
209\r
210 //\r
211 // Link & Record the current uplink.\r
212 //\r
ab1a5a58 213 *Uplink = Address | mAddressEncMask | IA32_PG_P | IA32_PG_RW;\r
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214 mPageFaultUplink[mPageFaultIndex] = Uplink;\r
215\r
216 mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r
be46cd5f 217}\r
218\r
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219/**\r
220 The page fault handler that on-demand read >4G memory/MMIO.\r
221 \r
222 @retval TRUE The page fault is correctly handled.\r
223 @retval FALSE The page fault is not handled and is passed through to original handler.\r
224\r
225**/\r
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226BOOLEAN\r
227EFIAPI\r
228PageFaultHandler (\r
229 VOID\r
230 )\r
231{\r
232 UINT64 *PageTable;\r
233 UINT64 PFAddress;\r
234 UINTN PTIndex;\r
235\r
236 PFAddress = AsmReadCr2 ();\r
237 DEBUG ((EFI_D_ERROR, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r
238\r
239 if (PFAddress >= mPhyMask + SIZE_4KB) {\r
240 return FALSE;\r
241 }\r
242 PFAddress &= mPhyMask;\r
243\r
244 PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);\r
245\r
246 PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
247 // PML4E\r
248 if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
c6368abc 249 AcquirePage (&PageTable[PTIndex]);\r
d0bf5623 250 }\r
ab1a5a58 251 PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
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252 PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
253 // PDPTE\r
254 if (mPage1GSupport) {\r
ab1a5a58 255 PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
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256 } else {\r
257 if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
c6368abc 258 AcquirePage (&PageTable[PTIndex]);\r
d0bf5623 259 }\r
ab1a5a58 260 PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
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261 PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
262 // PD\r
ab1a5a58 263 PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
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264 }\r
265\r
266 return TRUE;\r
267}\r