# depends on any PEI or DXE service.\r
#\r
# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials are\r
# licensed and made available under the terms and conditions of the BSD License\r
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES\r
gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfilePropertyMask ## CONSUMES\r
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ## CONSUMES\r
\r
[Depex]\r
gEfiLockBoxProtocolGuid\r
in the entry point. The functionality is to interpret and restore the S3 boot script\r
\r
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
};\r
\r
BOOLEAN mPage1GSupport = FALSE;\r
+UINT64 mAddressEncMask = 0;\r
\r
/**\r
Entry function of Boot script exector. This function will be executed in\r
return EFI_UNSUPPORTED;\r
}\r
\r
+ //\r
+ // Make sure AddressEncMask is contained to smallest supported address field.\r
+ //\r
+ mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
+\r
//\r
// Test if the gEfiCallerIdGuid of this image is already installed. if not, the entry\r
// point is loaded by DXE code which is the first time loaded. or else, it is already\r
in the entry point. The functionality is to interpret and restore the S3 boot script \r
\r
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
\r
#include <Protocol/DxeSmmReadyToLock.h>\r
#include <IndustryStandard/Acpi.h>\r
+\r
+#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
+\r
/**\r
a ASM function to transfer control to OS.\r
\r
extern UINT32 AsmFixAddress16;\r
extern UINT32 AsmJmpAddr32;\r
extern BOOLEAN mPage1GSupport;\r
+extern UINT64 mAddressEncMask;\r
\r
#endif //_BOOT_SCRIPT_EXECUTOR_H_\r
Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform\r
\r
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
//\r
// Cut the previous uplink if it exists and wasn't overwritten.\r
//\r
- if ((mPageFaultUplink[mPageFaultIndex] != NULL) && ((*mPageFaultUplink[mPageFaultIndex] & mPhyMask) == Address)) {\r
+ if ((mPageFaultUplink[mPageFaultIndex] != NULL) &&\r
+ ((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) == Address)) {\r
*mPageFaultUplink[mPageFaultIndex] = 0;\r
}\r
\r
//\r
// Link & Record the current uplink.\r
//\r
- *Uplink = Address | IA32_PG_P | IA32_PG_RW;\r
+ *Uplink = Address | mAddressEncMask | IA32_PG_P | IA32_PG_RW;\r
mPageFaultUplink[mPageFaultIndex] = Uplink;\r
\r
mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
AcquirePage (&PageTable[PTIndex]);\r
}\r
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);\r
+ PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
// PDPTE\r
if (mPage1GSupport) {\r
- PageTable[PTIndex] = (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
+ PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
} else {\r
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
AcquirePage (&PageTable[PTIndex]);\r
}\r
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);\r
+ PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
// PD\r
- PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
+ PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
}\r
\r
return TRUE;\r