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1. added functions header for MACROS in PCI22.h.
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci22.h
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a7ed1e2e 1/** @file\r
2 Support for PCI 2.2 standard.\r
3\r
bc14bdb3 4 This file includes the definitions in the following specifications,\r
427987f5 5 PCI Local Bus Specification, 2.2\r
6 PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
bc14bdb3 7 PC Card Standard, 8.0\r
8\r
9 Copyright (c) 2006 - 2008, Intel Corporation \r
a7ed1e2e 10 All rights reserved. This program and the accompanying materials \r
11 are licensed and made available under the terms and conditions of the BSD License \r
12 which accompanies this distribution. The full text of the license may be found at \r
13 http://opensource.org/licenses/bsd-license.php \r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
17\r
a7ed1e2e 18**/\r
19\r
42eedea9 20#ifndef _PCI22_H_\r
21#define _PCI22_H_\r
a7ed1e2e 22\r
23#define PCI_MAX_SEGMENT 0\r
a7ed1e2e 24#define PCI_MAX_BUS 255\r
a7ed1e2e 25#define PCI_MAX_DEVICE 31\r
26#define PCI_MAX_FUNC 7\r
27\r
766f4bc1 28#pragma pack(1)\r
427987f5 29\r
30///\r
31/// Common header region in PCI Configuration Space\r
32/// Section 6.1, PCI Local Bus Specification, 2.2\r
33///\r
a7ed1e2e 34typedef struct {\r
35 UINT16 VendorId;\r
36 UINT16 DeviceId;\r
37 UINT16 Command;\r
38 UINT16 Status;\r
39 UINT8 RevisionID;\r
40 UINT8 ClassCode[3];\r
41 UINT8 CacheLineSize;\r
42 UINT8 LatencyTimer;\r
43 UINT8 HeaderType;\r
44 UINT8 BIST;\r
45} PCI_DEVICE_INDEPENDENT_REGION;\r
46\r
427987f5 47///\r
48/// PCI Device header region in PCI Configuration Space\r
49/// Section 6.1, PCI Local Bus Specification, 2.2\r
50///\r
a7ed1e2e 51typedef struct {\r
52 UINT32 Bar[6];\r
53 UINT32 CISPtr;\r
54 UINT16 SubsystemVendorID;\r
55 UINT16 SubsystemID;\r
56 UINT32 ExpansionRomBar;\r
57 UINT8 CapabilityPtr;\r
58 UINT8 Reserved1[3];\r
59 UINT32 Reserved2;\r
60 UINT8 InterruptLine;\r
61 UINT8 InterruptPin;\r
62 UINT8 MinGnt;\r
63 UINT8 MaxLat;\r
64} PCI_DEVICE_HEADER_TYPE_REGION;\r
65\r
427987f5 66///\r
67/// PCI Device Configuration Space\r
68/// Section 6.1, PCI Local Bus Specification, 2.2\r
69///\r
a7ed1e2e 70typedef struct {\r
71 PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
72 PCI_DEVICE_HEADER_TYPE_REGION Device;\r
73} PCI_TYPE00;\r
74\r
bc14bdb3 75///\r
427987f5 76/// PCI-PCI Bridge header region in PCI Configuration Space\r
77/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
bc14bdb3 78///\r
a7ed1e2e 79typedef struct {\r
80 UINT32 Bar[2];\r
81 UINT8 PrimaryBus;\r
82 UINT8 SecondaryBus;\r
83 UINT8 SubordinateBus;\r
84 UINT8 SecondaryLatencyTimer;\r
85 UINT8 IoBase;\r
86 UINT8 IoLimit;\r
87 UINT16 SecondaryStatus;\r
88 UINT16 MemoryBase;\r
89 UINT16 MemoryLimit;\r
90 UINT16 PrefetchableMemoryBase;\r
91 UINT16 PrefetchableMemoryLimit;\r
92 UINT32 PrefetchableBaseUpper32;\r
93 UINT32 PrefetchableLimitUpper32;\r
94 UINT16 IoBaseUpper16;\r
95 UINT16 IoLimitUpper16;\r
96 UINT8 CapabilityPtr;\r
97 UINT8 Reserved[3];\r
98 UINT32 ExpansionRomBAR;\r
99 UINT8 InterruptLine;\r
100 UINT8 InterruptPin;\r
101 UINT16 BridgeControl;\r
102} PCI_BRIDGE_CONTROL_REGISTER;\r
103\r
427987f5 104///\r
105/// PCI-to-PCI Bridge Configuration Space\r
106/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
107///\r
a7ed1e2e 108typedef struct {\r
109 PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
110 PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
111} PCI_TYPE01;\r
112\r
113typedef union {\r
114 PCI_TYPE00 Device;\r
115 PCI_TYPE01 Bridge;\r
116} PCI_TYPE_GENERIC;\r
117\r
bc14bdb3 118/// \r
427987f5 119/// CardBus Conroller Configuration Space, \r
120/// Section 4.5.1, PC Card Standard. 8.0\r
bc14bdb3 121///\r
a7ed1e2e 122typedef struct {\r
bc14bdb3 123 UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base\r
124 UINT8 Cap_Ptr;\r
125 UINT8 Reserved;\r
126 UINT16 SecondaryStatus; ///< Secondary Status\r
127 UINT8 PciBusNumber; ///< PCI Bus Number\r
128 UINT8 CardBusBusNumber; ///< CardBus Bus Number\r
129 UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r
130 UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r
131 UINT32 MemoryBase0; ///< Memory Base Register 0\r
132 UINT32 MemoryLimit0; ///< Memory Limit Register 0\r
a7ed1e2e 133 UINT32 MemoryBase1;\r
134 UINT32 MemoryLimit1;\r
135 UINT32 IoBase0;\r
bc14bdb3 136 UINT32 IoLimit0; ///< I/O Base Register 0\r
137 UINT32 IoBase1; ///< I/O Limit Register 0\r
a7ed1e2e 138 UINT32 IoLimit1;\r
bc14bdb3 139 UINT8 InterruptLine; ///< Interrupt Line\r
140 UINT8 InterruptPin; ///< Interrupt Pin\r
141 UINT16 BridgeControl; ///< Bridge Control\r
a7ed1e2e 142} PCI_CARDBUS_CONTROL_REGISTER;\r
143\r
a2461f6b 144//\r
145// Definitions of PCI class bytes and manipulation macros.\r
146//\r
a7ed1e2e 147#define PCI_CLASS_OLD 0x00\r
bc14bdb3 148#define PCI_CLASS_OLD_OTHER 0x00\r
149#define PCI_CLASS_OLD_VGA 0x01\r
a7ed1e2e 150\r
151#define PCI_CLASS_MASS_STORAGE 0x01\r
bc14bdb3 152#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
153#define PCI_CLASS_MASS_STORAGE_IDE 0x01\r
154#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
155#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
156#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
157#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
a7ed1e2e 158\r
159#define PCI_CLASS_NETWORK 0x02\r
bc14bdb3 160#define PCI_CLASS_NETWORK_ETHERNET 0x00 \r
161#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
162#define PCI_CLASS_NETWORK_FDDI 0x02\r
163#define PCI_CLASS_NETWORK_ATM 0x03\r
164#define PCI_CLASS_NETWORK_ISDN 0x04\r
165#define PCI_CLASS_NETWORK_OTHER 0x80\r
a7ed1e2e 166\r
167#define PCI_CLASS_DISPLAY 0x03\r
bc14bdb3 168#define PCI_CLASS_DISPLAY_VGA 0x00\r
169#define PCI_IF_VGA_VGA 0x00\r
170#define PCI_IF_VGA_8514 0x01\r
171#define PCI_CLASS_DISPLAY_XGA 0x01\r
172#define PCI_CLASS_DISPLAY_3D 0x02\r
173#define PCI_CLASS_DISPLAY_OTHER 0x80 \r
bc14bdb3 174\r
175#define PCI_CLASS_MEDIA 0x04\r
176#define PCI_CLASS_MEDIA_VIDEO 0x00\r
177#define PCI_CLASS_MEDIA_AUDIO 0x01\r
178#define PCI_CLASS_MEDIA_TELEPHONE 0x02\r
179#define PCI_CLASS_MEDIA_OTHER 0x80\r
180\r
181#define PCI_CLASS_MEMORY_CONTROLLER 0x05\r
182#define PCI_CLASS_MEMORY_RAM 0x00\r
183#define PCI_CLASS_MEMORY_FLASH 0x01\r
184#define PCI_CLASS_MEMORY_OTHER 0x80\r
185\r
a7ed1e2e 186#define PCI_CLASS_BRIDGE 0x06\r
bc14bdb3 187#define PCI_CLASS_BRIDGE_HOST 0x00\r
188#define PCI_CLASS_BRIDGE_ISA 0x01\r
189#define PCI_CLASS_BRIDGE_EISA 0x02\r
190#define PCI_CLASS_BRIDGE_MCA 0x03\r
191#define PCI_CLASS_BRIDGE_P2P 0x04\r
192#define PCI_IF_BRIDGE_P2P 0x00\r
193#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r
194#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
195#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
196#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
197#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
198#define PCI_CLASS_BRIDGE_OTHER 0x80\r
199#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
200\r
201#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers \r
202#define PCI_SUBCLASS_SERIAL 0x00\r
203#define PCI_IF_GENERIC_XT 0x00\r
204#define PCI_IF_16450 0x01\r
205#define PCI_IF_16550 0x02\r
206#define PCI_IF_16650 0x03\r
207#define PCI_IF_16750 0x04\r
208#define PCI_IF_16850 0x05\r
209#define PCI_IF_16950 0x06\r
210#define PCI_SUBCLASS_PARALLEL 0x01\r
211#define PCI_IF_PARALLEL_PORT 0x00\r
212#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
213#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
214#define PCI_IF_1284_CONTROLLER 0x03\r
215#define PCI_IF_1284_DEVICE 0xFE\r
216#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
217#define PCI_SUBCLASS_MODEM 0x03\r
218#define PCI_IF_GENERIC_MODEM 0x00\r
219#define PCI_IF_16450_MODEM 0x01\r
220#define PCI_IF_16550_MODEM 0x02\r
221#define PCI_IF_16650_MODEM 0x03\r
222#define PCI_IF_16750_MODEM 0x04\r
223#define PCI_SUBCLASS_SCC_OTHER 0x80\r
a7ed1e2e 224\r
225#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
bc14bdb3 226#define PCI_SUBCLASS_PIC 0x00\r
227#define PCI_IF_8259_PIC 0x00\r
228#define PCI_IF_ISA_PIC 0x01\r
229#define PCI_IF_EISA_PIC 0x02\r
230#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory. \r
231#define PCI_IF_APIC_CONTROLLER2 0x20 \r
232#define PCI_SUBCLASS_DMA 0x01\r
233#define PCI_IF_8237_DMA 0x00\r
234#define PCI_IF_ISA_DMA 0x01\r
235#define PCI_IF_EISA_DMA 0x02\r
236#define PCI_SUBCLASS_TIMER 0x02\r
237#define PCI_IF_8254_TIMER 0x00\r
238#define PCI_IF_ISA_TIMER 0x01\r
239#define PCI_IF_EISA_TIMER 0x02\r
240#define PCI_SUBCLASS_RTC 0x03\r
241#define PCI_IF_GENERIC_RTC 0x00\r
242#define PCI_IF_ISA_RTC 0x00\r
243#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r
244#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
a7ed1e2e 245\r
246#define PCI_CLASS_INPUT_DEVICE 0x09\r
bc14bdb3 247#define PCI_SUBCLASS_KEYBOARD 0x00\r
248#define PCI_SUBCLASS_PEN 0x01\r
249#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
250#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
251#define PCI_SUBCLASS_GAMEPORT 0x04\r
252#define PCI_IF_GAMEPORT 0x00\r
253#define PCI_IF_GAMEPORT1 0x01\r
254#define PCI_SUBCLASS_INPUT_OTHER 0x80\r
a7ed1e2e 255\r
256#define PCI_CLASS_DOCKING_STATION 0x0A\r
257\r
258#define PCI_CLASS_PROCESSOR 0x0B\r
bc14bdb3 259#define PCI_SUBCLASS_PROC_386 0x00\r
260#define PCI_SUBCLASS_PROC_486 0x01\r
261#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
262#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
263#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
264#define PCI_SUBCLASS_PROC_MIPS 0x30\r
265#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r
a7ed1e2e 266\r
267#define PCI_CLASS_SERIAL 0x0C\r
bc14bdb3 268#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
269#define PCI_IF_1394 0x00\r
270#define PCI_IF_1394_OPEN_HCI 0x10\r
271#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
272#define PCI_CLASS_SERIAL_SSA 0x02\r
273#define PCI_CLASS_SERIAL_USB 0x03\r
274#define PCI_IF_UHCI 0x00\r
275#define PCI_IF_OHCI 0x10\r
276#define PCI_IF_USB_OTHER 0x80\r
277#define PCI_IF_USB_DEVICE 0xFE\r
278#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
279#define PCI_CLASS_SERIAL_SMB 0x05\r
a7ed1e2e 280\r
281#define PCI_CLASS_WIRELESS 0x0D\r
bc14bdb3 282#define PCI_SUBCLASS_IRDA 0x00\r
283#define PCI_SUBCLASS_IR 0x01\r
284#define PCI_SUBCLASS_RF 0x02\r
285#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r
a7ed1e2e 286\r
287#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
288\r
289#define PCI_CLASS_SATELLITE 0x0F\r
bc14bdb3 290#define PCI_SUBCLASS_TV 0x01\r
291#define PCI_SUBCLASS_AUDIO 0x02\r
292#define PCI_SUBCLASS_VOICE 0x03\r
293#define PCI_SUBCLASS_DATA 0x04\r
a7ed1e2e 294\r
bc14bdb3 295#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r
296#define PCI_SUBCLASS_NET_COMPUT 0x00\r
297#define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r
298#define PCI_SUBCLASS_SECURITY_OTHER 0x80\r
a7ed1e2e 299\r
300#define PCI_CLASS_DPIO 0x11\r
bc14bdb3 301#define PCI_SUBCLASS_DPIO 0x00\r
302#define PCI_SUBCLASS_DPIO_OTHER 0x80\r
a7ed1e2e 303\r
1833218d 304/** \r
305 Macro that checks whether the Base Class code of device matched.\r
306\r
307 @param _p Specified device.\r
308 @param c Base Class code needs matching.\r
309\r
310 @retval TRUE Base Class code matches the specified device.\r
311 @retval FALSE Base Class code doesn't match the specified device. \r
312\r
313**/\r
a7ed1e2e 314#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
1833218d 315/** \r
316 Macro that checks whether the Base Class code and Sub-Class code of device matched.\r
317\r
318 @param _p Specified device.\r
319 @param c Base Class code needs matching.\r
320 @param s Sub-Class code needs matching.\r
321\r
322 @retval TRUE Base Class code and Sub-Class code match the specified device.\r
323 @retval FALSE Base Class code and Sub-Class code don't match the specified device. \r
324\r
325**/\r
a7ed1e2e 326#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
1833218d 327/** \r
328 Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r
329\r
330 @param _p Specified device.\r
331 @param c Base Class code needs matching.\r
332 @param s Sub-Class code needs matching.\r
333 @param p Interface code needs matching.\r
334\r
335 @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\r
336 @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device. \r
337\r
338**/\r
a7ed1e2e 339#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
340\r
1833218d 341/** \r
342 Macro that checks whether device is a display controller.\r
343\r
344 @param _p Specified device.\r
345\r
346 @retval TRUE Device is a display controller.\r
347 @retval FALSE Device is not a display controller.\r
348\r
349**/\r
a7ed1e2e 350#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
1833218d 351/** \r
352 Macro that checks whether device is a VGA-compatible controller.\r
353\r
354 @param _p Specified device.\r
355\r
356 @retval TRUE Device is a VGA-compatible controller.\r
357 @retval FALSE Device is not a VGA-compatible controller.\r
358\r
359**/\r
360#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r
361/** \r
362 Macro that checks whether device is an 8514-compatible controller.\r
363\r
364 @param _p Specified device.\r
365\r
366 @retval TRUE Device is an 8514-compatible controller.\r
367 @retval FALSE Device is not an 8514-compatible controller.\r
368\r
369**/\r
370#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r
371/** \r
372 Macro that checks whether device is built before the Class Code field was defined.\r
373\r
374 @param _p Specified device.\r
375\r
376 @retval TRUE Device is an old device.\r
377 @retval FALSE Device is not an old device.\r
378\r
379**/\r
a7ed1e2e 380#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
1833218d 381/** \r
382 Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r
383\r
384 @param _p Specified device.\r
385\r
386 @retval TRUE Device is an old VGA-compatible device.\r
387 @retval FALSE Device is not an old VGA-compatible device.\r
388\r
389**/\r
a7ed1e2e 390#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
1833218d 391/** \r
392 Macro that checks whether device is an IDE controller.\r
393\r
394 @param _p Specified device.\r
395\r
396 @retval TRUE Device is an IDE controller.\r
397 @retval FALSE Device is not an IDE controller.\r
398\r
399**/\r
a7ed1e2e 400#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
1833218d 401/** \r
402 Macro that checks whether device is a SCSI bus controller.\r
403\r
404 @param _p Specified device.\r
405\r
406 @retval TRUE Device is a SCSI bus controller.\r
407 @retval FALSE Device is not a SCSI bus controller.\r
408\r
409**/\r
410#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r
411/** \r
412 Macro that checks whether device is a RAID controller.\r
413\r
414 @param _p Specified device.\r
415\r
416 @retval TRUE Device is a RAID controller.\r
417 @retval FALSE Device is not a RAID controller.\r
418\r
419**/\r
420#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r
421/** \r
422 Macro that checks whether device is an ISA bridge.\r
423\r
424 @param _p Specified device.\r
425\r
426 @retval TRUE Device is an ISA bridge.\r
427 @retval FALSE Device is not an ISA bridge.\r
428\r
429**/\r
430#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r
431/** \r
432 Macro that checks whether device is a PCI-to-PCI bridge.\r
433\r
434 @param _p Specified device.\r
435\r
436 @retval TRUE Device is a PCI-to-PCI bridge.\r
437 @retval FALSE Device is not a PCI-to-PCI bridge.\r
438\r
439**/\r
440#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r
441/** \r
442 Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r
443\r
444 @param _p Specified device.\r
445\r
446 @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.\r
447 @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\r
448\r
449**/\r
450#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r
451/** \r
452 Macro that checks whether device is a 16550-compatible serial controller.\r
453\r
454 @param _p Specified device.\r
455\r
456 @retval TRUE Device is a 16550-compatible serial controller.\r
457 @retval FALSE Device is not a 16550-compatible serial controller.\r
458\r
459**/\r
a7ed1e2e 460#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
1833218d 461/** \r
462 Macro that checks whether device is a Universal Serial Bus controller.\r
463\r
464 @param _p Specified device.\r
465\r
466 @retval TRUE Device is a Universal Serial Bus controller.\r
467 @retval FALSE Device is not a Universal Serial Bus controller.\r
468\r
469**/\r
a7ed1e2e 470#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
471\r
bc14bdb3 472//\r
473// the definition of Header Type \r
474//\r
a7ed1e2e 475#define HEADER_TYPE_DEVICE 0x00\r
476#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
477#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
a7ed1e2e 478#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
bc14bdb3 479//\r
480// Mask of Header type\r
481//\r
a7ed1e2e 482#define HEADER_LAYOUT_CODE 0x7f\r
1833218d 483/** \r
484 Macro that checks whether device is a PCI-PCI bridge.\r
485\r
486 @param _p Specified device.\r
487\r
488 @retval TRUE Device is a PCI-PCI bridge.\r
489 @retval FALSE Device is not a PCI-PCI bridge.\r
a7ed1e2e 490\r
1833218d 491**/\r
a7ed1e2e 492#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
1833218d 493/** \r
494 Macro that checks whether device is a CardBus bridge.\r
495\r
496 @param _p Specified device.\r
497\r
498 @retval TRUE Device is a CardBus bridge.\r
499 @retval FALSE Device is not a CardBus bridge.\r
500\r
501**/\r
a7ed1e2e 502#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
1833218d 503/** \r
504 Macro that checks whether device is a multiple functions device.\r
505\r
506 @param _p Specified device.\r
507\r
508 @retval TRUE Device is a multiple functions device.\r
509 @retval FALSE Device is not a multiple functions device.\r
510\r
511**/\r
a7ed1e2e 512#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
513\r
bc14bdb3 514///\r
515/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r
516///\r
a7ed1e2e 517#define PCI_BRIDGE_ROMBAR 0x38\r
518\r
519#define PCI_MAX_BAR 0x0006\r
520#define PCI_MAX_CONFIG_OFFSET 0x0100\r
521\r
522#define PCI_VENDOR_ID_OFFSET 0x00\r
523#define PCI_DEVICE_ID_OFFSET 0x02\r
524#define PCI_COMMAND_OFFSET 0x04\r
525#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
526#define PCI_REVISION_ID_OFFSET 0x08\r
527#define PCI_CLASSCODE_OFFSET 0x09\r
528#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
529#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
530#define PCI_HEADER_TYPE_OFFSET 0x0E\r
531#define PCI_BIST_OFFSET 0x0F\r
532#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
533#define PCI_CARDBUS_CIS_OFFSET 0x28\r
bc14bdb3 534#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r
a7ed1e2e 535#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
bc14bdb3 536#define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r
a7ed1e2e 537#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
538#define PCI_EXPANSION_ROM_BASE 0x30\r
539#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
bc14bdb3 540#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r
541#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r
542#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r
543#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r
a7ed1e2e 544\r
a2461f6b 545//\r
546// defined in PCI-to-PCI Bridge Architecture Specification\r
547//\r
bc14bdb3 548#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r
549#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r
550#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r
551#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r
552#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r
a7ed1e2e 553\r
bc14bdb3 554///\r
555/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
556///\r
a7ed1e2e 557#define PCI_INT_LINE_UNKNOWN 0xFF \r
558\r
1833218d 559///\r
560/// PCI Access Data Format\r
561///\r
a7ed1e2e 562typedef union {\r
563 struct {\r
564 UINT32 Reg : 8;\r
565 UINT32 Func : 3;\r
566 UINT32 Dev : 5;\r
567 UINT32 Bus : 8;\r
568 UINT32 Reserved : 7;\r
569 UINT32 Enable : 1;\r
570 } Bits;\r
571 UINT32 Uint32;\r
572} PCI_CONFIG_ACCESS_CF8;\r
573\r
766f4bc1 574#pragma pack()\r
575\r
bc14bdb3 576#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r
577#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r
578#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r
579#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r
580#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r
581#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r
582#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r
583#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r
584#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r
585#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r
a7ed1e2e 586\r
a2461f6b 587//\r
588// defined in PCI-to-PCI Bridge Architecture Specification\r
589//\r
bc14bdb3 590#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r
591#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r
592#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r
593#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r
594#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r
595#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r
596#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r
597#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r
598#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r
599#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r
600#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r
601#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r
602\r
a2461f6b 603//\r
604// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
605//\r
bc14bdb3 606#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r
607#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r
608#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r
609#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r
a7ed1e2e 610\r
611//\r
612// Following are the PCI status control bit\r
613//\r
bc14bdb3 614#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r
615#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r
616#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r
617#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r
a7ed1e2e 618\r
bc14bdb3 619///\r
620/// defined in PC Card Standard\r
621///\r
a7ed1e2e 622#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
623\r
766f4bc1 624#pragma pack(1)\r
a7ed1e2e 625//\r
626// PCI Capability List IDs and records\r
627//\r
628#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
629#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
630#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
631#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
632#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
633#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
a2461f6b 634\r
427987f5 635///\r
636/// Capabilities List Header\r
637/// Section 6.7, PCI Local Bus Specification, 2.2\r
638///\r
a7ed1e2e 639typedef struct {\r
640 UINT8 CapabilityID;\r
641 UINT8 NextItemPtr;\r
642} EFI_PCI_CAPABILITY_HDR;\r
643\r
1bc5d021 644///\r
427987f5 645/// Power Management Register Block Definition \r
646/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
1bc5d021 647///\r
a7ed1e2e 648typedef struct {\r
649 EFI_PCI_CAPABILITY_HDR Hdr;\r
650 UINT16 PMC;\r
651 UINT16 PMCSR;\r
652 UINT8 BridgeExtention;\r
653 UINT8 Data;\r
654} EFI_PCI_CAPABILITY_PMI;\r
655\r
1bc5d021 656///\r
427987f5 657/// A.G.P Capability\r
658/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r
1bc5d021 659///\r
a7ed1e2e 660typedef struct {\r
661 EFI_PCI_CAPABILITY_HDR Hdr;\r
662 UINT8 Rev;\r
663 UINT8 Reserved;\r
664 UINT32 Status;\r
665 UINT32 Command;\r
666} EFI_PCI_CAPABILITY_AGP;\r
667\r
1bc5d021 668///\r
427987f5 669/// VPD Capability Structure\r
670/// Appendix I, PCI Local Bus Specification, 2.2\r
1bc5d021 671///\r
a7ed1e2e 672typedef struct {\r
673 EFI_PCI_CAPABILITY_HDR Hdr;\r
674 UINT16 AddrReg;\r
675 UINT32 DataReg;\r
676} EFI_PCI_CAPABILITY_VPD;\r
677\r
1bc5d021 678///\r
427987f5 679/// Slot Numbering Capabilities Register\r
680/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2\r
1bc5d021 681///\r
a7ed1e2e 682typedef struct {\r
683 EFI_PCI_CAPABILITY_HDR Hdr;\r
684 UINT8 ExpnsSlotReg;\r
685 UINT8 ChassisNo;\r
686} EFI_PCI_CAPABILITY_SLOTID;\r
687\r
1bc5d021 688///\r
427987f5 689/// Message Capability Structure for 32-bit Message Address\r
690/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
1bc5d021 691///\r
a7ed1e2e 692typedef struct {\r
693 EFI_PCI_CAPABILITY_HDR Hdr;\r
694 UINT16 MsgCtrlReg;\r
695 UINT32 MsgAddrReg;\r
696 UINT16 MsgDataReg;\r
697} EFI_PCI_CAPABILITY_MSI32;\r
698\r
427987f5 699///\r
700/// Message Capability Structure for 64-bit Message Address\r
701/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
702///\r
a7ed1e2e 703typedef struct {\r
704 EFI_PCI_CAPABILITY_HDR Hdr;\r
705 UINT16 MsgCtrlReg;\r
706 UINT32 MsgAddrRegLsdw;\r
707 UINT32 MsgAddrRegMsdw;\r
708 UINT16 MsgDataReg;\r
709} EFI_PCI_CAPABILITY_MSI64;\r
710\r
1bc5d021 711///\r
427987f5 712/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, \r
713/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
1bc5d021 714///\r
a7ed1e2e 715typedef struct {\r
716 EFI_PCI_CAPABILITY_HDR Hdr;\r
1bc5d021 717 ///\r
718 /// not finished - fields need to go here\r
719 ///\r
a7ed1e2e 720} EFI_PCI_CAPABILITY_HOTPLUG;\r
721\r
a7ed1e2e 722#define DEVICE_ID_NOCARE 0xFFFF\r
723\r
724#define PCI_ACPI_UNUSED 0\r
725#define PCI_BAR_NOCHANGE 0\r
726#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r
727#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r
728#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
729#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
730\r
731#define PCI_BAR_IDX0 0x00\r
732#define PCI_BAR_IDX1 0x01\r
733#define PCI_BAR_IDX2 0x02\r
734#define PCI_BAR_IDX3 0x03\r
735#define PCI_BAR_IDX4 0x04\r
736#define PCI_BAR_IDX5 0x05\r
737#define PCI_BAR_ALL 0xFF\r
738\r
bc14bdb3 739///\r
740/// EFI PCI Option ROM definitions\r
741/// \r
742#define EFI_ROOT_BRIDGE_LIST 'eprb' \r
743#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r
afcf4907 744\r
bc14bdb3 745#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
13c31065 746#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r
bc14bdb3 747#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
a2461f6b 748#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r
bc14bdb3 749\r
427987f5 750///\r
751/// Standard PCI Expansion ROM Header\r
752/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
753///\r
bc14bdb3 754typedef struct {\r
755 UINT16 Signature; ///< 0xaa55\r
756 UINT8 Reserved[0x16];\r
757 UINT16 PcirOffset;\r
758} PCI_EXPANSION_ROM_HEADER;\r
759\r
427987f5 760///\r
761/// Legacy ROM Header Extensions\r
762/// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r
763///\r
bc14bdb3 764typedef struct {\r
765 UINT16 Signature; ///< 0xaa55\r
766 UINT8 Size512;\r
767 UINT8 InitEntryPoint[3];\r
768 UINT8 Reserved[0x12];\r
769 UINT16 PcirOffset;\r
770} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
771\r
427987f5 772///\r
773/// PCI Data Structure Format\r
774/// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r
775///\r
bc14bdb3 776typedef struct {\r
777 UINT32 Signature; ///< "PCIR"\r
778 UINT16 VendorId;\r
779 UINT16 DeviceId;\r
780 UINT16 Reserved0;\r
781 UINT16 Length;\r
782 UINT8 Revision;\r
783 UINT8 ClassCode[3];\r
784 UINT16 ImageLength;\r
785 UINT16 CodeRevision;\r
786 UINT8 CodeType;\r
787 UINT8 Indicator;\r
788 UINT16 Reserved1;\r
789} PCI_DATA_STRUCTURE;\r
790\r
791///\r
427987f5 792/// EFI PCI Expansion ROM Header\r
793/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
bc14bdb3 794///\r
afcf4907 795typedef struct {\r
bc14bdb3 796 UINT16 Signature; ///< 0xaa55\r
afcf4907 797 UINT16 InitializationSize;\r
bc14bdb3 798 UINT32 EfiSignature; ///< 0x0EF1\r
afcf4907 799 UINT16 EfiSubsystem;\r
800 UINT16 EfiMachineType;\r
801 UINT16 CompressionType;\r
802 UINT8 Reserved[8];\r
803 UINT16 EfiImageHeaderOffset;\r
804 UINT16 PcirOffset;\r
805} EFI_PCI_EXPANSION_ROM_HEADER;\r
806\r
807typedef union {\r
808 UINT8 *Raw;\r
809 PCI_EXPANSION_ROM_HEADER *Generic;\r
810 EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r
811 EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
812} EFI_PCI_ROM_HEADER;\r
813\r
766f4bc1 814#pragma pack()\r
815\r
a7ed1e2e 816#endif\r
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