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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 2.2 standard.\r | |
3 | \r | |
bc14bdb3 | 4 | This file includes the definitions in the following specifications,\r |
427987f5 | 5 | PCI Local Bus Specification, 2.2\r |
6 | PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r | |
bc14bdb3 | 7 | PC Card Standard, 8.0\r |
8 | \r | |
9 | Copyright (c) 2006 - 2008, Intel Corporation \r | |
a7ed1e2e | 10 | All rights reserved. This program and the accompanying materials \r |
11 | are licensed and made available under the terms and conditions of the BSD License \r | |
12 | which accompanies this distribution. The full text of the license may be found at \r | |
13 | http://opensource.org/licenses/bsd-license.php \r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
17 | \r | |
a7ed1e2e | 18 | **/\r |
19 | \r | |
42eedea9 | 20 | #ifndef _PCI22_H_\r |
21 | #define _PCI22_H_\r | |
a7ed1e2e | 22 | \r |
23 | #define PCI_MAX_SEGMENT 0\r | |
a7ed1e2e | 24 | #define PCI_MAX_BUS 255\r |
a7ed1e2e | 25 | #define PCI_MAX_DEVICE 31\r |
26 | #define PCI_MAX_FUNC 7\r | |
27 | \r | |
766f4bc1 | 28 | #pragma pack(1)\r |
427987f5 | 29 | \r |
30 | ///\r | |
31 | /// Common header region in PCI Configuration Space\r | |
32 | /// Section 6.1, PCI Local Bus Specification, 2.2\r | |
33 | ///\r | |
a7ed1e2e | 34 | typedef struct {\r |
35 | UINT16 VendorId;\r | |
36 | UINT16 DeviceId;\r | |
37 | UINT16 Command;\r | |
38 | UINT16 Status;\r | |
39 | UINT8 RevisionID;\r | |
40 | UINT8 ClassCode[3];\r | |
41 | UINT8 CacheLineSize;\r | |
42 | UINT8 LatencyTimer;\r | |
43 | UINT8 HeaderType;\r | |
44 | UINT8 BIST;\r | |
45 | } PCI_DEVICE_INDEPENDENT_REGION;\r | |
46 | \r | |
427987f5 | 47 | ///\r |
48 | /// PCI Device header region in PCI Configuration Space\r | |
49 | /// Section 6.1, PCI Local Bus Specification, 2.2\r | |
50 | ///\r | |
a7ed1e2e | 51 | typedef struct {\r |
52 | UINT32 Bar[6];\r | |
53 | UINT32 CISPtr;\r | |
54 | UINT16 SubsystemVendorID;\r | |
55 | UINT16 SubsystemID;\r | |
56 | UINT32 ExpansionRomBar;\r | |
57 | UINT8 CapabilityPtr;\r | |
58 | UINT8 Reserved1[3];\r | |
59 | UINT32 Reserved2;\r | |
60 | UINT8 InterruptLine;\r | |
61 | UINT8 InterruptPin;\r | |
62 | UINT8 MinGnt;\r | |
63 | UINT8 MaxLat;\r | |
64 | } PCI_DEVICE_HEADER_TYPE_REGION;\r | |
65 | \r | |
427987f5 | 66 | ///\r |
67 | /// PCI Device Configuration Space\r | |
68 | /// Section 6.1, PCI Local Bus Specification, 2.2\r | |
69 | ///\r | |
a7ed1e2e | 70 | typedef struct {\r |
71 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r | |
72 | PCI_DEVICE_HEADER_TYPE_REGION Device;\r | |
73 | } PCI_TYPE00;\r | |
74 | \r | |
bc14bdb3 | 75 | ///\r |
427987f5 | 76 | /// PCI-PCI Bridge header region in PCI Configuration Space\r |
77 | /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r | |
bc14bdb3 | 78 | ///\r |
a7ed1e2e | 79 | typedef struct {\r |
80 | UINT32 Bar[2];\r | |
81 | UINT8 PrimaryBus;\r | |
82 | UINT8 SecondaryBus;\r | |
83 | UINT8 SubordinateBus;\r | |
84 | UINT8 SecondaryLatencyTimer;\r | |
85 | UINT8 IoBase;\r | |
86 | UINT8 IoLimit;\r | |
87 | UINT16 SecondaryStatus;\r | |
88 | UINT16 MemoryBase;\r | |
89 | UINT16 MemoryLimit;\r | |
90 | UINT16 PrefetchableMemoryBase;\r | |
91 | UINT16 PrefetchableMemoryLimit;\r | |
92 | UINT32 PrefetchableBaseUpper32;\r | |
93 | UINT32 PrefetchableLimitUpper32;\r | |
94 | UINT16 IoBaseUpper16;\r | |
95 | UINT16 IoLimitUpper16;\r | |
96 | UINT8 CapabilityPtr;\r | |
97 | UINT8 Reserved[3];\r | |
98 | UINT32 ExpansionRomBAR;\r | |
99 | UINT8 InterruptLine;\r | |
100 | UINT8 InterruptPin;\r | |
101 | UINT16 BridgeControl;\r | |
102 | } PCI_BRIDGE_CONTROL_REGISTER;\r | |
103 | \r | |
427987f5 | 104 | ///\r |
105 | /// PCI-to-PCI Bridge Configuration Space\r | |
106 | /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r | |
107 | ///\r | |
a7ed1e2e | 108 | typedef struct {\r |
109 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r | |
110 | PCI_BRIDGE_CONTROL_REGISTER Bridge;\r | |
111 | } PCI_TYPE01;\r | |
112 | \r | |
113 | typedef union {\r | |
114 | PCI_TYPE00 Device;\r | |
115 | PCI_TYPE01 Bridge;\r | |
116 | } PCI_TYPE_GENERIC;\r | |
117 | \r | |
bc14bdb3 | 118 | /// \r |
427987f5 | 119 | /// CardBus Conroller Configuration Space, \r |
120 | /// Section 4.5.1, PC Card Standard. 8.0\r | |
bc14bdb3 | 121 | ///\r |
a7ed1e2e | 122 | typedef struct {\r |
bc14bdb3 | 123 | UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base\r |
124 | UINT8 Cap_Ptr;\r | |
125 | UINT8 Reserved;\r | |
126 | UINT16 SecondaryStatus; ///< Secondary Status\r | |
127 | UINT8 PciBusNumber; ///< PCI Bus Number\r | |
128 | UINT8 CardBusBusNumber; ///< CardBus Bus Number\r | |
129 | UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r | |
130 | UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r | |
131 | UINT32 MemoryBase0; ///< Memory Base Register 0\r | |
132 | UINT32 MemoryLimit0; ///< Memory Limit Register 0\r | |
a7ed1e2e | 133 | UINT32 MemoryBase1;\r |
134 | UINT32 MemoryLimit1;\r | |
135 | UINT32 IoBase0;\r | |
bc14bdb3 | 136 | UINT32 IoLimit0; ///< I/O Base Register 0\r |
137 | UINT32 IoBase1; ///< I/O Limit Register 0\r | |
a7ed1e2e | 138 | UINT32 IoLimit1;\r |
bc14bdb3 | 139 | UINT8 InterruptLine; ///< Interrupt Line\r |
140 | UINT8 InterruptPin; ///< Interrupt Pin\r | |
141 | UINT16 BridgeControl; ///< Bridge Control\r | |
a7ed1e2e | 142 | } PCI_CARDBUS_CONTROL_REGISTER;\r |
143 | \r | |
a2461f6b | 144 | //\r |
145 | // Definitions of PCI class bytes and manipulation macros.\r | |
146 | //\r | |
a7ed1e2e | 147 | #define PCI_CLASS_OLD 0x00\r |
bc14bdb3 | 148 | #define PCI_CLASS_OLD_OTHER 0x00\r |
149 | #define PCI_CLASS_OLD_VGA 0x01\r | |
a7ed1e2e | 150 | \r |
151 | #define PCI_CLASS_MASS_STORAGE 0x01\r | |
bc14bdb3 | 152 | #define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r |
153 | #define PCI_CLASS_MASS_STORAGE_IDE 0x01\r | |
154 | #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r | |
155 | #define PCI_CLASS_MASS_STORAGE_IPI 0x03\r | |
156 | #define PCI_CLASS_MASS_STORAGE_RAID 0x04\r | |
157 | #define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r | |
a7ed1e2e | 158 | \r |
159 | #define PCI_CLASS_NETWORK 0x02\r | |
bc14bdb3 | 160 | #define PCI_CLASS_NETWORK_ETHERNET 0x00 \r |
161 | #define PCI_CLASS_NETWORK_TOKENRING 0x01\r | |
162 | #define PCI_CLASS_NETWORK_FDDI 0x02\r | |
163 | #define PCI_CLASS_NETWORK_ATM 0x03\r | |
164 | #define PCI_CLASS_NETWORK_ISDN 0x04\r | |
165 | #define PCI_CLASS_NETWORK_OTHER 0x80\r | |
a7ed1e2e | 166 | \r |
167 | #define PCI_CLASS_DISPLAY 0x03\r | |
bc14bdb3 | 168 | #define PCI_CLASS_DISPLAY_VGA 0x00\r |
169 | #define PCI_IF_VGA_VGA 0x00\r | |
170 | #define PCI_IF_VGA_8514 0x01\r | |
171 | #define PCI_CLASS_DISPLAY_XGA 0x01\r | |
172 | #define PCI_CLASS_DISPLAY_3D 0x02\r | |
173 | #define PCI_CLASS_DISPLAY_OTHER 0x80 \r | |
174 | #define PCI_CLASS_DISPLAY_GFX 0x80\r | |
175 | \r | |
176 | #define PCI_CLASS_MEDIA 0x04\r | |
177 | #define PCI_CLASS_MEDIA_VIDEO 0x00\r | |
178 | #define PCI_CLASS_MEDIA_AUDIO 0x01\r | |
179 | #define PCI_CLASS_MEDIA_TELEPHONE 0x02\r | |
180 | #define PCI_CLASS_MEDIA_OTHER 0x80\r | |
181 | \r | |
182 | #define PCI_CLASS_MEMORY_CONTROLLER 0x05\r | |
183 | #define PCI_CLASS_MEMORY_RAM 0x00\r | |
184 | #define PCI_CLASS_MEMORY_FLASH 0x01\r | |
185 | #define PCI_CLASS_MEMORY_OTHER 0x80\r | |
186 | \r | |
a7ed1e2e | 187 | #define PCI_CLASS_BRIDGE 0x06\r |
bc14bdb3 | 188 | #define PCI_CLASS_BRIDGE_HOST 0x00\r |
189 | #define PCI_CLASS_BRIDGE_ISA 0x01\r | |
190 | #define PCI_CLASS_BRIDGE_EISA 0x02\r | |
191 | #define PCI_CLASS_BRIDGE_MCA 0x03\r | |
192 | #define PCI_CLASS_BRIDGE_P2P 0x04\r | |
193 | #define PCI_IF_BRIDGE_P2P 0x00\r | |
194 | #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r | |
195 | #define PCI_CLASS_BRIDGE_PCMCIA 0x05\r | |
196 | #define PCI_CLASS_BRIDGE_NUBUS 0x06\r | |
197 | #define PCI_CLASS_BRIDGE_CARDBUS 0x07\r | |
198 | #define PCI_CLASS_BRIDGE_RACEWAY 0x08\r | |
199 | #define PCI_CLASS_BRIDGE_OTHER 0x80\r | |
200 | #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r | |
201 | \r | |
202 | #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers \r | |
203 | #define PCI_SUBCLASS_SERIAL 0x00\r | |
204 | #define PCI_IF_GENERIC_XT 0x00\r | |
205 | #define PCI_IF_16450 0x01\r | |
206 | #define PCI_IF_16550 0x02\r | |
207 | #define PCI_IF_16650 0x03\r | |
208 | #define PCI_IF_16750 0x04\r | |
209 | #define PCI_IF_16850 0x05\r | |
210 | #define PCI_IF_16950 0x06\r | |
211 | #define PCI_SUBCLASS_PARALLEL 0x01\r | |
212 | #define PCI_IF_PARALLEL_PORT 0x00\r | |
213 | #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r | |
214 | #define PCI_IF_ECP_PARALLEL_PORT 0x02\r | |
215 | #define PCI_IF_1284_CONTROLLER 0x03\r | |
216 | #define PCI_IF_1284_DEVICE 0xFE\r | |
217 | #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r | |
218 | #define PCI_SUBCLASS_MODEM 0x03\r | |
219 | #define PCI_IF_GENERIC_MODEM 0x00\r | |
220 | #define PCI_IF_16450_MODEM 0x01\r | |
221 | #define PCI_IF_16550_MODEM 0x02\r | |
222 | #define PCI_IF_16650_MODEM 0x03\r | |
223 | #define PCI_IF_16750_MODEM 0x04\r | |
224 | #define PCI_SUBCLASS_SCC_OTHER 0x80\r | |
a7ed1e2e | 225 | \r |
226 | #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r | |
bc14bdb3 | 227 | #define PCI_SUBCLASS_PIC 0x00\r |
228 | #define PCI_IF_8259_PIC 0x00\r | |
229 | #define PCI_IF_ISA_PIC 0x01\r | |
230 | #define PCI_IF_EISA_PIC 0x02\r | |
231 | #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory. \r | |
232 | #define PCI_IF_APIC_CONTROLLER2 0x20 \r | |
233 | #define PCI_SUBCLASS_DMA 0x01\r | |
234 | #define PCI_IF_8237_DMA 0x00\r | |
235 | #define PCI_IF_ISA_DMA 0x01\r | |
236 | #define PCI_IF_EISA_DMA 0x02\r | |
237 | #define PCI_SUBCLASS_TIMER 0x02\r | |
238 | #define PCI_IF_8254_TIMER 0x00\r | |
239 | #define PCI_IF_ISA_TIMER 0x01\r | |
240 | #define PCI_IF_EISA_TIMER 0x02\r | |
241 | #define PCI_SUBCLASS_RTC 0x03\r | |
242 | #define PCI_IF_GENERIC_RTC 0x00\r | |
243 | #define PCI_IF_ISA_RTC 0x00\r | |
244 | #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r | |
245 | #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r | |
a7ed1e2e | 246 | \r |
247 | #define PCI_CLASS_INPUT_DEVICE 0x09\r | |
bc14bdb3 | 248 | #define PCI_SUBCLASS_KEYBOARD 0x00\r |
249 | #define PCI_SUBCLASS_PEN 0x01\r | |
250 | #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r | |
251 | #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r | |
252 | #define PCI_SUBCLASS_GAMEPORT 0x04\r | |
253 | #define PCI_IF_GAMEPORT 0x00\r | |
254 | #define PCI_IF_GAMEPORT1 0x01\r | |
255 | #define PCI_SUBCLASS_INPUT_OTHER 0x80\r | |
a7ed1e2e | 256 | \r |
257 | #define PCI_CLASS_DOCKING_STATION 0x0A\r | |
258 | \r | |
259 | #define PCI_CLASS_PROCESSOR 0x0B\r | |
bc14bdb3 | 260 | #define PCI_SUBCLASS_PROC_386 0x00\r |
261 | #define PCI_SUBCLASS_PROC_486 0x01\r | |
262 | #define PCI_SUBCLASS_PROC_PENTIUM 0x02\r | |
263 | #define PCI_SUBCLASS_PROC_ALPHA 0x10\r | |
264 | #define PCI_SUBCLASS_PROC_POWERPC 0x20\r | |
265 | #define PCI_SUBCLASS_PROC_MIPS 0x30\r | |
266 | #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r | |
a7ed1e2e | 267 | \r |
268 | #define PCI_CLASS_SERIAL 0x0C\r | |
bc14bdb3 | 269 | #define PCI_CLASS_SERIAL_FIREWIRE 0x00\r |
270 | #define PCI_IF_1394 0x00\r | |
271 | #define PCI_IF_1394_OPEN_HCI 0x10\r | |
272 | #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r | |
273 | #define PCI_CLASS_SERIAL_SSA 0x02\r | |
274 | #define PCI_CLASS_SERIAL_USB 0x03\r | |
275 | #define PCI_IF_UHCI 0x00\r | |
276 | #define PCI_IF_OHCI 0x10\r | |
277 | #define PCI_IF_USB_OTHER 0x80\r | |
278 | #define PCI_IF_USB_DEVICE 0xFE\r | |
279 | #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r | |
280 | #define PCI_CLASS_SERIAL_SMB 0x05\r | |
a7ed1e2e | 281 | \r |
282 | #define PCI_CLASS_WIRELESS 0x0D\r | |
bc14bdb3 | 283 | #define PCI_SUBCLASS_IRDA 0x00\r |
284 | #define PCI_SUBCLASS_IR 0x01\r | |
285 | #define PCI_SUBCLASS_RF 0x02\r | |
286 | #define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r | |
a7ed1e2e | 287 | \r |
288 | #define PCI_CLASS_INTELLIGENT_IO 0x0E\r | |
289 | \r | |
290 | #define PCI_CLASS_SATELLITE 0x0F\r | |
bc14bdb3 | 291 | #define PCI_SUBCLASS_TV 0x01\r |
292 | #define PCI_SUBCLASS_AUDIO 0x02\r | |
293 | #define PCI_SUBCLASS_VOICE 0x03\r | |
294 | #define PCI_SUBCLASS_DATA 0x04\r | |
a7ed1e2e | 295 | \r |
bc14bdb3 | 296 | #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r |
297 | #define PCI_SUBCLASS_NET_COMPUT 0x00\r | |
298 | #define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r | |
299 | #define PCI_SUBCLASS_SECURITY_OTHER 0x80\r | |
a7ed1e2e | 300 | \r |
301 | #define PCI_CLASS_DPIO 0x11\r | |
bc14bdb3 | 302 | #define PCI_SUBCLASS_DPIO 0x00\r |
303 | #define PCI_SUBCLASS_DPIO_OTHER 0x80\r | |
a7ed1e2e | 304 | \r |
305 | #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r | |
306 | #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r | |
307 | #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r | |
308 | \r | |
309 | #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r | |
310 | #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)\r | |
311 | #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)\r | |
312 | #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)\r | |
313 | #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r | |
314 | #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r | |
315 | #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r | |
316 | #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)\r | |
317 | #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)\r | |
318 | #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)\r | |
319 | #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)\r | |
320 | #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)\r | |
321 | #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r | |
322 | #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r | |
323 | \r | |
bc14bdb3 | 324 | //\r |
325 | // the definition of Header Type \r | |
326 | //\r | |
a7ed1e2e | 327 | #define HEADER_TYPE_DEVICE 0x00\r |
328 | #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r | |
329 | #define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r | |
a7ed1e2e | 330 | #define HEADER_TYPE_MULTI_FUNCTION 0x80\r |
bc14bdb3 | 331 | //\r |
332 | // Mask of Header type\r | |
333 | //\r | |
a7ed1e2e | 334 | #define HEADER_LAYOUT_CODE 0x7f\r |
335 | \r | |
336 | #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r | |
337 | #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r | |
338 | #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r | |
339 | \r | |
bc14bdb3 | 340 | ///\r |
341 | /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r | |
342 | ///\r | |
a7ed1e2e | 343 | #define PCI_BRIDGE_ROMBAR 0x38\r |
344 | \r | |
345 | #define PCI_MAX_BAR 0x0006\r | |
346 | #define PCI_MAX_CONFIG_OFFSET 0x0100\r | |
347 | \r | |
348 | #define PCI_VENDOR_ID_OFFSET 0x00\r | |
349 | #define PCI_DEVICE_ID_OFFSET 0x02\r | |
350 | #define PCI_COMMAND_OFFSET 0x04\r | |
351 | #define PCI_PRIMARY_STATUS_OFFSET 0x06\r | |
352 | #define PCI_REVISION_ID_OFFSET 0x08\r | |
353 | #define PCI_CLASSCODE_OFFSET 0x09\r | |
354 | #define PCI_CACHELINE_SIZE_OFFSET 0x0C\r | |
355 | #define PCI_LATENCY_TIMER_OFFSET 0x0D\r | |
356 | #define PCI_HEADER_TYPE_OFFSET 0x0E\r | |
357 | #define PCI_BIST_OFFSET 0x0F\r | |
358 | #define PCI_BASE_ADDRESSREG_OFFSET 0x10\r | |
359 | #define PCI_CARDBUS_CIS_OFFSET 0x28\r | |
bc14bdb3 | 360 | #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r |
a7ed1e2e | 361 | #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r |
bc14bdb3 | 362 | #define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r |
a7ed1e2e | 363 | #define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r |
364 | #define PCI_EXPANSION_ROM_BASE 0x30\r | |
365 | #define PCI_CAPBILITY_POINTER_OFFSET 0x34\r | |
bc14bdb3 | 366 | #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r |
367 | #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r | |
368 | #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r | |
369 | #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r | |
a7ed1e2e | 370 | \r |
a2461f6b | 371 | //\r |
372 | // defined in PCI-to-PCI Bridge Architecture Specification\r | |
373 | //\r | |
bc14bdb3 | 374 | #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r |
375 | #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r | |
376 | #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r | |
377 | #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r | |
378 | #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r | |
a7ed1e2e | 379 | \r |
bc14bdb3 | 380 | ///\r |
381 | /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r | |
382 | ///\r | |
a7ed1e2e | 383 | #define PCI_INT_LINE_UNKNOWN 0xFF \r |
384 | \r | |
385 | typedef union {\r | |
386 | struct {\r | |
387 | UINT32 Reg : 8;\r | |
388 | UINT32 Func : 3;\r | |
389 | UINT32 Dev : 5;\r | |
390 | UINT32 Bus : 8;\r | |
391 | UINT32 Reserved : 7;\r | |
392 | UINT32 Enable : 1;\r | |
393 | } Bits;\r | |
394 | UINT32 Uint32;\r | |
395 | } PCI_CONFIG_ACCESS_CF8;\r | |
396 | \r | |
766f4bc1 | 397 | #pragma pack()\r |
398 | \r | |
bc14bdb3 | 399 | #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r |
400 | #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r | |
401 | #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r | |
402 | #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r | |
403 | #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r | |
404 | #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r | |
405 | #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r | |
406 | #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r | |
407 | #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r | |
408 | #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r | |
a7ed1e2e | 409 | \r |
a2461f6b | 410 | //\r |
411 | // defined in PCI-to-PCI Bridge Architecture Specification\r | |
412 | //\r | |
bc14bdb3 | 413 | #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r |
414 | #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r | |
415 | #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r | |
416 | #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r | |
417 | #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r | |
418 | #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r | |
419 | #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r | |
420 | #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r | |
421 | #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r | |
422 | #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r | |
423 | #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r | |
424 | #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r | |
425 | \r | |
a2461f6b | 426 | //\r |
427 | // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r | |
428 | //\r | |
bc14bdb3 | 429 | #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r |
430 | #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r | |
431 | #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r | |
432 | #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r | |
a7ed1e2e | 433 | \r |
434 | //\r | |
435 | // Following are the PCI status control bit\r | |
436 | //\r | |
bc14bdb3 | 437 | #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r |
438 | #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r | |
439 | #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r | |
440 | #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r | |
a7ed1e2e | 441 | \r |
bc14bdb3 | 442 | ///\r |
443 | /// defined in PC Card Standard\r | |
444 | ///\r | |
a7ed1e2e | 445 | #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r |
446 | \r | |
766f4bc1 | 447 | #pragma pack(1)\r |
a7ed1e2e | 448 | //\r |
449 | // PCI Capability List IDs and records\r | |
450 | //\r | |
451 | #define EFI_PCI_CAPABILITY_ID_PMI 0x01\r | |
452 | #define EFI_PCI_CAPABILITY_ID_AGP 0x02\r | |
453 | #define EFI_PCI_CAPABILITY_ID_VPD 0x03\r | |
454 | #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r | |
455 | #define EFI_PCI_CAPABILITY_ID_MSI 0x05\r | |
456 | #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r | |
a2461f6b | 457 | \r |
427987f5 | 458 | ///\r |
459 | /// Capabilities List Header\r | |
460 | /// Section 6.7, PCI Local Bus Specification, 2.2\r | |
461 | ///\r | |
a7ed1e2e | 462 | typedef struct {\r |
463 | UINT8 CapabilityID;\r | |
464 | UINT8 NextItemPtr;\r | |
465 | } EFI_PCI_CAPABILITY_HDR;\r | |
466 | \r | |
1bc5d021 | 467 | ///\r |
427987f5 | 468 | /// Power Management Register Block Definition \r |
469 | /// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r | |
1bc5d021 | 470 | ///\r |
a7ed1e2e | 471 | typedef struct {\r |
472 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
473 | UINT16 PMC;\r | |
474 | UINT16 PMCSR;\r | |
475 | UINT8 BridgeExtention;\r | |
476 | UINT8 Data;\r | |
477 | } EFI_PCI_CAPABILITY_PMI;\r | |
478 | \r | |
1bc5d021 | 479 | ///\r |
427987f5 | 480 | /// A.G.P Capability\r |
481 | /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r | |
1bc5d021 | 482 | ///\r |
a7ed1e2e | 483 | typedef struct {\r |
484 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
485 | UINT8 Rev;\r | |
486 | UINT8 Reserved;\r | |
487 | UINT32 Status;\r | |
488 | UINT32 Command;\r | |
489 | } EFI_PCI_CAPABILITY_AGP;\r | |
490 | \r | |
1bc5d021 | 491 | ///\r |
427987f5 | 492 | /// VPD Capability Structure\r |
493 | /// Appendix I, PCI Local Bus Specification, 2.2\r | |
1bc5d021 | 494 | ///\r |
a7ed1e2e | 495 | typedef struct {\r |
496 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
497 | UINT16 AddrReg;\r | |
498 | UINT32 DataReg;\r | |
499 | } EFI_PCI_CAPABILITY_VPD;\r | |
500 | \r | |
1bc5d021 | 501 | ///\r |
427987f5 | 502 | /// Slot Numbering Capabilities Register\r |
503 | /// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2\r | |
1bc5d021 | 504 | ///\r |
a7ed1e2e | 505 | typedef struct {\r |
506 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
507 | UINT8 ExpnsSlotReg;\r | |
508 | UINT8 ChassisNo;\r | |
509 | } EFI_PCI_CAPABILITY_SLOTID;\r | |
510 | \r | |
1bc5d021 | 511 | ///\r |
427987f5 | 512 | /// Message Capability Structure for 32-bit Message Address\r |
513 | /// Section 6.8.1, PCI Local Bus Specification, 2.2\r | |
1bc5d021 | 514 | ///\r |
a7ed1e2e | 515 | typedef struct {\r |
516 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
517 | UINT16 MsgCtrlReg;\r | |
518 | UINT32 MsgAddrReg;\r | |
519 | UINT16 MsgDataReg;\r | |
520 | } EFI_PCI_CAPABILITY_MSI32;\r | |
521 | \r | |
427987f5 | 522 | ///\r |
523 | /// Message Capability Structure for 64-bit Message Address\r | |
524 | /// Section 6.8.1, PCI Local Bus Specification, 2.2\r | |
525 | ///\r | |
a7ed1e2e | 526 | typedef struct {\r |
527 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
528 | UINT16 MsgCtrlReg;\r | |
529 | UINT32 MsgAddrRegLsdw;\r | |
530 | UINT32 MsgAddrRegMsdw;\r | |
531 | UINT16 MsgDataReg;\r | |
532 | } EFI_PCI_CAPABILITY_MSI64;\r | |
533 | \r | |
1bc5d021 | 534 | ///\r |
427987f5 | 535 | /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, \r |
536 | /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r | |
1bc5d021 | 537 | ///\r |
a7ed1e2e | 538 | typedef struct {\r |
539 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
1bc5d021 | 540 | ///\r |
541 | /// not finished - fields need to go here\r | |
542 | ///\r | |
a7ed1e2e | 543 | } EFI_PCI_CAPABILITY_HOTPLUG;\r |
544 | \r | |
a7ed1e2e | 545 | #define DEVICE_ID_NOCARE 0xFFFF\r |
546 | \r | |
547 | #define PCI_ACPI_UNUSED 0\r | |
548 | #define PCI_BAR_NOCHANGE 0\r | |
549 | #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r | |
550 | #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r | |
551 | #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r | |
552 | #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r | |
553 | \r | |
554 | #define PCI_BAR_IDX0 0x00\r | |
555 | #define PCI_BAR_IDX1 0x01\r | |
556 | #define PCI_BAR_IDX2 0x02\r | |
557 | #define PCI_BAR_IDX3 0x03\r | |
558 | #define PCI_BAR_IDX4 0x04\r | |
559 | #define PCI_BAR_IDX5 0x05\r | |
560 | #define PCI_BAR_ALL 0xFF\r | |
561 | \r | |
bc14bdb3 | 562 | ///\r |
563 | /// EFI PCI Option ROM definitions\r | |
564 | /// \r | |
565 | #define EFI_ROOT_BRIDGE_LIST 'eprb' \r | |
566 | #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r | |
afcf4907 | 567 | \r |
bc14bdb3 | 568 | #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r |
13c31065 | 569 | #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r |
bc14bdb3 | 570 | #define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r |
a2461f6b | 571 | #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r |
bc14bdb3 | 572 | \r |
427987f5 | 573 | ///\r |
574 | /// Standard PCI Expansion ROM Header\r | |
575 | /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r | |
576 | ///\r | |
bc14bdb3 | 577 | typedef struct {\r |
578 | UINT16 Signature; ///< 0xaa55\r | |
579 | UINT8 Reserved[0x16];\r | |
580 | UINT16 PcirOffset;\r | |
581 | } PCI_EXPANSION_ROM_HEADER;\r | |
582 | \r | |
427987f5 | 583 | ///\r |
584 | /// Legacy ROM Header Extensions\r | |
585 | /// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r | |
586 | ///\r | |
bc14bdb3 | 587 | typedef struct {\r |
588 | UINT16 Signature; ///< 0xaa55\r | |
589 | UINT8 Size512;\r | |
590 | UINT8 InitEntryPoint[3];\r | |
591 | UINT8 Reserved[0x12];\r | |
592 | UINT16 PcirOffset;\r | |
593 | } EFI_LEGACY_EXPANSION_ROM_HEADER;\r | |
594 | \r | |
427987f5 | 595 | ///\r |
596 | /// PCI Data Structure Format\r | |
597 | /// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r | |
598 | ///\r | |
bc14bdb3 | 599 | typedef struct {\r |
600 | UINT32 Signature; ///< "PCIR"\r | |
601 | UINT16 VendorId;\r | |
602 | UINT16 DeviceId;\r | |
603 | UINT16 Reserved0;\r | |
604 | UINT16 Length;\r | |
605 | UINT8 Revision;\r | |
606 | UINT8 ClassCode[3];\r | |
607 | UINT16 ImageLength;\r | |
608 | UINT16 CodeRevision;\r | |
609 | UINT8 CodeType;\r | |
610 | UINT8 Indicator;\r | |
611 | UINT16 Reserved1;\r | |
612 | } PCI_DATA_STRUCTURE;\r | |
613 | \r | |
614 | ///\r | |
427987f5 | 615 | /// EFI PCI Expansion ROM Header\r |
616 | /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r | |
bc14bdb3 | 617 | ///\r |
afcf4907 | 618 | typedef struct {\r |
bc14bdb3 | 619 | UINT16 Signature; ///< 0xaa55\r |
afcf4907 | 620 | UINT16 InitializationSize;\r |
bc14bdb3 | 621 | UINT32 EfiSignature; ///< 0x0EF1\r |
afcf4907 | 622 | UINT16 EfiSubsystem;\r |
623 | UINT16 EfiMachineType;\r | |
624 | UINT16 CompressionType;\r | |
625 | UINT8 Reserved[8];\r | |
626 | UINT16 EfiImageHeaderOffset;\r | |
627 | UINT16 PcirOffset;\r | |
628 | } EFI_PCI_EXPANSION_ROM_HEADER;\r | |
629 | \r | |
630 | typedef union {\r | |
631 | UINT8 *Raw;\r | |
632 | PCI_EXPANSION_ROM_HEADER *Generic;\r | |
633 | EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r | |
634 | EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r | |
635 | } EFI_PCI_ROM_HEADER;\r | |
636 | \r | |
766f4bc1 | 637 | #pragma pack()\r |
638 | \r | |
a7ed1e2e | 639 | #endif\r |