| 73c31a3d |
1 | /** @file\r |
| 2 | This file declares PlatfromOpRom protocols which provides the interface between \r |
| 3 | the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific \r |
| 4 | driver to describe the unique features of a platform. This\r |
| 5 | protocol is optional.\r |
| 6 | \r |
| 7 | Copyright (c) 2007 - 2009, Intel Corporation\r |
| 8 | All rights reserved. This program and the accompanying materials\r |
| 9 | are licensed and made available under the terms and conditions of the BSD License\r |
| 10 | which accompanies this distribution. The full text of the license may be found at\r |
| 11 | http://opensource.org/licenses/bsd-license.php\r |
| 12 | \r |
| 13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 15 | \r |
| 16 | @par Revision Reference:\r |
| 17 | This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r |
| 18 | Volume 5: Standards\r |
| 19 | \r |
| 20 | **/\r |
| 21 | \r |
| 22 | #ifndef _PCI_PLATFORM_H_\r |
| 23 | #define _PCI_PLATFORM_H_\r |
| 24 | \r |
| 25 | ///\r |
| 26 | /// This file must be included because the EFI_PCI_PLATFORM_PROTOCOL uses\r |
| 27 | /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE\r |
| 28 | ///\r |
| 29 | #include <Protocol/PciHostBridgeResourceAllocation.h>\r |
| 30 | \r |
| 31 | ///\r |
| 32 | /// Global ID for the EFI_PCI_PLATFORM_PROTOCOL\r |
| 33 | ///\r |
| 34 | #define EFI_PCI_PLATFORM_PROTOCOL_GUID \\r |
| 35 | { \\r |
| 36 | 0x7d75280, 0x27d4, 0x4d69, {0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41} \\r |
| 37 | }\r |
| 38 | \r |
| 39 | ///\r |
| 40 | /// Forward declaration for EFI_PCI_PLATFORM_PROTOCOL\r |
| 41 | ///\r |
| 42 | typedef struct _EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_PLATFORM_PROTOCOL;\r |
| 43 | \r |
| 44 | ///\r |
| 45 | /// EFI_PCI_PLATYFORM_POLICY that is a bitmask with the following legal combinations:\r |
| 46 | /// - EFI_RESERVE_NONE_IO_ALIAS:<BR>\r |
| 47 | /// Does not set aside either ISA or VGA I/O resources during PCI\r |
| 48 | /// enumeration. By using this selection, the platform indicates that it does\r |
| 49 | /// not want to support a PCI device that requires ISA or legacy VGA\r |
| 50 | /// resources. If a PCI device driver asks for these resources, the request\r |
| 51 | /// will be turned down.\r |
| 52 | /// - EFI_RESERVE_ISA_IO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>\r |
| 53 | /// Sets aside the ISA I/O range and all the aliases during PCI\r |
| 54 | /// enumeration. VGA I/O ranges and aliases are included in ISA alias\r |
| 55 | /// ranges. In this scheme, 75 percent of the I/O space remains unused.\r |
| 56 | /// By using this selection, the platform indicates that it wants to support\r |
| 57 | /// PCI devices that require the following, at the cost of wasted I/O space:\r |
| 58 | /// ISA range and its aliases\r |
| 59 | /// Legacy VGA range and its aliases\r |
| 60 | /// The PCI bus driver will not allocate I/O addresses out of the ISA I/O\r |
| 61 | /// range and its aliases. The following are the ISA I/O ranges:\r |
| 62 | /// - n100..n3FF\r |
| 63 | /// - n500..n7FF\r |
| 64 | /// - n900..nBFF\r |
| 65 | /// - nD00..nFFF\r |
| 66 | ///\r |
| 67 | /// In this case, the PCI bus driver will ask the PCI host bridge driver for\r |
| 68 | /// larger I/O ranges. The PCI host bridge driver is not aware of the ISA\r |
| 69 | /// aliasing policy and merely attempts to allocate the requested ranges.\r |
| 70 | /// The first device that requests the legacy VGA range will get all the\r |
| 71 | /// legacy VGA range plus its aliased addresses forwarded to it. The first\r |
| 72 | /// device that requests the legacy ISA range will get all the legacy ISA\r |
| 73 | /// range plus its aliased addresses forwarded to it.\r |
| 74 | /// - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>\r |
| 75 |
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