| d0778dd7 |
1 | /** @file\r |
| 2 | EFI SMM CPU Protocol as defined in the PI 1.2 specification.\r |
| 3 | \r |
| 4 | This protocol allows SMM drivers to access architecture-standard registers from any of the CPU \r |
| 5 | save state areas. In some cases, difference processors provide the same information in the save state, \r |
| 6 | but not in the same format. These so-called pseudo-registers provide this information in a standard \r |
| 7 | format. \r |
| 8 | \r |
| 9 | Copyright (c) 2009, Intel Corporation \r |
| 10 | All rights reserved. This program and the accompanying materials \r |
| 11 | are licensed and made available under the terms and conditions of the BSD License \r |
| 12 | which accompanies this distribution. The full text of the license may be found at \r |
| 13 | http://opensource.org/licenses/bsd-license.php \r |
| 14 | \r |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 17 | \r |
| 18 | **/\r |
| 19 | \r |
| 20 | #ifndef _SMM_CPU_H_\r |
| 21 | #define _SMM_CPU_H_\r |
| 22 | \r |
| 23 | #include <Pi/PiSmmCis.h>\r |
| 24 | \r |
| 25 | #define EFI_SMM_CPU_PROTOCOL_GUID \\r |
| 26 | { \\r |
| 27 | 0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 } \\r |
| 28 | }\r |
| 29 | \r |
| 30 | ///\r |
| 31 | /// Save State register index\r |
| 32 | ///\r |
| 33 | typedef enum {\r |
| 34 | ///\r |
| 35 | /// x86/X64 standard registers\r |
| 36 | ///\r |
| 37 | EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4,\r |
| 38 | EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5,\r |
| 39 | EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6,\r |
| 40 | EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7,\r |
| 41 | EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8,\r |
| 42 | EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9,\r |
| 43 | EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10,\r |
| 44 | EFI_SMM_SAVE_STATE_REGISTER_ES = 20,\r |
| 45 | EFI_SMM_SAVE_STATE_REGISTER_CS = 21,\r |
| 46 | EFI_SMM_SAVE_STATE_REGISTER_SS = 22,\r |
| 47 | EFI_SMM_SAVE_STATE_REGISTER_DS = 23,\r |
| 48 | EFI_SMM_SAVE_STATE_REGISTER_FS = 24,\r |
| 49 | EFI_SMM_SAVE_STATE_REGISTER_GS = 25,\r |
| 50 | EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26,\r |
| 51 | EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27,\r |
| 52 | EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28,\r |
| 53 | EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29,\r |
| 54 | EFI_SMM_SAVE_STATE_REGISTER_R8 = 30,\r |
| 55 | EFI_SMM_SAVE_STATE_REGISTER_R9 = 31,\r |
| 56 | EFI_SMM_SAVE_STATE_REGISTER_R10 = 32,\r |
| 57 | EFI_SMM_SAVE_STATE_REGISTER_R11 = 33,\r |
| 58 | EFI_SMM_SAVE_STATE_REGISTER_R12 = 34,\r |
| 59 | EFI_SMM_SAVE_STATE_REGISTER_R13 = 35,\r |
| 60 | EFI_SMM_SAVE_STATE_REGISTER_R14 = 36,\r |
| 61 | EFI_SMM_SAVE_STATE_REGISTER_R15 = 37, \r |
| 62 | EFI_SMM_SAVE_STATE_REGISTER_RAX = 38,\r |
| 63 | EFI_SMM_SAVE_STATE_REGISTER_RBX = 39,\r |
| 64 | EFI_SMM_SAVE_STATE_REGISTER_RCX = 40,\r |
| 65 | EFI_SMM_SAVE_STATE_REGISTER_RDX = 41,\r |
| 66 | EFI_SMM_SAVE_STATE_REGISTER_RSP = 42,\r |
| 67 | EFI_SMM_SAVE_STATE_REGISTER_RBP = 43,\r |
| 68 | EFI_SMM_SAVE_STATE_REGISTER_RSI = 44,\r |
| 69 | EFI_SMM_SAVE_STATE_REGISTER_RDI = 45,\r |
| 70 | EFI_SMM_SAVE_STATE_REGISTER_RIP = 46,\r |
| 71 | EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51,\r |
| 72 | EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52,\r |
| 73 | EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53,\r |
| 74 | EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54,\r |
| 75 | EFI_SMM_SAVE_STATE_REGISTER_FCW = 256,\r |
| 76 | EFI_SMM_SAVE_STATE_REGISTER_FSW = 257,\r |
| 77 | EFI_SMM_SAVE_STATE_REGISTER_FTW = 258, \r |
| 78 | EFI_SMM_SAVE_STATE_REGISTER_OPCODE = 259,\r |
| 79 | EFI_SMM_SAVE_STATE_REGISTER_FP_EIP = 260,\r |
| 80 | EFI_SMM_SAVE_STATE_REGISTER_FP_CS = 261,\r |
| 81 | EFI_SMM_SAVE_STATE_REGISTER_DATAOFFSET = 262,\r |
| 82 | EFI_SMM_SAVE_STATE_REGISTER_FP_DS = 263,\r |
| 83 | EFI_SMM_SAVE_STATE_REGISTER_MM0 = 264,\r |
| 84 | EFI_SMM_SAVE_STATE_REGISTER_MM1 = 265,\r |
| 85 | EFI_SMM_SAVE_STATE_REGISTER_MM2 = 266,\r |
| 86 | EFI_SMM_SAVE_STATE_REGISTER_MM3 = 267,\r |
| 87 | EFI_SMM_SAVE_STATE_REGISTER_MM4 = 268,\r |
| 88 | EFI_SMM_SAVE_STATE_REGISTER_MM5 = 269,\r |
| 89 | EFI_SMM_SAVE_STATE_REGISTER_MM6 = 270,\r |
| 90 | EFI_SMM_SAVE_STATE_REGISTER_MM7 = 271,\r |
| 91 | EFI_SMM_SAVE_STATE_REGISTER_XMM0 = 272,\r |
| 92 | EFI_SMM_SAVE_STATE_REGISTER_XMM1 = 273,\r |
| 93 | EFI_SMM_SAVE_STATE_REGISTER_XMM2 = 274,\r |
| 94 | EFI_SMM_SAVE_STATE_REGISTER_XMM3 = 275,\r |
| 95 | EFI_SMM_SAVE_STATE_REGISTER_XMM4 = 276,\r |
| 96 | EFI_SMM_SAVE_STATE_REGISTER_XMM5 = 277,\r |
| 97 | EFI_SMM_SAVE_STATE_REGISTER_XMM6 = 278,\r |
| 98 | EFI_SMM_SAVE_STATE_REGISTER_XMM7 = 279,\r |
| 99 | EFI_SMM_SAVE_STATE_REGISTER_XMM8 = 280,\r |
| 100 | EFI_SMM_SAVE_STATE_REGISTER_XMM9 = 281,\r |
| 101 | EFI_SMM_SAVE_STATE_REGISTER_XMM10 = 282,\r |
| 102 | EFI_SMM_SAVE_STATE_REGISTER_XMM11 = 283,\r |
| 103 | EFI_SMM_SAVE_STATE_REGISTER_XMM12 = 284,\r |
| 104 | EFI_SMM_SAVE_STATE_REGISTER_XMM13 = 285,\r |
| 105 | EFI_SMM_SAVE_STATE_REGISTER_XMM14 = 286,\r |
| 106 | EFI_SMM_SAVE_STATE_REGISTER_XMM15 = 287, \r |
| 107 | ///\r |
| 108 | /// Pseudo-Registers\r |
| 109 | ///\r |
| 110 | EFI_SMM_SAVE_STATE_REGISTER_IO = 512,\r |
| 111 | EFI_SMM_SAVE_STATE_REGISTER_LMA = 513\r |
| 112 | } EFI_SMM_SAVE_STATE_REGISTER; \r |
| 113 | \r |
| 114 | ///\r |
| 115 | /// The EFI_SMM_SAVE_STATE_REGISTER_LMA pseudo-register values\r |
| 116 | /// If the processor acts in 32-bit mode at the time the SMI occurred, the pseudo register value \r |
| 117 | /// EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT is returned in Buffer. Otherwise, \r |
| 118 | /// EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer.\r |
| 119 | ///\r |
| 120 | #define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT 32\r |
| 121 | #define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT 64\r |
| 122 | \r |
| 123 | ///\r |
| 124 | /// Size width of I/O instruction\r |
| 125 | ///\r |
| 126 | typedef enum {\r |
| 127 | EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 = 0,\r |
| 128 | EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 = 1,\r |
| 129 | EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 = 2,\r |
| 130 | EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64 = 3\r |
| 131 | } EFI_SMM_SAVE_STATE_IO_WIDTH;\r |
| 132 | \r |
| 133 | ///\r |
| 134 | /// Types of I/O instruction\r |
| 135 | ///\r |
| 136 | typedef enum {\r |
| 137 | EFI_SMM_SAVE_STATE_IO_TYPE_INPUT = 1,\r |
| 138 | EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT = 2,\r |
| 139 | EFI_SMM_SAVE_STATE_IO_TYPE_STRING = 4,\r |
| 140 | EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8\r |
| 141 | } EFI_SMM_SAVE_STATE_IO_TYPE;\r |
| 142 | \r |
| 143 | ///\r |
| 144 | /// Structure of the data which is returned when ReadSaveState() is called with \r |
| 145 | /// EFI_SMM_SAVE_STATE_REGISTER_IO. If there was no I/O then ReadSaveState() will \r |
| 146 | /// return EFI_NOT_FOUND.\r |
| 147 | ///\r |
| 148 | /// This structure describes the I/O operation which was in process when the SMI was generated.\r |
| 149 | ///\r |
| 150 | typedef struct _EFI_SMM_SAVE_STATE_IO_INFO {\r |
| 151 | ///\r |
| 152 | /// For input instruction (IN, INS), this is data read before the SMI occurred. For output \r |
| 153 | /// instructions (OUT, OUTS) this is data that was written before the SMI occurred. The \r |
| 154 | /// width of the data is specified by IoWidth.\r |
| 155 | ///\r |
| 156 | /// Note: inconsistency with PI 1.2 spec here. wait for spec update.\r |
| 157 | ///\r |
| 158 | UINTN IoData;\r |
| 159 | ///\r |
| 160 | /// The I/O port that was being accessed when the SMI was triggered.\r |
| 161 | ///\r |
| 162 | UINT16 IoPort;\r |
| 163 | ///\r |
| 164 | /// Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData.\r |
| 165 | ///\r |
| 166 | EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth;\r |
| 167 | ///\r |
| 168 | /// Defines type of I/O instruction.\r |
| 169 | ///\r |
| 170 | EFI_SMM_SAVE_STATE_IO_TYPE IoType;\r |
| 171 | } EFI_SMM_SAVE_STATE_IO_INFO;\r |
| 172 | \r |
| 173 | typedef struct _EFI_SMM_CPU_PROTOCOL EFI_SMM_CPU_PROTOCOL;\r |
| 174 | \r |
| 175 | /**\r |
| 176 | Read data from the CPU save state.\r |
| 177 | \r |
| 178 | This function is used to read the specified number of bytes of the specified register from the CPU \r |
| 179 | save state of the specified CPU and place the value into the buffer. If the CPU does not support the\r |
| 180 | specified register Register, then EFI_NOT_FOUND should be returned. If the CPU does not \r |
| 181 | support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r |
| 182 | \r |
| 183 | @param[in] This The EFI_SMM_CPU_PROTOCOL instance.\r |
| 184 | @param[in] Width The number of bytes to read from the CPU save state.\r |
| 185 | @param[in] Register Specifies the CPU register to read form the save state.\r |
| 186 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r |
| 187 | @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r |
| 188 | \r |
| 189 | @retval EFI_SUCCESS The register was read from Save State.\r |
| 190 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r |
| 191 | @retval EFI_INVALID_PARAMETER Input parameters are not valid, for example, Processor No or register width \r |
| 192 | is not correct.This or Buffer is NULL.\r |
| 193 | **/\r |
| 194 | typedef\r |
| 195 | EFI_STATUS\r |
| 196 | (EFIAPI *EFI_SMM_READ_SAVE_STATE)(\r |
| 197 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r |
| 198 | IN UINTN Width,\r |
| 199 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r |
| 200 | IN UINTN CpuIndex,\r |
| 201 | OUT VOID *Buffer\r |
| 202 | );\r |
| 203 | \r |
| 204 | \r |
| 205 | /**\r |
| 206 | Write data to the CPU save state.\r |
| 207 | \r |
| 208 | This function is used to write the specified number of bytes of the specified register to the CPU save \r |
| 209 | state of the specified CPU and place the value into the buffer. If the CPU does not support the \r |
| 210 | specified register Register, then EFI_UNSUPPORTED should be returned. If the CPU does not \r |
| 211 | support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r |
| 212 | \r |
| 213 | @param[in] This The EFI_SMM_CPU_PROTOCOL instance.\r |
| 214 | @param[in] Width The number of bytes to write to the CPU save state.\r |
| 215 | @param[in] Register Specifies the CPU register to write to the save state.\r |
| 216 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r |
| 217 | @param[in] Buffer Upon entry, this holds the new CPU register value.\r |
| 218 | \r |
| 219 | @retval EFI_SUCCESS The register was written to Save State.\r |
| 220 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r |
| 221 | @retval EFI_INVALID_PARAMETER Input parameters are not valid. For example: \r |
| 222 | ProcessorIndex or Width is not correct.\r |
| 223 | **/\r |
| 224 | typedef\r |
| 225 | EFI_STATUS\r |
| 226 | (EFIAPI *EFI_SMM_WRITE_SAVE_STATE)(\r |
| 227 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r |
| 228 | IN UINTN Width, \r |
| 229 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r |
| 230 | IN UINTN CpuIndex,\r |
| 231 | IN CONST VOID *Buffer\r |
| 232 | );\r |
| 233 | \r |
| 234 | ///\r |
| 235 | /// EFI SMM CPU Protocol provides access to CPU-related information while in SMM.\r |
| 236 | ///\r |
| 237 | /// This protocol allows SMM drivers to access architecture-standard registers from any of the CPU \r |
| 238 | /// save state areas. In some cases, difference processors provide the same information in the save state, \r |
| 239 | /// but not in the same format. These so-called pseudo-registers provide this information in a standard \r |
| 240 | /// format. \r |
| 241 | ///\r |
| 242 | struct _EFI_SMM_CPU_PROTOCOL {\r |
| 243 | EFI_SMM_READ_SAVE_STATE ReadSaveState;\r |
| 244 | EFI_SMM_WRITE_SAVE_STATE WriteSaveState;\r |
| 245 | };\r |
| 246 | \r |
| 247 | extern EFI_GUID gEfiSmmCpuProtocolGuid;\r |
| 248 | \r |
| 249 | #endif\r |
| 250 | \r |
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