[mirror_edk2.git] / MdePkg / Include / Register / Intel / Msr / XeonE7Msr.h

/** @file\r
  MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
#ifndef __XEON_E7_MSR_H__\r
#define __XEON_E7_MSR_H__\r
\r
#include <Register/Intel/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel(R) Xeon(R) Processor E7 Family?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x2F    \\r
    )                       \\r
   )\r
\r
/**\r
  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
  handler to handle unsuccessful read of this MSR.\r
\r
  @param  ECX  MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_XEON_E7_FEATURE_CONFIG_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r
  AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r
  @endcode\r
  @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
#define MSR_XEON_E7_FEATURE_CONFIG  0x0000013C\r
\r
/**\r
  MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this\r
    /// MSR, the configuration of AES instruction set availability is as\r
    /// follows: 11b: AES instructions are not available until next RESET.\r
    /// otherwise, AES instructions are available. Note, AES instruction set\r
    /// is not available if read is unsuccessful. If the configuration is not\r
    /// 01b, AES instruction can be mis-configured if a privileged agent\r
    /// unintentionally writes 11b.\r
    ///\r
    UINT32    AESConfiguration : 2;\r
    UINT32    Reserved1        : 30;\r
    UINT32    Reserved2        : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
\r
/**\r
  Thread. Offcore Response Event Select Register (R/W).\r
\r
  @param  ECX  MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r
  AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
#define MSR_XEON_E7_OFFCORE_RSP_1  0x000001A7\r
\r
/**\r
  Package. Reserved Attempt to read/write will cause #UD.\r
\r
  @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r
  AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_XEON_E7_TURBO_RATIO_LIMIT  0x000001AD\r
\r
/**\r
  Package. Uncore C-box 8 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_XEON_E7_C8_PMON_BOX_CTRL  0x00000F40\r
\r
/**\r
  Package. Uncore C-box 8 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_XEON_E7_C8_PMON_BOX_STATUS  0x00000F41\r
\r
/**\r
  Package. Uncore C-box 8 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL  0x00000F42\r
\r
/**\r
  Package. Uncore C-box 8 perfmon event select MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.\r
        MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
  @{\r
**/\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL0  0x00000F50\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL1  0x00000F52\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL2  0x00000F54\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL3  0x00000F56\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL4  0x00000F58\r
#define MSR_XEON_E7_C8_PMON_EVNT_SEL5  0x00000F5A\r
/// @}\r
\r
/**\r
  Package. Uncore C-box 8 perfmon counter MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C8_PMON_CTRn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.\r
        MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
  @{\r
**/\r
#define MSR_XEON_E7_C8_PMON_CTR0  0x00000F51\r
#define MSR_XEON_E7_C8_PMON_CTR1  0x00000F53\r
#define MSR_XEON_E7_C8_PMON_CTR2  0x00000F55\r
#define MSR_XEON_E7_C8_PMON_CTR3  0x00000F57\r
#define MSR_XEON_E7_C8_PMON_CTR4  0x00000F59\r
#define MSR_XEON_E7_C8_PMON_CTR5  0x00000F5B\r
/// @}\r
\r
/**\r
  Package. Uncore C-box 9 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_XEON_E7_C9_PMON_BOX_CTRL  0x00000FC0\r
\r
/**\r
  Package. Uncore C-box 9 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_XEON_E7_C9_PMON_BOX_STATUS  0x00000FC1\r
\r
/**\r
  Package. Uncore C-box 9 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL  0x00000FC2\r
\r
/**\r
  Package. Uncore C-box 9 perfmon event select MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_EVNT_SELn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.\r
        MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
  @{\r
**/\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL0  0x00000FD0\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL1  0x00000FD2\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL2  0x00000FD4\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL3  0x00000FD6\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL4  0x00000FD8\r
#define MSR_XEON_E7_C9_PMON_EVNT_SEL5  0x00000FDA\r
/// @}\r
\r
/**\r
  Package. Uncore C-box 9 perfmon counter MSR.\r
\r
  @param  ECX  MSR_XEON_E7_C9_PMON_CTRn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.\r
        MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
  @{\r
**/\r
#define MSR_XEON_E7_C9_PMON_CTR0  0x00000FD1\r
#define MSR_XEON_E7_C9_PMON_CTR1  0x00000FD3\r
#define MSR_XEON_E7_C9_PMON_CTR2  0x00000FD5\r
#define MSR_XEON_E7_C9_PMON_CTR3  0x00000FD7\r
#define MSR_XEON_E7_C9_PMON_CTR4  0x00000FD9\r
#define MSR_XEON_E7_C9_PMON_CTR5  0x00000FDB\r
/// @}\r
\r
#endif\r
Commit	Line	Data
ebb74e4a MK	1	/** @file\r
	2	MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.\r
	3	\r
	4	Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
	5	are provided for MSRs that contain one or more bit fields. If the MSR value\r
	6	returned is a single 32-bit or 64-bit value, then a data structure is not\r
	7	provided for that MSR.\r
	8	\r
e057908f	9	Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
0acd8697	10	SPDX-License-Identifier: BSD-2-Clause-Patent\r
ebb74e4a MK	11	\r
ebb74e4a MK	12	@par Specification Reference:\r
ba1a2d11 ED	13	Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
ba1a2d11 ED	14	May 2018, Volume 4: Model-Specific-Registers (MSR)\r
ebb74e4a MK	15	\r
	16	**/\r
	17	\r
	18	#ifndef __XEON_E7_MSR_H__\r
	19	#define __XEON_E7_MSR_H__\r
	20	\r
e057908f	21	#include <Register/Intel/ArchitecturalMsr.h>\r
ebb74e4a	22	\r
f4c982bf JF	23	/**\r
	24	Is Intel(R) Xeon(R) Processor E7 Family?\r
	25	\r
	26	@param DisplayFamily Display Family ID\r
	27	@param DisplayModel Display Model ID\r
	28	\r
	29	@retval TRUE Yes, it is.\r
	30	@retval FALSE No, it isn't.\r
	31	**/\r
	32	#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \\r
	33	(DisplayFamily == 0x06 && \\r
	34	( \\r
	35	DisplayModel == 0x2F \\r
	36	) \\r
	37	)\r
	38	\r
0f16be6d HW	39	/**\r
	40	Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
	41	handler to handle unsuccessful read of this MSR.\r
	42	\r
	43	@param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r
	44	@param EAX Lower 32-bits of MSR value.\r
	45	Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
	46	@param EDX Upper 32-bits of MSR value.\r
	47	Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
	48	\r
	49	<b>Example usage</b>\r
	50	@code\r
	51	MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;\r
	52	\r
	53	Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r
	54	AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r
	55	@endcode\r
	56	@note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
	57	**/\r
2f88bd3a	58	#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C\r
0f16be6d HW	59	\r
	60	/**\r
	61	MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
	62	**/\r
	63	typedef union {\r
	64	///\r
	65	/// Individual bit fields\r
	66	///\r
	67	struct {\r
	68	///\r
	69	/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
	70	/// MSR, the configuration of AES instruction set availability is as\r
	71	/// follows: 11b: AES instructions are not available until next RESET.\r
	72	/// otherwise, AES instructions are available. Note, AES instruction set\r
	73	/// is not available if read is unsuccessful. If the configuration is not\r
	74	/// 01b, AES instruction can be mis-configured if a privileged agent\r
	75	/// unintentionally writes 11b.\r
	76	///\r
2f88bd3a MK	77	UINT32 AESConfiguration : 2;\r
	78	UINT32 Reserved1 : 30;\r
	79	UINT32 Reserved2 : 32;\r
0f16be6d HW	80	} Bits;\r
	81	///\r
	82	/// All bit fields as a 32-bit value\r
	83	///\r
2f88bd3a	84	UINT32 Uint32;\r
0f16be6d HW	85	///\r
	86	/// All bit fields as a 64-bit value\r
	87	///\r
2f88bd3a	88	UINT64 Uint64;\r
0f16be6d HW	89	} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
0f16be6d HW	90	\r
0f16be6d HW	91	/**\r
	92	Thread. Offcore Response Event Select Register (R/W).\r
	93	\r
	94	@param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r
	95	@param EAX Lower 32-bits of MSR value.\r
	96	@param EDX Upper 32-bits of MSR value.\r
	97	\r
	98	<b>Example usage</b>\r
	99	@code\r
	100	UINT64 Msr;\r
	101	\r
	102	Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r
	103	AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r
	104	@endcode\r
	105	@note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
	106	**/\r
2f88bd3a	107	#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7\r
0f16be6d	108	\r
ebb74e4a MK	109	/**\r
	110	Package. Reserved Attempt to read/write will cause #UD.\r
	111	\r
	112	@param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)\r
	113	@param EAX Lower 32-bits of MSR value.\r
	114	@param EDX Upper 32-bits of MSR value.\r
	115	\r
	116	<b>Example usage</b>\r
	117	@code\r
	118	UINT64 Msr;\r
	119	\r
	120	Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r
	121	AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r
	122	@endcode\r
97ea5b7f	123	@note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
ebb74e4a	124	**/\r
2f88bd3a	125	#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD\r
ebb74e4a MK	126	\r
	127	/**\r
	128	Package. Uncore C-box 8 perfmon local box control MSR.\r
	129	\r
	130	@param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)\r
	131	@param EAX Lower 32-bits of MSR value.\r
	132	@param EDX Upper 32-bits of MSR value.\r
	133	\r
	134	<b>Example usage</b>\r
	135	@code\r
	136	UINT64 Msr;\r
	137	\r
	138	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r
	139	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r
	140	@endcode\r
97ea5b7f	141	@note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
ebb74e4a	142	**/\r
2f88bd3a	143	#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40\r
ebb74e4a MK	144	\r
	145	/**\r
	146	Package. Uncore C-box 8 perfmon local box status MSR.\r
	147	\r
	148	@param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)\r
	149	@param EAX Lower 32-bits of MSR value.\r
	150	@param EDX Upper 32-bits of MSR value.\r
	151	\r
	152	<b>Example usage</b>\r
	153	@code\r
	154	UINT64 Msr;\r
	155	\r
	156	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r
	157	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r
	158	@endcode\r
97ea5b7f	159	@note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
ebb74e4a	160	**/\r
2f88bd3a	161	#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41\r
ebb74e4a MK	162	\r
	163	/**\r
	164	Package. Uncore C-box 8 perfmon local box overflow control MSR.\r
	165	\r
	166	@param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)\r
	167	@param EAX Lower 32-bits of MSR value.\r
	168	@param EDX Upper 32-bits of MSR value.\r
	169	\r
	170	<b>Example usage</b>\r
	171	@code\r
	172	UINT64 Msr;\r
	173	\r
	174	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r
	175	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r
	176	@endcode\r
97ea5b7f	177	@note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
ebb74e4a	178	**/\r
2f88bd3a	179	#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42\r
ebb74e4a MK	180	\r
	181	/**\r
	182	Package. Uncore C-box 8 perfmon event select MSR.\r
	183	\r
	184	@param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn\r
	185	@param EAX Lower 32-bits of MSR value.\r
	186	@param EDX Upper 32-bits of MSR value.\r
	187	\r
	188	<b>Example usage</b>\r
	189	@code\r
	190	UINT64 Msr;\r
	191	\r
	192	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r
	193	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r
	194	@endcode\r
97ea5b7f JF	195	@note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.\r
	196	MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.\r
	197	MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.\r
	198	MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.\r
	199	MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.\r
	200	MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
ebb74e4a MK	201	@{\r
ebb74e4a MK	202	**/\r
2f88bd3a MK	203	#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50\r
	204	#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52\r
	205	#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54\r
	206	#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56\r
	207	#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58\r
	208	#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A\r
ebb74e4a MK	209	/// @}\r
ebb74e4a MK	210	\r
ebb74e4a MK	211	/**\r
	212	Package. Uncore C-box 8 perfmon counter MSR.\r
	213	\r
	214	@param ECX MSR_XEON_E7_C8_PMON_CTRn\r
	215	@param EAX Lower 32-bits of MSR value.\r
	216	@param EDX Upper 32-bits of MSR value.\r
	217	\r
	218	<b>Example usage</b>\r
	219	@code\r
	220	UINT64 Msr;\r
	221	\r
	222	Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r
	223	AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r
	224	@endcode\r
97ea5b7f JF	225	@note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
	226	MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
	227	MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
	228	MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
	229	MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.\r
	230	MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
ebb74e4a MK	231	@{\r
ebb74e4a MK	232	**/\r
2f88bd3a MK	233	#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51\r
	234	#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53\r
	235	#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55\r
	236	#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57\r
	237	#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59\r
	238	#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B\r
ebb74e4a MK	239	/// @}\r
ebb74e4a MK	240	\r
ebb74e4a MK	241	/**\r
	242	Package. Uncore C-box 9 perfmon local box control MSR.\r
	243	\r
	244	@param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)\r
	245	@param EAX Lower 32-bits of MSR value.\r
	246	@param EDX Upper 32-bits of MSR value.\r
	247	\r
	248	<b>Example usage</b>\r
	249	@code\r
	250	UINT64 Msr;\r
	251	\r
	252	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r
	253	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r
	254	@endcode\r
97ea5b7f	255	@note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
ebb74e4a	256	**/\r
2f88bd3a	257	#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0\r
ebb74e4a MK	258	\r
	259	/**\r
	260	Package. Uncore C-box 9 perfmon local box status MSR.\r
	261	\r
	262	@param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)\r
	263	@param EAX Lower 32-bits of MSR value.\r
	264	@param EDX Upper 32-bits of MSR value.\r
	265	\r
	266	<b>Example usage</b>\r
	267	@code\r
	268	UINT64 Msr;\r
	269	\r
	270	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r
	271	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r
	272	@endcode\r
97ea5b7f	273	@note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
ebb74e4a	274	**/\r
2f88bd3a	275	#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1\r
ebb74e4a MK	276	\r
	277	/**\r
	278	Package. Uncore C-box 9 perfmon local box overflow control MSR.\r
	279	\r
	280	@param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)\r
	281	@param EAX Lower 32-bits of MSR value.\r
	282	@param EDX Upper 32-bits of MSR value.\r
	283	\r
	284	<b>Example usage</b>\r
	285	@code\r
	286	UINT64 Msr;\r
	287	\r
	288	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r
	289	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r
	290	@endcode\r
97ea5b7f	291	@note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
ebb74e4a	292	**/\r
2f88bd3a	293	#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2\r
ebb74e4a MK	294	\r
	295	/**\r
	296	Package. Uncore C-box 9 perfmon event select MSR.\r
	297	\r
	298	@param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn\r
	299	@param EAX Lower 32-bits of MSR value.\r
	300	@param EDX Upper 32-bits of MSR value.\r
	301	\r
	302	<b>Example usage</b>\r
	303	@code\r
	304	UINT64 Msr;\r
	305	\r
	306	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r
	307	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r
	308	@endcode\r
97ea5b7f JF	309	@note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.\r
	310	MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.\r
	311	MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.\r
	312	MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.\r
	313	MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.\r
	314	MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
ebb74e4a MK	315	@{\r
ebb74e4a MK	316	**/\r
2f88bd3a MK	317	#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0\r
	318	#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2\r
	319	#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4\r
	320	#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6\r
	321	#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8\r
	322	#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA\r
ebb74e4a MK	323	/// @}\r
ebb74e4a MK	324	\r
ebb74e4a MK	325	/**\r
	326	Package. Uncore C-box 9 perfmon counter MSR.\r
	327	\r
	328	@param ECX MSR_XEON_E7_C9_PMON_CTRn\r
	329	@param EAX Lower 32-bits of MSR value.\r
	330	@param EDX Upper 32-bits of MSR value.\r
	331	\r
	332	<b>Example usage</b>\r
	333	@code\r
	334	UINT64 Msr;\r
	335	\r
	336	Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r
	337	AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r
	338	@endcode\r
97ea5b7f JF	339	@note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
	340	MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
	341	MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
	342	MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
	343	MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.\r
	344	MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
ebb74e4a MK	345	@{\r
ebb74e4a MK	346	**/\r
2f88bd3a MK	347	#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1\r
	348	#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3\r
	349	#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5\r
	350	#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7\r
	351	#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9\r
	352	#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB\r
ebb74e4a MK	353	/// @}\r
	354	\r
	355	#endif\r