MdePkg/ProcessorBind: add defines for page allocation granularity
[mirror_edk2.git] / MdePkg / Include / Uefi / UefiPxe.h
CommitLineData
959ccb23 1/** @file\r
2 This header file contains all of the PXE type definitions,\r
3 structure prototypes, global variables and constants that\r
4 are needed for porting PXE to EFI.\r
4ccd9566 5\r
b4bddb6e 6Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
af2dc6a7 7This program and the accompanying materials are licensed and made available under \r
8the terms and conditions of the BSD License that accompanies this distribution. \r
9The full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php. \r
11 \r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
4ccd9566 14\r
959ccb23 15 @par Revision Reference:\r
16 32/64-bit PXE specification:\r
af2dc6a7 17 alpha-4, 99-Dec-17.\r
993702aa 18\r
959ccb23 19**/\r
20\r
21#ifndef __EFI_PXE_H__\r
22#define __EFI_PXE_H__\r
23\r
24#pragma pack(1)\r
25\r
959ccb23 26#define PXE_BUSTYPE(a, b, c, d) \\r
27 ( \\r
28 (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \\r
29 ((PXE_UINT32) (a) & 0xFF) \\r
30 )\r
31\r
8b13229b 32///\r
af2dc6a7 33/// UNDI ROM ID and devive ID signature.\r
8b13229b 34///\r
959ccb23 35#define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r
36\r
8b13229b 37///\r
af2dc6a7 38/// BUS ROM ID signatures.\r
8b13229b 39///\r
959ccb23 40#define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')\r
41#define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')\r
42#define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')\r
43#define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')\r
44\r
45#define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))\r
46\r
47#define PXE_SWAP_UINT32(n) \\r
48 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \\r
49 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \\r
50 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \\r
51 (((PXE_UINT32)(n) & 0xFF000000) >> 24))\r
52\r
53#define PXE_SWAP_UINT64(n) \\r
54 ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \\r
55 (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \\r
56 (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \\r
57 (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \\r
58 (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \\r
59 (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \\r
60 (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \\r
61 (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))\r
62\r
63\r
3ed785e9 64#define PXE_CPBSIZE_NOT_USED 0 ///< zero\r
65#define PXE_DBSIZE_NOT_USED 0 ///< zero\r
66#define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 ///< zero\r
67#define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 ///< zero\r
68#define PXE_CONST CONST\r
959ccb23 69\r
70#define PXE_VOLATILE volatile\r
71\r
72typedef VOID PXE_VOID;\r
73typedef UINT8 PXE_UINT8;\r
74typedef UINT16 PXE_UINT16;\r
75typedef UINT32 PXE_UINT32;\r
76typedef UINTN PXE_UINTN;\r
4ccd9566 77\r
8b13229b 78///\r
af2dc6a7 79/// Typedef unsigned long PXE_UINT64.\r
8b13229b 80///\r
959ccb23 81typedef UINT64 PXE_UINT64;\r
82\r
83typedef PXE_UINT8 PXE_BOOL;\r
3ed785e9 84#define PXE_FALSE 0 ///< zero\r
959ccb23 85#define PXE_TRUE (!PXE_FALSE)\r
86\r
87typedef PXE_UINT16 PXE_OPCODE;\r
88\r
8b13229b 89///\r
90/// Return UNDI operational state.\r
91///\r
959ccb23 92#define PXE_OPCODE_GET_STATE 0x0000\r
93\r
8b13229b 94///\r
95/// Change UNDI operational state from Stopped to Started.\r
96///\r
959ccb23 97#define PXE_OPCODE_START 0x0001\r
98\r
8b13229b 99///\r
100/// Change UNDI operational state from Started to Stopped.\r
101///\r
959ccb23 102#define PXE_OPCODE_STOP 0x0002\r
103\r
8b13229b 104///\r
105/// Get UNDI initialization information.\r
106///\r
959ccb23 107#define PXE_OPCODE_GET_INIT_INFO 0x0003\r
108\r
8b13229b 109///\r
110/// Get NIC configuration information.\r
111///\r
959ccb23 112#define PXE_OPCODE_GET_CONFIG_INFO 0x0004\r
113\r
8b13229b 114///\r
115/// Changed UNDI operational state from Started to Initialized.\r
116///\r
959ccb23 117#define PXE_OPCODE_INITIALIZE 0x0005\r
118\r
8b13229b 119///\r
120/// Re-initialize the NIC H/W.\r
121///\r
959ccb23 122#define PXE_OPCODE_RESET 0x0006\r
123\r
8b13229b 124///\r
125/// Change the UNDI operational state from Initialized to Started.\r
126///\r
959ccb23 127#define PXE_OPCODE_SHUTDOWN 0x0007\r
128\r
8b13229b 129///\r
130/// Read & change state of external interrupt enables.\r
131///\r
959ccb23 132#define PXE_OPCODE_INTERRUPT_ENABLES 0x0008\r
133\r
8b13229b 134///\r
135/// Read & change state of packet receive filters.\r
136///\r
959ccb23 137#define PXE_OPCODE_RECEIVE_FILTERS 0x0009\r
138\r
8b13229b 139///\r
140/// Read & change station MAC address.\r
141///\r
959ccb23 142#define PXE_OPCODE_STATION_ADDRESS 0x000A\r
143\r
8b13229b 144///\r
145/// Read traffic statistics.\r
146///\r
959ccb23 147#define PXE_OPCODE_STATISTICS 0x000B\r
148\r
8b13229b 149///\r
150/// Convert multicast IP address to multicast MAC address.\r
151///\r
959ccb23 152#define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C\r
153\r
8b13229b 154///\r
155/// Read or change non-volatile storage on the NIC.\r
156///\r
959ccb23 157#define PXE_OPCODE_NVDATA 0x000D\r
158\r
8b13229b 159///\r
160/// Get & clear interrupt status.\r
161///\r
959ccb23 162#define PXE_OPCODE_GET_STATUS 0x000E\r
163\r
8b13229b 164///\r
165/// Fill media header in packet for transmit.\r
166///\r
959ccb23 167#define PXE_OPCODE_FILL_HEADER 0x000F\r
168\r
8b13229b 169///\r
170/// Transmit packet(s).\r
171///\r
959ccb23 172#define PXE_OPCODE_TRANSMIT 0x0010\r
173\r
8b13229b 174///\r
175/// Receive packet.\r
176///\r
959ccb23 177#define PXE_OPCODE_RECEIVE 0x0011\r
178\r
8b13229b 179///\r
180/// Last valid PXE UNDI OpCode number.\r
181///\r
959ccb23 182#define PXE_OPCODE_LAST_VALID 0x0011\r
183\r
184typedef PXE_UINT16 PXE_OPFLAGS;\r
185\r
186#define PXE_OPFLAGS_NOT_USED 0x0000\r
187\r
188//\r
189// //////////////////////////////////////\r
190// UNDI Get State\r
191//\r
192// No OpFlags\r
193\r
194////////////////////////////////////////\r
195// UNDI Start\r
196//\r
197// No OpFlags\r
198\r
199////////////////////////////////////////\r
200// UNDI Stop\r
201//\r
202// No OpFlags\r
203\r
204////////////////////////////////////////\r
205// UNDI Get Init Info\r
206//\r
207// No Opflags\r
208\r
209////////////////////////////////////////\r
210// UNDI Get Config Info\r
211//\r
212// No Opflags\r
213\r
3ed785e9 214///\r
215/// UNDI Initialize\r
216///\r
959ccb23 217#define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001\r
218#define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000\r
219#define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001\r
220\r
3ed785e9 221///\r
222///\r
223/// UNDI Reset\r
224///\r
959ccb23 225#define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001\r
226#define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002\r
227\r
3ed785e9 228///\r
af2dc6a7 229/// UNDI Shutdown.\r
3ed785e9 230///\r
af2dc6a7 231/// No OpFlags.\r
959ccb23 232\r
3ed785e9 233///\r
af2dc6a7 234/// UNDI Interrupt Enables.\r
3ed785e9 235///\r
236///\r
237/// Select whether to enable or disable external interrupt signals.\r
238/// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.\r
239///\r
959ccb23 240#define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000\r
241#define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000\r
242#define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000\r
243#define PXE_OPFLAGS_INTERRUPT_READ 0x0000\r
244\r
8b13229b 245///\r
246/// Enable receive interrupts. An external interrupt will be generated\r
247/// after a complete non-error packet has been received.\r
248///\r
959ccb23 249#define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001\r
250\r
8b13229b 251///\r
252/// Enable transmit interrupts. An external interrupt will be generated\r
253/// after a complete non-error packet has been transmitted.\r
254///\r
959ccb23 255#define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002\r
256\r
8b13229b 257///\r
258/// Enable command interrupts. An external interrupt will be generated\r
259/// when command execution stops.\r
260///\r
959ccb23 261#define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004\r
262\r
8b13229b 263///\r
264/// Generate software interrupt. Setting this bit generates an external\r
265/// interrupt, if it is supported by the hardware.\r
266///\r
959ccb23 267#define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008\r
268\r
4ccd9566 269///\r
af2dc6a7 270/// UNDI Receive Filters.\r
3ed785e9 271///\r
272///\r
273/// Select whether to enable or disable receive filters.\r
274/// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.\r
275///\r
959ccb23 276#define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000\r
277#define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000\r
278#define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000\r
279#define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000\r
280\r
8b13229b 281///\r
282/// To reset the contents of the multicast MAC address filter list,\r
283/// set this OpFlag:\r
284///\r
959ccb23 285#define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000\r
286\r
8b13229b 287///\r
288/// Enable unicast packet receiving. Packets sent to the current station\r
289/// MAC address will be received.\r
290///\r
959ccb23 291#define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r
292\r
8b13229b 293///\r
294/// Enable broadcast packet receiving. Packets sent to the broadcast\r
295/// MAC address will be received.\r
296///\r
959ccb23 297#define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r
298\r
8b13229b 299///\r
300/// Enable filtered multicast packet receiving. Packets sent to any\r
301/// of the multicast MAC addresses in the multicast MAC address filter\r
302/// list will be received. If the filter list is empty, no multicast\r
303///\r
959ccb23 304#define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r
305\r
8b13229b 306///\r
307/// Enable promiscuous packet receiving. All packets will be received.\r
308///\r
959ccb23 309#define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r
310\r
8b13229b 311///\r
312/// Enable promiscuous multicast packet receiving. All multicast\r
313/// packets will be received.\r
314///\r
959ccb23 315#define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r
316\r
4ccd9566 317///\r
af2dc6a7 318/// UNDI Station Address.\r
3ed785e9 319///\r
959ccb23 320#define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000\r
321#define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000\r
322#define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001\r
323\r
3ed785e9 324///\r
af2dc6a7 325/// UNDI Statistics.\r
3ed785e9 326///\r
959ccb23 327#define PXE_OPFLAGS_STATISTICS_READ 0x0000\r
328#define PXE_OPFLAGS_STATISTICS_RESET 0x0001\r
329\r
3ed785e9 330///\r
af2dc6a7 331/// UNDI MCast IP to MAC.\r
3ed785e9 332///\r
333///\r
334/// Identify the type of IP address in the CPB.\r
335///\r
959ccb23 336#define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003\r
337#define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000\r
338#define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001\r
339\r
3ed785e9 340///\r
af2dc6a7 341/// UNDI NvData.\r
3ed785e9 342///\r
343///\r
344/// Select the type of non-volatile data operation.\r
345///\r
959ccb23 346#define PXE_OPFLAGS_NVDATA_OPMASK 0x0001\r
347#define PXE_OPFLAGS_NVDATA_READ 0x0000\r
348#define PXE_OPFLAGS_NVDATA_WRITE 0x0001\r
349\r
3ed785e9 350///\r
af2dc6a7 351/// UNDI Get Status.\r
3ed785e9 352///\r
353///\r
354/// Return current interrupt status. This will also clear any interrupts\r
355/// that are currently set. This can be used in a polling routine. The\r
356/// interrupt flags are still set and cleared even when the interrupts\r
357/// are disabled.\r
358///\r
959ccb23 359#define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001\r
360\r
3ed785e9 361///\r
362/// Return list of transmitted buffers for recycling. Transmit buffers\r
363/// must not be changed or unallocated until they have recycled. After\r
364/// issuing a transmit command, wait for a transmit complete interrupt.\r
365/// When a transmit complete interrupt is received, read the transmitted\r
366/// buffers. Do not plan on getting one buffer per interrupt. Some\r
367/// NICs and UNDIs may transmit multiple buffers per interrupt.\r
368///\r
959ccb23 369#define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002\r
370\r
993702aa 371///\r
372/// Return current media status.\r
373///\r
374#define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004\r
375\r
3ed785e9 376///\r
af2dc6a7 377/// UNDI Fill Header.\r
3ed785e9 378///\r
959ccb23 379#define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001\r
380#define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001\r
381#define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000\r
382\r
3ed785e9 383///\r
af2dc6a7 384/// UNDI Transmit.\r
3ed785e9 385///\r
386///\r
387/// S/W UNDI only. Return after the packet has been transmitted. A\r
388/// transmit complete interrupt will still be generated and the transmit\r
389/// buffer will have to be recycled.\r
390///\r
959ccb23 391#define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001\r
392#define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001\r
393#define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000\r
394\r
959ccb23 395#define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002\r
396#define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002\r
397#define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000\r
398\r
4ccd9566 399///\r
af2dc6a7 400/// UNDI Receive.\r
3ed785e9 401///\r
af2dc6a7 402/// No OpFlags.\r
3ed785e9 403///\r
404\r
405///\r
af2dc6a7 406/// PXE STATFLAGS.\r
3ed785e9 407///\r
959ccb23 408typedef PXE_UINT16 PXE_STATFLAGS;\r
409\r
410#define PXE_STATFLAGS_INITIALIZE 0x0000\r
411\r
3ed785e9 412///\r
413/// Common StatFlags that can be returned by all commands.\r
414///\r
415///\r
416/// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be\r
417/// implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs\r
418/// that support command queuing.\r
419///\r
959ccb23 420#define PXE_STATFLAGS_STATUS_MASK 0xC000\r
421#define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000\r
422#define PXE_STATFLAGS_COMMAND_FAILED 0x8000\r
423#define PXE_STATFLAGS_COMMAND_QUEUED 0x4000\r
424\r
3ed785e9 425///\r
af2dc6a7 426/// UNDI Get State.\r
3ed785e9 427///\r
959ccb23 428#define PXE_STATFLAGS_GET_STATE_MASK 0x0003\r
429#define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002\r
430#define PXE_STATFLAGS_GET_STATE_STARTED 0x0001\r
431#define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000\r
432\r
3ed785e9 433///\r
af2dc6a7 434/// UNDI Start.\r
3ed785e9 435///\r
af2dc6a7 436/// No additional StatFlags.\r
3ed785e9 437///\r
959ccb23 438\r
3ed785e9 439///\r
af2dc6a7 440/// UNDI Get Init Info.\r
3ed785e9 441///\r
959ccb23 442#define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001\r
443#define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000\r
444#define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001\r
445\r
993702aa 446#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK 0x0002\r
447#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED 0x0000\r
448#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED 0x0002\r
449\r
3ed785e9 450///\r
af2dc6a7 451/// UNDI Initialize.\r
3ed785e9 452///\r
959ccb23 453#define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001\r
454\r
3ed785e9 455///\r
af2dc6a7 456/// UNDI Reset.\r
3ed785e9 457///\r
959ccb23 458#define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001\r
459\r
3ed785e9 460///\r
af2dc6a7 461/// UNDI Shutdown.\r
3ed785e9 462///\r
af2dc6a7 463/// No additional StatFlags.\r
959ccb23 464\r
3ed785e9 465///\r
af2dc6a7 466/// UNDI Interrupt Enables.\r
3ed785e9 467///\r
468///\r
469/// If set, receive interrupts are enabled.\r
470///\r
959ccb23 471#define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001\r
472\r
3ed785e9 473///\r
474/// If set, transmit interrupts are enabled.\r
475///\r
959ccb23 476#define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002\r
477\r
3ed785e9 478///\r
479/// If set, command interrupts are enabled.\r
480///\r
959ccb23 481#define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004\r
482\r
3ed785e9 483///\r
af2dc6a7 484/// UNDI Receive Filters.\r
3ed785e9 485///\r
486\r
487///\r
488/// If set, unicast packets will be received.\r
489///\r
959ccb23 490#define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r
491\r
3ed785e9 492///\r
493/// If set, broadcast packets will be received.\r
494///\r
959ccb23 495#define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r
496\r
3ed785e9 497///\r
498/// If set, multicast packets that match up with the multicast address\r
499/// filter list will be received.\r
500///\r
959ccb23 501#define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r
502\r
3ed785e9 503///\r
504/// If set, all packets will be received.\r
505///\r
959ccb23 506#define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r
507\r
3ed785e9 508///\r
509/// If set, all multicast packets will be received.\r
510///\r
959ccb23 511#define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r
512\r
3ed785e9 513///\r
af2dc6a7 514/// UNDI Station Address.\r
3ed785e9 515///\r
af2dc6a7 516/// No additional StatFlags.\r
3ed785e9 517///\r
959ccb23 518\r
3ed785e9 519///\r
af2dc6a7 520/// UNDI Statistics.\r
3ed785e9 521///\r
af2dc6a7 522/// No additional StatFlags.\r
3ed785e9 523///\r
959ccb23 524\r
3ed785e9 525///\r
af2dc6a7 526//// UNDI MCast IP to MAC.\r
3ed785e9 527////\r
af2dc6a7 528//// No additional StatFlags.\r
959ccb23 529\r
3ed785e9 530///\r
af2dc6a7 531/// UNDI NvData.\r
3ed785e9 532///\r
af2dc6a7 533/// No additional StatFlags.\r
3ed785e9 534///\r
959ccb23 535\r
3ed785e9 536///\r
af2dc6a7 537/// UNDI Get Status.\r
3ed785e9 538///\r
959ccb23 539\r
3ed785e9 540///\r
541/// Use to determine if an interrupt has occurred.\r
542///\r
959ccb23 543#define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F\r
544#define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000\r
545\r
3ed785e9 546///\r
547/// If set, at least one receive interrupt occurred.\r
548///\r
959ccb23 549#define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001\r
550\r
3ed785e9 551///\r
552/// If set, at least one transmit interrupt occurred.\r
553///\r
959ccb23 554#define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002\r
555\r
3ed785e9 556///\r
557/// If set, at least one command interrupt occurred.\r
558///\r
959ccb23 559#define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004\r
560\r
3ed785e9 561///\r
562/// If set, at least one software interrupt occurred.\r
563///\r
959ccb23 564#define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008\r
565\r
3ed785e9 566///\r
567/// This flag is set if the transmitted buffer queue is empty. This flag\r
568/// will be set if all transmitted buffer addresses get written into the DB.\r
569///\r
959ccb23 570#define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010\r
571\r
3ed785e9 572///\r
573/// This flag is set if no transmitted buffer addresses were written\r
574/// into the DB. (This could be because DBsize was too small.)\r
575///\r
959ccb23 576#define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020\r
577\r
993702aa 578///\r
579/// This flag is set if there is no media detected.\r
580///\r
581#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA 0x0040\r
582\r
3ed785e9 583///\r
af2dc6a7 584/// UNDI Fill Header.\r
3ed785e9 585///\r
af2dc6a7 586/// No additional StatFlags.\r
3ed785e9 587///\r
959ccb23 588\r
3ed785e9 589///\r
af2dc6a7 590/// UNDI Transmit.\r
3ed785e9 591///\r
592/// No additional StatFlags.\r
959ccb23 593\r
3ed785e9 594///\r
595/// UNDI Receive\r
af2dc6a7 596///.\r
3ed785e9 597\r
598///\r
599/// No additional StatFlags.\r
600///\r
959ccb23 601typedef PXE_UINT16 PXE_STATCODE;\r
602\r
603#define PXE_STATCODE_INITIALIZE 0x0000\r
604\r
3ed785e9 605///\r
606/// Common StatCodes returned by all UNDI commands, UNDI protocol functions\r
607/// and BC protocol functions.\r
608///\r
959ccb23 609#define PXE_STATCODE_SUCCESS 0x0000\r
610\r
611#define PXE_STATCODE_INVALID_CDB 0x0001\r
612#define PXE_STATCODE_INVALID_CPB 0x0002\r
613#define PXE_STATCODE_BUSY 0x0003\r
614#define PXE_STATCODE_QUEUE_FULL 0x0004\r
615#define PXE_STATCODE_ALREADY_STARTED 0x0005\r
616#define PXE_STATCODE_NOT_STARTED 0x0006\r
617#define PXE_STATCODE_NOT_SHUTDOWN 0x0007\r
618#define PXE_STATCODE_ALREADY_INITIALIZED 0x0008\r
619#define PXE_STATCODE_NOT_INITIALIZED 0x0009\r
620#define PXE_STATCODE_DEVICE_FAILURE 0x000A\r
621#define PXE_STATCODE_NVDATA_FAILURE 0x000B\r
622#define PXE_STATCODE_UNSUPPORTED 0x000C\r
623#define PXE_STATCODE_BUFFER_FULL 0x000D\r
624#define PXE_STATCODE_INVALID_PARAMETER 0x000E\r
625#define PXE_STATCODE_INVALID_UNDI 0x000F\r
626#define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010\r
627#define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011\r
628#define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012\r
629#define PXE_STATCODE_NO_DATA 0x0013\r
630\r
631typedef PXE_UINT16 PXE_IFNUM;\r
632\r
3ed785e9 633///\r
634/// This interface number must be passed to the S/W UNDI Start command.\r
635///\r
959ccb23 636#define PXE_IFNUM_START 0x0000\r
637\r
3ed785e9 638///\r
639/// This interface number is returned by the S/W UNDI Get State and\r
640/// Start commands if information in the CDB, CPB or DB is invalid.\r
641///\r
959ccb23 642#define PXE_IFNUM_INVALID 0x0000\r
643\r
644typedef PXE_UINT16 PXE_CONTROL;\r
645\r
3ed785e9 646///\r
647/// Setting this flag directs the UNDI to queue this command for later\r
648/// execution if the UNDI is busy and it supports command queuing.\r
649/// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error\r
650/// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL\r
651/// error is returned.\r
652///\r
959ccb23 653#define PXE_CONTROL_QUEUE_IF_BUSY 0x0002\r
654\r
3ed785e9 655///\r
656/// These two bit values are used to determine if there are more UNDI\r
657/// CDB structures following this one. If the link bit is set, there\r
658/// must be a CDB structure following this one. Execution will start\r
659/// on the next CDB structure as soon as this one completes successfully.\r
660/// If an error is generated by this command, execution will stop.\r
661///\r
959ccb23 662#define PXE_CONTROL_LINK 0x0001\r
663#define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000\r
664\r
665typedef PXE_UINT8 PXE_FRAME_TYPE;\r
666\r
667#define PXE_FRAME_TYPE_NONE 0x00\r
668#define PXE_FRAME_TYPE_UNICAST 0x01\r
669#define PXE_FRAME_TYPE_BROADCAST 0x02\r
670#define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03\r
671#define PXE_FRAME_TYPE_PROMISCUOUS 0x04\r
672#define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05\r
673\r
4ccd9566 674#define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST\r
959ccb23 675\r
676typedef PXE_UINT32 PXE_IPV4;\r
677\r
678typedef PXE_UINT32 PXE_IPV6[4];\r
679#define PXE_MAC_LENGTH 32\r
680\r
681typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];\r
682\r
683typedef PXE_UINT8 PXE_IFTYPE;\r
684typedef UINT16 PXE_MEDIA_PROTOCOL;\r
685\r
3ed785e9 686///\r
687/// This information is from the ARP section of RFC 1700.\r
688///\r
689/// 1 Ethernet (10Mb) [JBP]\r
690/// 2 Experimental Ethernet (3Mb) [JBP]\r
691/// 3 Amateur Radio AX.25 [PXK]\r
692/// 4 Proteon ProNET Token Ring [JBP]\r
693/// 5 Chaos [GXP]\r
694/// 6 IEEE 802 Networks [JBP]\r
695/// 7 ARCNET [JBP]\r
696/// 8 Hyperchannel [JBP]\r
697/// 9 Lanstar [TU]\r
698/// 10 Autonet Short Address [MXB1]\r
699/// 11 LocalTalk [JKR1]\r
700/// 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]\r
701/// 13 Ultra link [RXD2]\r
702/// 14 SMDS [GXC1]\r
703/// 15 Frame Relay [AGM]\r
704/// 16 Asynchronous Transmission Mode (ATM) [JXB2]\r
705/// 17 HDLC [JBP]\r
706/// 18 Fibre Channel [Yakov Rekhter]\r
707/// 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]\r
708/// 20 Serial Line [JBP]\r
709/// 21 Asynchronous Transmission Mode (ATM) [MXB1]\r
710///\r
711/// * Other names and brands may be claimed as the property of others.\r
712///\r
959ccb23 713#define PXE_IFTYPE_ETHERNET 0x01\r
714#define PXE_IFTYPE_TOKENRING 0x04\r
715#define PXE_IFTYPE_FIBRE_CHANNEL 0x12\r
716\r
717typedef struct s_pxe_hw_undi {\r
af2dc6a7 718 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.\r
719 PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI).\r
720 PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero.\r
721 PXE_UINT8 Rev; ///< PXE_ROMID_REV.\r
61f2ab90 722 PXE_UINT8 IFcnt; ///< physical connector count lower byte.\r
af2dc6a7 723 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.\r
724 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.\r
61f2ab90
QO
725 PXE_UINT8 IFcntExt; ///< physical connector count upper byte.\r
726 PXE_UINT8 reserved; ///< zero, not used.\r
af2dc6a7 727 PXE_UINT32 Implementation; ///< implementation flags.\r
728 ///< reserved ///< vendor use.\r
729 ///< UINT32 Status; ///< status port.\r
730 ///< UINT32 Command; ///< command port.\r
731 ///< UINT64 CDBaddr; ///< CDB address port.\r
3ed785e9 732 ///<\r
959ccb23 733} PXE_HW_UNDI;\r
734\r
3ed785e9 735///\r
af2dc6a7 736/// Status port bit definitions.\r
3ed785e9 737///\r
738\r
739///\r
af2dc6a7 740/// UNDI operation state.\r
3ed785e9 741///\r
959ccb23 742#define PXE_HWSTAT_STATE_MASK 0xC0000000\r
743#define PXE_HWSTAT_BUSY 0xC0000000\r
744#define PXE_HWSTAT_INITIALIZED 0x80000000\r
745#define PXE_HWSTAT_STARTED 0x40000000\r
746#define PXE_HWSTAT_STOPPED 0x00000000\r
747\r
3ed785e9 748///\r
af2dc6a7 749/// If set, last command failed.\r
3ed785e9 750///\r
959ccb23 751#define PXE_HWSTAT_COMMAND_FAILED 0x20000000\r
752\r
3ed785e9 753///\r
af2dc6a7 754/// If set, identifies enabled receive filters.\r
3ed785e9 755///\r
959ccb23 756#define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000\r
757#define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800\r
758#define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400\r
759#define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200\r
760#define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100\r
761\r
3ed785e9 762///\r
af2dc6a7 763/// If set, identifies enabled external interrupts.\r
3ed785e9 764///\r
959ccb23 765#define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080\r
766#define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040\r
767#define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020\r
768#define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010\r
769\r
3ed785e9 770///\r
af2dc6a7 771/// If set, identifies pending interrupts.\r
3ed785e9 772///\r
959ccb23 773#define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008\r
774#define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004\r
775#define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002\r
776#define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001\r
777\r
3ed785e9 778///\r
af2dc6a7 779/// Command port definitions.\r
3ed785e9 780///\r
781\r
782///\r
783/// If set, CDB identified in CDBaddr port is given to UNDI.\r
784/// If not set, other bits in this word will be processed.\r
785///\r
959ccb23 786#define PXE_HWCMD_ISSUE_COMMAND 0x80000000\r
787#define PXE_HWCMD_INTS_AND_FILTS 0x00000000\r
788\r
3ed785e9 789///\r
790/// Use these to enable/disable receive filters.\r
791///\r
959ccb23 792#define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000\r
793#define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800\r
794#define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400\r
795#define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200\r
796#define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100\r
797\r
3ed785e9 798///\r
af2dc6a7 799/// Use these to enable/disable external interrupts.\r
3ed785e9 800///\r
959ccb23 801#define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080\r
802#define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040\r
803#define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020\r
804#define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010\r
805\r
3ed785e9 806///\r
af2dc6a7 807/// Use these to clear pending external interrupts.\r
3ed785e9 808///\r
959ccb23 809#define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008\r
810#define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004\r
811#define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002\r
812#define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001\r
813\r
814typedef struct s_pxe_sw_undi {\r
af2dc6a7 815 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.\r
816 PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI).\r
817 PXE_UINT8 Fudge; ///< makes 8-bit cksum zero.\r
818 PXE_UINT8 Rev; ///< PXE_ROMID_REV.\r
61f2ab90 819 PXE_UINT8 IFcnt; ///< physical connector count lower byte.\r
af2dc6a7 820 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.\r
821 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.\r
61f2ab90
QO
822 PXE_UINT8 IFcntExt; ///< physical connector count upper byte.\r
823 PXE_UINT8 reserved1; ///< zero, not used.\r
af2dc6a7 824 PXE_UINT32 Implementation; ///< Implementation flags.\r
825 PXE_UINT64 EntryPoint; ///< API entry point.\r
826 PXE_UINT8 reserved2[3]; ///< zero, not used.\r
827 PXE_UINT8 BusCnt; ///< number of bustypes supported.\r
828 PXE_UINT32 BusType[1]; ///< list of supported bustypes.\r
959ccb23 829} PXE_SW_UNDI;\r
830\r
831typedef union u_pxe_undi {\r
832 PXE_HW_UNDI hw;\r
833 PXE_SW_UNDI sw;\r
834} PXE_UNDI;\r
835\r
3ed785e9 836///\r
af2dc6a7 837/// Signature of !PXE structure.\r
3ed785e9 838///\r
959ccb23 839#define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r
840\r
3ed785e9 841///\r
842/// !PXE structure format revision\r
af2dc6a7 843///.\r
959ccb23 844#define PXE_ROMID_REV 0x02\r
845\r
3ed785e9 846///\r
847/// UNDI command interface revision. These are the values that get sent\r
848/// in option 94 (Client Network Interface Identifier) in the DHCP Discover\r
849/// and PXE Boot Server Request packets.\r
850///\r
959ccb23 851#define PXE_ROMID_MAJORVER 0x03\r
852#define PXE_ROMID_MINORVER 0x01\r
853\r
3ed785e9 854///\r
af2dc6a7 855/// Implementation flags.\r
3ed785e9 856///\r
959ccb23 857#define PXE_ROMID_IMP_HW_UNDI 0x80000000\r
858#define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000\r
859#define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000\r
860#define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000\r
861#define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000\r
862#define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000\r
863#define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000\r
864#define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00\r
865#define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00\r
866#define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800\r
867#define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400\r
868#define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000\r
869#define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200\r
870#define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100\r
871#define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080\r
872#define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040\r
873#define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020\r
874#define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010\r
875#define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008\r
876#define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004\r
877#define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002\r
878#define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001\r
879\r
880typedef struct s_pxe_cdb {\r
881 PXE_OPCODE OpCode;\r
882 PXE_OPFLAGS OpFlags;\r
883 PXE_UINT16 CPBsize;\r
884 PXE_UINT16 DBsize;\r
885 PXE_UINT64 CPBaddr;\r
886 PXE_UINT64 DBaddr;\r
887 PXE_STATCODE StatCode;\r
888 PXE_STATFLAGS StatFlags;\r
889 PXE_UINT16 IFnum;\r
890 PXE_CONTROL Control;\r
891} PXE_CDB;\r
892\r
893typedef union u_pxe_ip_addr {\r
894 PXE_IPV6 IPv6;\r
895 PXE_IPV4 IPv4;\r
896} PXE_IP_ADDR;\r
897\r
898typedef union pxe_device {\r
3ed785e9 899 ///\r
900 /// PCI and PC Card NICs are both identified using bus, device\r
901 /// and function numbers. For PC Card, this may require PC\r
902 /// Card services to be loaded in the BIOS or preboot\r
903 /// environment.\r
904 ///\r
959ccb23 905 struct {\r
3ed785e9 906 ///\r
907 /// See S/W UNDI ROMID structure definition for PCI and\r
908 /// PCC BusType definitions.\r
909 ///\r
959ccb23 910 PXE_UINT32 BusType;\r
911\r
3ed785e9 912 ///\r
913 /// Bus, device & function numbers that locate this device.\r
914 ///\r
959ccb23 915 PXE_UINT16 Bus;\r
916 PXE_UINT8 Device;\r
917 PXE_UINT8 Function;\r
918 }\r
919 PCI, PCC;\r
920\r
959ccb23 921} PXE_DEVICE;\r
922\r
3ed785e9 923///\r
924/// cpb and db definitions\r
925///\r
af2dc6a7 926#define MAX_PCI_CONFIG_LEN 64 ///< # of dwords.\r
927#define MAX_EEPROM_LEN 128 ///< # of dwords.\r
928#define MAX_XMIT_BUFFERS 32 ///< recycling Q length for xmit_done.\r
959ccb23 929#define MAX_MCAST_ADDRESS_CNT 8\r
930\r
931typedef struct s_pxe_cpb_start_30 {\r
3ed785e9 932 ///\r
933 /// PXE_VOID Delay(UINTN microseconds);\r
934 ///\r
935 /// UNDI will never request a delay smaller than 10 microseconds\r
936 /// and will always request delays in increments of 10 microseconds.\r
937 /// The Delay() CallBack routine must delay between n and n + 10\r
938 /// microseconds before returning control to the UNDI.\r
939 ///\r
940 /// This field cannot be set to zero.\r
941 ///\r
959ccb23 942 UINT64 Delay;\r
943\r
3ed785e9 944 ///\r
945 /// PXE_VOID Block(UINT32 enable);\r
946 ///\r
947 /// UNDI may need to block multi-threaded/multi-processor access to\r
948 /// critical code sections when programming or accessing the network\r
949 /// device. To this end, a blocking service is needed by the UNDI.\r
950 /// When UNDI needs a block, it will call Block() passing a non-zero\r
951 /// value. When UNDI no longer needs a block, it will call Block()\r
952 /// with a zero value. When called, if the Block() is already enabled,\r
953 /// do not return control to the UNDI until the previous Block() is\r
954 /// disabled.\r
955 ///\r
956 /// This field cannot be set to zero.\r
957 ///\r
959ccb23 958 UINT64 Block;\r
959\r
3ed785e9 960 ///\r
961 /// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);\r
962 ///\r
963 /// UNDI will pass the virtual address of a buffer and the virtual\r
964 /// address of a 64-bit physical buffer. Convert the virtual address\r
965 /// to a physical address and write the result to the physical address\r
966 /// buffer. If virtual and physical addresses are the same, just\r
967 /// copy the virtual address to the physical address buffer.\r
968 ///\r
969 /// This field can be set to zero if virtual and physical addresses\r
970 /// are equal.\r
971 ///\r
959ccb23 972 UINT64 Virt2Phys;\r
3ed785e9 973 ///\r
974 /// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,\r
975 /// UINT64 buf_addr);\r
976 ///\r
977 /// UNDI will read or write the device io space using this call back\r
978 /// function. It passes the number of bytes as the len parameter and it\r
979 /// will be either 1,2,4 or 8.\r
980 ///\r
981 /// This field can not be set to zero.\r
982 ///\r
959ccb23 983 UINT64 Mem_IO;\r
984} PXE_CPB_START_30;\r
985\r
986typedef struct s_pxe_cpb_start_31 {\r
3ed785e9 987 ///\r
988 /// PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);\r
989 ///\r
990 /// UNDI will never request a delay smaller than 10 microseconds\r
991 /// and will always request delays in increments of 10 microseconds.\r
992 /// The Delay() CallBack routine must delay between n and n + 10\r
993 /// microseconds before returning control to the UNDI.\r
994 ///\r
995 /// This field cannot be set to zero.\r
996 ///\r
959ccb23 997 UINT64 Delay;\r
998\r
3ed785e9 999 ///\r
1000 /// PXE_VOID Block(UINT64 unq_id, UINT32 enable);\r
1001 ///\r
1002 /// UNDI may need to block multi-threaded/multi-processor access to\r
1003 /// critical code sections when programming or accessing the network\r
1004 /// device. To this end, a blocking service is needed by the UNDI.\r
1005 /// When UNDI needs a block, it will call Block() passing a non-zero\r
1006 /// value. When UNDI no longer needs a block, it will call Block()\r
1007 /// with a zero value. When called, if the Block() is already enabled,\r
1008 /// do not return control to the UNDI until the previous Block() is\r
1009 /// disabled.\r
1010 ///\r
1011 /// This field cannot be set to zero.\r
1012 ///\r
959ccb23 1013 UINT64 Block;\r
1014\r
3ed785e9 1015 ///\r
1016 /// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);\r
1017 ///\r
1018 /// UNDI will pass the virtual address of a buffer and the virtual\r
1019 /// address of a 64-bit physical buffer. Convert the virtual address\r
1020 /// to a physical address and write the result to the physical address\r
1021 /// buffer. If virtual and physical addresses are the same, just\r
1022 /// copy the virtual address to the physical address buffer.\r
1023 ///\r
1024 /// This field can be set to zero if virtual and physical addresses\r
1025 /// are equal.\r
1026 ///\r
959ccb23 1027 UINT64 Virt2Phys;\r
3ed785e9 1028 ///\r
1029 /// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,\r
1030 /// UINT64 buf_addr);\r
1031 ///\r
1032 /// UNDI will read or write the device io space using this call back\r
1033 /// function. It passes the number of bytes as the len parameter and it\r
1034 /// will be either 1,2,4 or 8.\r
1035 ///\r
1036 /// This field can not be set to zero.\r
1037 ///\r
959ccb23 1038 UINT64 Mem_IO;\r
3ed785e9 1039 ///\r
1040 /// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
1041 /// UINT32 Direction, UINT64 mapped_addr);\r
1042 ///\r
1043 /// UNDI will pass the virtual address of a buffer, direction of the data\r
1044 /// flow from/to the mapped buffer (the constants are defined below)\r
1045 /// and a place holder (pointer) for the mapped address.\r
1046 /// This call will Map the given address to a physical DMA address and write\r
1047 /// the result to the mapped_addr pointer. If there is no need to\r
1048 /// map the given address to a lower address (i.e. the given address is\r
1049 /// associated with a physical address that is already compatible to be\r
1050 /// used with the DMA, it converts the given virtual address to it's\r
1051 /// physical address and write that in the mapped address pointer.\r
1052 ///\r
af2dc6a7 1053 /// This field can be set to zero if there is no mapping service available.\r
3ed785e9 1054 ///\r
959ccb23 1055 UINT64 Map_Mem;\r
1056\r
3ed785e9 1057 ///\r
1058 /// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
1059 /// UINT32 Direction, UINT64 mapped_addr);\r
1060 ///\r
af2dc6a7 1061 /// UNDI will pass the virtual and mapped addresses of a buffer.\r
1062 /// This call will un map the given address.\r
3ed785e9 1063 ///\r
af2dc6a7 1064 /// This field can be set to zero if there is no unmapping service available.\r
3ed785e9 1065 ///\r
959ccb23 1066 UINT64 UnMap_Mem;\r
1067\r
3ed785e9 1068 ///\r
1069 /// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,\r
1070 /// UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r
1071 ///\r
af2dc6a7 1072 /// UNDI will pass the virtual and mapped addresses of a buffer.\r
1073 /// This call will synchronize the contents of both the virtual and mapped.\r
3ed785e9 1074 /// buffers for the given Direction.\r
1075 ///\r
af2dc6a7 1076 /// This field can be set to zero if there is no service available.\r
3ed785e9 1077 ///\r
959ccb23 1078 UINT64 Sync_Mem;\r
1079\r
3ed785e9 1080 ///\r
1081 /// protocol driver can provide anything for this Unique_ID, UNDI remembers\r
00b7cc0f 1082 /// that as just a 64bit value associated to the interface specified by\r
3ed785e9 1083 /// the ifnum and gives it back as a parameter to all the call-back routines\r
1084 /// when calling for that interface!\r
1085 ///\r
959ccb23 1086 UINT64 Unique_ID;\r
959ccb23 1087} PXE_CPB_START_31;\r
1088\r
1089#define TO_AND_FROM_DEVICE 0\r
1090#define FROM_DEVICE 1\r
1091#define TO_DEVICE 2\r
1092\r
1093#define PXE_DELAY_MILLISECOND 1000\r
1094#define PXE_DELAY_SECOND 1000000\r
1095#define PXE_IO_READ 0\r
1096#define PXE_IO_WRITE 1\r
1097#define PXE_MEM_READ 2\r
1098#define PXE_MEM_WRITE 4\r
1099\r
1100typedef struct s_pxe_db_get_init_info {\r
3ed785e9 1101 ///\r
1102 /// Minimum length of locked memory buffer that must be given to\r
1103 /// the Initialize command. Giving UNDI more memory will generally\r
1104 /// give better performance.\r
1105 ///\r
1106 /// If MemoryRequired is zero, the UNDI does not need and will not\r
1107 /// use system memory to receive and transmit packets.\r
1108 ///\r
959ccb23 1109 PXE_UINT32 MemoryRequired;\r
1110\r
3ed785e9 1111 ///\r
1112 /// Maximum frame data length for Tx/Rx excluding the media header.\r
1113 ///\r
959ccb23 1114 PXE_UINT32 FrameDataLen;\r
1115\r
3ed785e9 1116 ///\r
1117 /// Supported link speeds are in units of mega bits. Common ethernet\r
1118 /// values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero\r
1119 /// filled.\r
1120 ///\r
959ccb23 1121 PXE_UINT32 LinkSpeeds[4];\r
1122\r
3ed785e9 1123 ///\r
1124 /// Number of non-volatile storage items.\r
1125 ///\r
959ccb23 1126 PXE_UINT32 NvCount;\r
1127\r
3ed785e9 1128 ///\r
1129 /// Width of non-volatile storage item in bytes. 0, 1, 2 or 4\r
1130 ///\r
959ccb23 1131 PXE_UINT16 NvWidth;\r
1132\r
3ed785e9 1133 ///\r
1134 /// Media header length. This is the typical media header length for\r
1135 /// this UNDI. This information is needed when allocating receive\r
1136 /// and transmit buffers.\r
1137 ///\r
959ccb23 1138 PXE_UINT16 MediaHeaderLen;\r
1139\r
3ed785e9 1140 ///\r
1141 /// Number of bytes in the NIC hardware (MAC) address.\r
1142 ///\r
959ccb23 1143 PXE_UINT16 HWaddrLen;\r
1144\r
3ed785e9 1145 ///\r
1146 /// Maximum number of multicast MAC addresses in the multicast\r
1147 /// MAC address filter list.\r
1148 ///\r
959ccb23 1149 PXE_UINT16 MCastFilterCnt;\r
1150\r
3ed785e9 1151 ///\r
1152 /// Default number and size of transmit and receive buffers that will\r
1153 /// be allocated by the UNDI. If MemoryRequired is non-zero, this\r
1154 /// allocation will come out of the memory buffer given to the Initialize\r
1155 /// command. If MemoryRequired is zero, this allocation will come out of\r
1156 /// memory on the NIC.\r
1157 ///\r
959ccb23 1158 PXE_UINT16 TxBufCnt;\r
1159 PXE_UINT16 TxBufSize;\r
1160 PXE_UINT16 RxBufCnt;\r
1161 PXE_UINT16 RxBufSize;\r
1162\r
3ed785e9 1163 ///\r
1164 /// Hardware interface types defined in the Assigned Numbers RFC\r
1165 /// and used in DHCP and ARP packets.\r
1166 /// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.\r
1167 ///\r
959ccb23 1168 PXE_UINT8 IFtype;\r
1169\r
3ed785e9 1170 ///\r
1171 /// Supported duplex. See PXE_DUPLEX_xxxxx #defines below.\r
1172 ///\r
959ccb23 1173 PXE_UINT8 SupportedDuplexModes;\r
1174\r
3ed785e9 1175 ///\r
1176 /// Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.\r
1177 ///\r
959ccb23 1178 PXE_UINT8 SupportedLoopBackModes;\r
1179} PXE_DB_GET_INIT_INFO;\r
1180\r
1181#define PXE_MAX_TXRX_UNIT_ETHER 1500\r
1182\r
1183#define PXE_HWADDR_LEN_ETHER 0x0006\r
1184#define PXE_MAC_HEADER_LEN_ETHER 0x000E\r
1185\r
1186#define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1\r
1187#define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2\r
1188\r
1189#define PXE_LOOPBACK_INTERNAL_SUPPORTED 1\r
1190#define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2\r
1191\r
1192typedef struct s_pxe_pci_config_info {\r
3ed785e9 1193 ///\r
1194 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r
1195 /// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.\r
1196 ///\r
959ccb23 1197 UINT32 BusType;\r
1198\r
3ed785e9 1199 ///\r
af2dc6a7 1200 /// This identifies the PCI network device that this UNDI interface.\r
3ed785e9 1201 /// is bound to.\r
1202 ///\r
959ccb23 1203 UINT16 Bus;\r
1204 UINT8 Device;\r
1205 UINT8 Function;\r
1206\r
3ed785e9 1207 ///\r
1208 /// This is a copy of the PCI configuration space for this\r
1209 /// network device.\r
1210 ///\r
959ccb23 1211 union {\r
1212 UINT8 Byte[256];\r
1213 UINT16 Word[128];\r
1214 UINT32 Dword[64];\r
1215 } Config;\r
1216} PXE_PCI_CONFIG_INFO;\r
1217\r
1218typedef struct s_pxe_pcc_config_info {\r
3ed785e9 1219 ///\r
1220 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r
1221 /// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.\r
1222 ///\r
959ccb23 1223 PXE_UINT32 BusType;\r
1224\r
3ed785e9 1225 ///\r
1226 /// This identifies the PCC network device that this UNDI interface\r
1227 /// is bound to.\r
1228 ///\r
959ccb23 1229 PXE_UINT16 Bus;\r
1230 PXE_UINT8 Device;\r
1231 PXE_UINT8 Function;\r
1232\r
3ed785e9 1233 ///\r
1234 /// This is a copy of the PCC configuration space for this\r
1235 /// network device.\r
1236 ///\r
959ccb23 1237 union {\r
1238 PXE_UINT8 Byte[256];\r
1239 PXE_UINT16 Word[128];\r
1240 PXE_UINT32 Dword[64];\r
1241 } Config;\r
1242} PXE_PCC_CONFIG_INFO;\r
1243\r
1244typedef union u_pxe_db_get_config_info {\r
1245 PXE_PCI_CONFIG_INFO pci;\r
1246 PXE_PCC_CONFIG_INFO pcc;\r
1247} PXE_DB_GET_CONFIG_INFO;\r
1248\r
1249typedef struct s_pxe_cpb_initialize {\r
3ed785e9 1250 ///\r
1251 /// Address of first (lowest) byte of the memory buffer. This buffer must\r
1252 /// be in contiguous physical memory and cannot be swapped out. The UNDI\r
1253 /// will be using this for transmit and receive buffering.\r
1254 ///\r
959ccb23 1255 PXE_UINT64 MemoryAddr;\r
1256\r
3ed785e9 1257 ///\r
1258 /// MemoryLength must be greater than or equal to MemoryRequired\r
1259 /// returned by the Get Init Info command.\r
1260 ///\r
959ccb23 1261 PXE_UINT32 MemoryLength;\r
1262\r
3ed785e9 1263 ///\r
1264 /// Desired link speed in Mbit/sec. Common ethernet values are 10, 100\r
1265 /// and 1000. Setting a value of zero will auto-detect and/or use the\r
1266 /// default link speed (operation depends on UNDI/NIC functionality).\r
1267 ///\r
959ccb23 1268 PXE_UINT32 LinkSpeed;\r
1269\r
3ed785e9 1270 ///\r
1271 /// Suggested number and size of receive and transmit buffers to\r
1272 /// allocate. If MemoryAddr and MemoryLength are non-zero, this\r
1273 /// allocation comes out of the supplied memory buffer. If MemoryAddr\r
1274 /// and MemoryLength are zero, this allocation comes out of memory\r
1275 /// on the NIC.\r
1276 ///\r
1277 /// If these fields are set to zero, the UNDI will allocate buffer\r
1278 /// counts and sizes as it sees fit.\r
1279 ///\r
959ccb23 1280 PXE_UINT16 TxBufCnt;\r
1281 PXE_UINT16 TxBufSize;\r
1282 PXE_UINT16 RxBufCnt;\r
1283 PXE_UINT16 RxBufSize;\r
1284\r
3ed785e9 1285 ///\r
1286 /// The following configuration parameters are optional and must be zero\r
1287 /// to use the default values.\r
1288 ///\r
959ccb23 1289 PXE_UINT8 DuplexMode;\r
1290\r
1291 PXE_UINT8 LoopBackMode;\r
1292} PXE_CPB_INITIALIZE;\r
1293\r
1294#define PXE_DUPLEX_DEFAULT 0x00\r
1295#define PXE_FORCE_FULL_DUPLEX 0x01\r
1296#define PXE_ENABLE_FULL_DUPLEX 0x02\r
1297#define PXE_FORCE_HALF_DUPLEX 0x04\r
1298#define PXE_DISABLE_FULL_DUPLEX 0x08\r
1299\r
1300#define LOOPBACK_NORMAL 0\r
1301#define LOOPBACK_INTERNAL 1\r
1302#define LOOPBACK_EXTERNAL 2\r
1303\r
1304typedef struct s_pxe_db_initialize {\r
3ed785e9 1305 ///\r
1306 /// Actual amount of memory used from the supplied memory buffer. This\r
1307 /// may be less that the amount of memory suppllied and may be zero if\r
1308 /// the UNDI and network device do not use external memory buffers.\r
1309 ///\r
1310 /// Memory used by the UNDI and network device is allocated from the\r
1311 /// lowest memory buffer address.\r
1312 ///\r
959ccb23 1313 PXE_UINT32 MemoryUsed;\r
1314\r
3ed785e9 1315 ///\r
1316 /// Actual number and size of receive and transmit buffers that were\r
1317 /// allocated.\r
1318 ///\r
959ccb23 1319 PXE_UINT16 TxBufCnt;\r
1320 PXE_UINT16 TxBufSize;\r
1321 PXE_UINT16 RxBufCnt;\r
1322 PXE_UINT16 RxBufSize;\r
1323} PXE_DB_INITIALIZE;\r
1324\r
1325typedef struct s_pxe_cpb_receive_filters {\r
3ed785e9 1326 ///\r
1327 /// List of multicast MAC addresses. This list, if present, will\r
1328 /// replace the existing multicast MAC address filter list.\r
1329 ///\r
959ccb23 1330 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r
1331} PXE_CPB_RECEIVE_FILTERS;\r
1332\r
1333typedef struct s_pxe_db_receive_filters {\r
3ed785e9 1334 ///\r
1335 /// Filtered multicast MAC address list.\r
1336 ///\r
959ccb23 1337 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r
1338} PXE_DB_RECEIVE_FILTERS;\r
1339\r
1340typedef struct s_pxe_cpb_station_address {\r
3ed785e9 1341 ///\r
1342 /// If supplied and supported, the current station MAC address\r
1343 /// will be changed.\r
1344 ///\r
959ccb23 1345 PXE_MAC_ADDR StationAddr;\r
1346} PXE_CPB_STATION_ADDRESS;\r
1347\r
1348typedef struct s_pxe_dpb_station_address {\r
3ed785e9 1349 ///\r
1350 /// Current station MAC address.\r
1351 ///\r
959ccb23 1352 PXE_MAC_ADDR StationAddr;\r
1353\r
3ed785e9 1354 ///\r
1355 /// Station broadcast MAC address.\r
1356 ///\r
959ccb23 1357 PXE_MAC_ADDR BroadcastAddr;\r
1358\r
3ed785e9 1359 ///\r
1360 /// Permanent station MAC address.\r
1361 ///\r
959ccb23 1362 PXE_MAC_ADDR PermanentAddr;\r
1363} PXE_DB_STATION_ADDRESS;\r
1364\r
1365typedef struct s_pxe_db_statistics {\r
3ed785e9 1366 ///\r
1367 /// Bit field identifying what statistic data is collected by the\r
1368 /// UNDI/NIC.\r
1369 /// If bit 0x00 is set, Data[0x00] is collected.\r
1370 /// If bit 0x01 is set, Data[0x01] is collected.\r
1371 /// If bit 0x20 is set, Data[0x20] is collected.\r
1372 /// If bit 0x21 is set, Data[0x21] is collected.\r
1373 /// Etc.\r
1374 ///\r
959ccb23 1375 PXE_UINT64 Supported;\r
1376\r
3ed785e9 1377 ///\r
1378 /// Statistic data.\r
1379 ///\r
959ccb23 1380 PXE_UINT64 Data[64];\r
1381} PXE_DB_STATISTICS;\r
1382\r
3ed785e9 1383///\r
1384/// Total number of frames received. Includes frames with errors and\r
1385/// dropped frames.\r
1386///\r
959ccb23 1387#define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00\r
1388\r
3ed785e9 1389///\r
1390/// Number of valid frames received and copied into receive buffers.\r
1391///\r
959ccb23 1392#define PXE_STATISTICS_RX_GOOD_FRAMES 0x01\r
1393\r
3ed785e9 1394///\r
1395/// Number of frames below the minimum length for the media.\r
1396/// This would be <64 for ethernet.\r
1397///\r
959ccb23 1398#define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02\r
1399\r
3ed785e9 1400///\r
1401/// Number of frames longer than the maxminum length for the\r
1402/// media. This would be >1500 for ethernet.\r
1403///\r
959ccb23 1404#define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03\r
1405\r
3ed785e9 1406///\r
1407/// Valid frames that were dropped because receive buffers were full.\r
1408///\r
959ccb23 1409#define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04\r
1410\r
3ed785e9 1411///\r
1412/// Number of valid unicast frames received and not dropped.\r
1413///\r
959ccb23 1414#define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05\r
1415\r
3ed785e9 1416///\r
1417/// Number of valid broadcast frames received and not dropped.\r
1418///\r
959ccb23 1419#define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06\r
1420\r
3ed785e9 1421///\r
1422/// Number of valid mutlicast frames received and not dropped.\r
1423///\r
959ccb23 1424#define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07\r
1425\r
3ed785e9 1426///\r
1427/// Number of frames w/ CRC or alignment errors.\r
1428///\r
959ccb23 1429#define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08\r
1430\r
3ed785e9 1431///\r
1432/// Total number of bytes received. Includes frames with errors\r
1433/// and dropped frames.\r
1434///\r
959ccb23 1435#define PXE_STATISTICS_RX_TOTAL_BYTES 0x09\r
1436\r
3ed785e9 1437///\r
1438/// Transmit statistics.\r
1439///\r
959ccb23 1440#define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A\r
1441#define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B\r
1442#define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C\r
1443#define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D\r
1444#define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E\r
1445#define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F\r
1446#define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10\r
1447#define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11\r
1448#define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12\r
1449#define PXE_STATISTICS_TX_TOTAL_BYTES 0x13\r
1450\r
3ed785e9 1451///\r
1452/// Number of collisions detection on this subnet.\r
1453///\r
959ccb23 1454#define PXE_STATISTICS_COLLISIONS 0x14\r
1455\r
3ed785e9 1456///\r
1457/// Number of frames destined for unsupported protocol.\r
1458///\r
959ccb23 1459#define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15\r
1460\r
b4bddb6e
ZL
1461///\r
1462/// Number of valid frames received that were duplicated.\r
1463///\r
1464#define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16\r
1465\r
1466///\r
1467/// Number of encrypted frames received that failed to decrypt.\r
1468///\r
1469#define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17\r
1470\r
1471///\r
1472/// Number of frames that failed to transmit after exceeding the retry limit.\r
1473///\r
1474#define PXE_STATISTICS_TX_ERROR_FRAMES 0x18\r
1475\r
1476///\r
1477/// Number of frames transmitted successfully after more than one attempt.\r
1478///\r
1479#define PXE_STATISTICS_TX_RETRY_FRAMES 0x19\r
1480\r
959ccb23 1481typedef struct s_pxe_cpb_mcast_ip_to_mac {\r
3ed785e9 1482 ///\r
1483 /// Multicast IP address to be converted to multicast MAC address.\r
1484 ///\r
959ccb23 1485 PXE_IP_ADDR IP;\r
1486} PXE_CPB_MCAST_IP_TO_MAC;\r
1487\r
1488typedef struct s_pxe_db_mcast_ip_to_mac {\r
3ed785e9 1489 ///\r
1490 /// Multicast MAC address.\r
1491 ///\r
959ccb23 1492 PXE_MAC_ADDR MAC;\r
1493} PXE_DB_MCAST_IP_TO_MAC;\r
1494\r
1495typedef struct s_pxe_cpb_nvdata_sparse {\r
3ed785e9 1496 ///\r
1497 /// NvData item list. Only items in this list will be updated.\r
1498 ///\r
959ccb23 1499 struct {\r
3ed785e9 1500 ///\r
1501 /// Non-volatile storage address to be changed.\r
1502 ///\r
959ccb23 1503 PXE_UINT32 Addr;\r
1504\r
3ed785e9 1505 ///\r
1506 /// Data item to write into above storage address.\r
1507 ///\r
959ccb23 1508 union {\r
1509 PXE_UINT8 Byte;\r
1510 PXE_UINT16 Word;\r
1511 PXE_UINT32 Dword;\r
1512 } Data;\r
1513 } Item[MAX_EEPROM_LEN];\r
3ed785e9 1514} PXE_CPB_NVDATA_SPARSE;\r
959ccb23 1515\r
3ed785e9 1516///\r
1517/// When using bulk update, the size of the CPB structure must be\r
1518/// the same size as the non-volatile NIC storage.\r
1519///\r
959ccb23 1520typedef union u_pxe_cpb_nvdata_bulk {\r
3ed785e9 1521 ///\r
1522 /// Array of byte-wide data items.\r
1523 ///\r
959ccb23 1524 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r
1525\r
3ed785e9 1526 ///\r
1527 /// Array of word-wide data items.\r
1528 ///\r
959ccb23 1529 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r
1530\r
3ed785e9 1531 ///\r
1532 /// Array of dword-wide data items.\r
1533 ///\r
959ccb23 1534 PXE_UINT32 Dword[MAX_EEPROM_LEN];\r
1535} PXE_CPB_NVDATA_BULK;\r
1536\r
1537typedef struct s_pxe_db_nvdata {\r
3ed785e9 1538 ///\r
1539 /// Arrays of data items from non-volatile storage.\r
1540 ///\r
959ccb23 1541 union {\r
3ed785e9 1542 ///\r
1543 /// Array of byte-wide data items.\r
1544 ///\r
959ccb23 1545 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r
1546\r
3ed785e9 1547 ///\r
1548 /// Array of word-wide data items.\r
1549 ///\r
959ccb23 1550 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r
1551\r
3ed785e9 1552 ///\r
1553 /// Array of dword-wide data items.\r
1554 ///\r
959ccb23 1555 PXE_UINT32 Dword[MAX_EEPROM_LEN];\r
1556 } Data;\r
1557} PXE_DB_NVDATA;\r
1558\r
1559typedef struct s_pxe_db_get_status {\r
3ed785e9 1560 ///\r
1561 /// Length of next receive frame (header + data). If this is zero,\r
1562 /// there is no next receive frame available.\r
1563 ///\r
959ccb23 1564 PXE_UINT32 RxFrameLen;\r
1565\r
3ed785e9 1566 ///\r
1567 /// Reserved, set to zero.\r
1568 ///\r
959ccb23 1569 PXE_UINT32 reserved;\r
1570\r
3ed785e9 1571 ///\r
1572 /// Addresses of transmitted buffers that need to be recycled.\r
1573 ///\r
959ccb23 1574 PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];\r
1575} PXE_DB_GET_STATUS;\r
1576\r
1577typedef struct s_pxe_cpb_fill_header {\r
3ed785e9 1578 ///\r
1579 /// Source and destination MAC addresses. These will be copied into\r
1580 /// the media header without doing byte swapping.\r
1581 ///\r
959ccb23 1582 PXE_MAC_ADDR SrcAddr;\r
1583 PXE_MAC_ADDR DestAddr;\r
1584\r
3ed785e9 1585 ///\r
1586 /// Address of first byte of media header. The first byte of packet data\r
1587 /// follows the last byte of the media header.\r
1588 ///\r
959ccb23 1589 PXE_UINT64 MediaHeader;\r
1590\r
3ed785e9 1591 ///\r
1592 /// Length of packet data in bytes (not including the media header).\r
1593 ///\r
959ccb23 1594 PXE_UINT32 PacketLen;\r
1595\r
3ed785e9 1596 ///\r
1597 /// Protocol type. This will be copied into the media header without\r
1598 /// doing byte swapping. Protocol type numbers can be obtained from\r
1599 /// the Assigned Numbers RFC 1700.\r
1600 ///\r
959ccb23 1601 PXE_UINT16 Protocol;\r
1602\r
3ed785e9 1603 ///\r
1604 /// Length of the media header in bytes.\r
1605 ///\r
959ccb23 1606 PXE_UINT16 MediaHeaderLen;\r
1607} PXE_CPB_FILL_HEADER;\r
1608\r
1609#define PXE_PROTOCOL_ETHERNET_IP 0x0800\r
1610#define PXE_PROTOCOL_ETHERNET_ARP 0x0806\r
1611#define MAX_XMIT_FRAGMENTS 16\r
1612\r
1613typedef struct s_pxe_cpb_fill_header_fragmented {\r
3ed785e9 1614 ///\r
1615 /// Source and destination MAC addresses. These will be copied into\r
1616 /// the media header without doing byte swapping.\r
1617 ///\r
959ccb23 1618 PXE_MAC_ADDR SrcAddr;\r
1619 PXE_MAC_ADDR DestAddr;\r
1620\r
3ed785e9 1621 ///\r
1622 /// Length of packet data in bytes (not including the media header).\r
1623 ///\r
959ccb23 1624 PXE_UINT32 PacketLen;\r
1625\r
3ed785e9 1626 ///\r
1627 /// Protocol type. This will be copied into the media header without\r
1628 /// doing byte swapping. Protocol type numbers can be obtained from\r
1629 /// the Assigned Numbers RFC 1700.\r
1630 ///\r
959ccb23 1631 PXE_MEDIA_PROTOCOL Protocol;\r
1632\r
3ed785e9 1633 ///\r
1634 /// Length of the media header in bytes.\r
1635 ///\r
959ccb23 1636 PXE_UINT16 MediaHeaderLen;\r
1637\r
3ed785e9 1638 ///\r
1639 /// Number of packet fragment descriptors.\r
1640 ///\r
959ccb23 1641 PXE_UINT16 FragCnt;\r
1642\r
3ed785e9 1643 ///\r
1644 /// Reserved, must be set to zero.\r
1645 ///\r
959ccb23 1646 PXE_UINT16 reserved;\r
1647\r
3ed785e9 1648 ///\r
1649 /// Array of packet fragment descriptors. The first byte of the media\r
1650 /// header is the first byte of the first fragment.\r
1651 ///\r
959ccb23 1652 struct {\r
3ed785e9 1653 ///\r
1654 /// Address of this packet fragment.\r
1655 ///\r
959ccb23 1656 PXE_UINT64 FragAddr;\r
1657\r
3ed785e9 1658 ///\r
1659 /// Length of this packet fragment.\r
1660 ///\r
959ccb23 1661 PXE_UINT32 FragLen;\r
1662\r
3ed785e9 1663 ///\r
1664 /// Reserved, must be set to zero.\r
1665 ///\r
959ccb23 1666 PXE_UINT32 reserved;\r
1667 } FragDesc[MAX_XMIT_FRAGMENTS];\r
1668}\r
1669PXE_CPB_FILL_HEADER_FRAGMENTED;\r
1670\r
1671typedef struct s_pxe_cpb_transmit {\r
3ed785e9 1672 ///\r
1673 /// Address of first byte of frame buffer. This is also the first byte\r
1674 /// of the media header.\r
1675 ///\r
959ccb23 1676 PXE_UINT64 FrameAddr;\r
1677\r
3ed785e9 1678 ///\r
1679 /// Length of the data portion of the frame buffer in bytes. Do not\r
1680 /// include the length of the media header.\r
1681 ///\r
959ccb23 1682 PXE_UINT32 DataLen;\r
1683\r
3ed785e9 1684 ///\r
1685 /// Length of the media header in bytes.\r
1686 ///\r
959ccb23 1687 PXE_UINT16 MediaheaderLen;\r
1688\r
3ed785e9 1689 ///\r
1690 /// Reserved, must be zero.\r
1691 ///\r
959ccb23 1692 PXE_UINT16 reserved;\r
1693} PXE_CPB_TRANSMIT;\r
1694\r
1695typedef struct s_pxe_cpb_transmit_fragments {\r
3ed785e9 1696 ///\r
1697 /// Length of packet data in bytes (not including the media header).\r
1698 ///\r
959ccb23 1699 PXE_UINT32 FrameLen;\r
1700\r
3ed785e9 1701 ///\r
1702 /// Length of the media header in bytes.\r
1703 ///\r
959ccb23 1704 PXE_UINT16 MediaheaderLen;\r
1705\r
3ed785e9 1706 ///\r
1707 /// Number of packet fragment descriptors.\r
1708 ///\r
959ccb23 1709 PXE_UINT16 FragCnt;\r
1710\r
3ed785e9 1711 ///\r
1712 /// Array of frame fragment descriptors. The first byte of the first\r
1713 /// fragment is also the first byte of the media header.\r
1714 ///\r
959ccb23 1715 struct {\r
3ed785e9 1716 ///\r
1717 /// Address of this frame fragment.\r
1718 ///\r
959ccb23 1719 PXE_UINT64 FragAddr;\r
1720\r
3ed785e9 1721 ///\r
1722 /// Length of this frame fragment.\r
1723 ///\r
959ccb23 1724 PXE_UINT32 FragLen;\r
1725\r
3ed785e9 1726 ///\r
1727 /// Reserved, must be set to zero.\r
1728 ///\r
959ccb23 1729 PXE_UINT32 reserved;\r
1730 } FragDesc[MAX_XMIT_FRAGMENTS];\r
1731}\r
1732PXE_CPB_TRANSMIT_FRAGMENTS;\r
1733\r
1734typedef struct s_pxe_cpb_receive {\r
3ed785e9 1735 ///\r
1736 /// Address of first byte of receive buffer. This is also the first byte\r
1737 /// of the frame header.\r
1738 ///\r
959ccb23 1739 PXE_UINT64 BufferAddr;\r
1740\r
3ed785e9 1741 ///\r
1742 /// Length of receive buffer. This must be large enough to hold the\r
1743 /// received frame (media header + data). If the length of smaller than\r
1744 /// the received frame, data will be lost.\r
1745 ///\r
959ccb23 1746 PXE_UINT32 BufferLen;\r
1747\r
3ed785e9 1748 ///\r
1749 /// Reserved, must be set to zero.\r
1750 ///\r
959ccb23 1751 PXE_UINT32 reserved;\r
1752} PXE_CPB_RECEIVE;\r
1753\r
1754typedef struct s_pxe_db_receive {\r
3ed785e9 1755 ///\r
1756 /// Source and destination MAC addresses from media header.\r
1757 ///\r
959ccb23 1758 PXE_MAC_ADDR SrcAddr;\r
1759 PXE_MAC_ADDR DestAddr;\r
1760\r
3ed785e9 1761 ///\r
1762 /// Length of received frame. May be larger than receive buffer size.\r
1763 /// The receive buffer will not be overwritten. This is how to tell\r
1764 /// if data was lost because the receive buffer was too small.\r
1765 ///\r
959ccb23 1766 PXE_UINT32 FrameLen;\r
1767\r
3ed785e9 1768 ///\r
1769 /// Protocol type from media header.\r
1770 ///\r
959ccb23 1771 PXE_MEDIA_PROTOCOL Protocol;\r
1772\r
3ed785e9 1773 ///\r
1774 /// Length of media header in received frame.\r
1775 ///\r
959ccb23 1776 PXE_UINT16 MediaHeaderLen;\r
1777\r
3ed785e9 1778 ///\r
1779 /// Type of receive frame.\r
1780 ///\r
959ccb23 1781 PXE_FRAME_TYPE Type;\r
1782\r
3ed785e9 1783 ///\r
1784 /// Reserved, must be zero.\r
1785 ///\r
959ccb23 1786 PXE_UINT8 reserved[7];\r
1787\r
1788} PXE_DB_RECEIVE;\r
1789\r
959ccb23 1790#pragma pack()\r
1791\r
1792#endif\r