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[mirror_edk2.git] / MdePkg / Include / Uefi / UefiPxe.h
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959ccb23 1/** @file\r
2 This header file contains all of the PXE type definitions,\r
3 structure prototypes, global variables and constants that\r
4 are needed for porting PXE to EFI.\r
5 \r
6 Copyright (c) 2006, Intel Corporation \r
7 All rights reserved. This program and the accompanying materials \r
8 are licensed and made available under the terms and conditions of the BSD License \r
9 which accompanies this distribution. The full text of the license may be found at \r
10 http://opensource.org/licenses/bsd-license.php \r
11 \r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
14 \r
15 Module name: EfiPxe.h\r
16 \r
17 @par Revision Reference:\r
18 32/64-bit PXE specification:\r
19 alpha-4, 99-Dec-17\r
20 \r
21**/\r
22\r
23#ifndef __EFI_PXE_H__\r
24#define __EFI_PXE_H__\r
25\r
26#pragma pack(1)\r
27\r
28\r
29\r
30#define PXE_BUSTYPE(a, b, c, d) \\r
31 ( \\r
32 (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \\r
33 ((PXE_UINT32) (a) & 0xFF) \\r
34 )\r
35\r
36//\r
37// UNDI ROM ID and devive ID signature\r
38//\r
39#define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r
40\r
41//\r
42// BUS ROM ID signatures\r
43//\r
44#define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')\r
45#define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')\r
46#define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')\r
47#define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')\r
48\r
49#define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))\r
50\r
51#define PXE_SWAP_UINT32(n) \\r
52 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \\r
53 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \\r
54 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \\r
55 (((PXE_UINT32)(n) & 0xFF000000) >> 24))\r
56\r
57#define PXE_SWAP_UINT64(n) \\r
58 ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \\r
59 (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \\r
60 (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \\r
61 (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \\r
62 (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \\r
63 (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \\r
64 (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \\r
65 (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))\r
66\r
67\r
68#define PXE_CPBSIZE_NOT_USED 0 // zero\r
69#define PXE_DBSIZE_NOT_USED 0 // zero\r
70#define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 // zero\r
71#define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 // zero\r
72#define PXE_CONST const\r
73\r
74#define PXE_VOLATILE volatile\r
75\r
76typedef VOID PXE_VOID;\r
77typedef UINT8 PXE_UINT8;\r
78typedef UINT16 PXE_UINT16;\r
79typedef UINT32 PXE_UINT32;\r
80typedef UINTN PXE_UINTN;\r
81 \r
82//\r
83// typedef unsigned long PXE_UINT64;\r
84//\r
85typedef UINT64 PXE_UINT64;\r
86\r
87typedef PXE_UINT8 PXE_BOOL;\r
88#define PXE_FALSE 0 // zero\r
89#define PXE_TRUE (!PXE_FALSE)\r
90\r
91typedef PXE_UINT16 PXE_OPCODE;\r
92\r
93//\r
94// Return UNDI operational state.\r
95//\r
96#define PXE_OPCODE_GET_STATE 0x0000\r
97\r
98//\r
99// Change UNDI operational state from Stopped to Started.\r
100//\r
101#define PXE_OPCODE_START 0x0001\r
102\r
103//\r
104// Change UNDI operational state from Started to Stopped.\r
105//\r
106#define PXE_OPCODE_STOP 0x0002\r
107\r
108//\r
109// Get UNDI initialization information.\r
110//\r
111#define PXE_OPCODE_GET_INIT_INFO 0x0003\r
112\r
113//\r
114// Get NIC configuration information.\r
115//\r
116#define PXE_OPCODE_GET_CONFIG_INFO 0x0004\r
117\r
118//\r
119// Changed UNDI operational state from Started to Initialized.\r
120//\r
121#define PXE_OPCODE_INITIALIZE 0x0005\r
122\r
123//\r
124// Re-initialize the NIC H/W.\r
125//\r
126#define PXE_OPCODE_RESET 0x0006\r
127\r
128//\r
129// Change the UNDI operational state from Initialized to Started.\r
130//\r
131#define PXE_OPCODE_SHUTDOWN 0x0007\r
132\r
133//\r
134// Read & change state of external interrupt enables.\r
135//\r
136#define PXE_OPCODE_INTERRUPT_ENABLES 0x0008\r
137\r
138//\r
139// Read & change state of packet receive filters.\r
140//\r
141#define PXE_OPCODE_RECEIVE_FILTERS 0x0009\r
142\r
143//\r
144// Read & change station MAC address.\r
145//\r
146#define PXE_OPCODE_STATION_ADDRESS 0x000A\r
147\r
148//\r
149// Read traffic statistics.\r
150//\r
151#define PXE_OPCODE_STATISTICS 0x000B\r
152\r
153//\r
154// Convert multicast IP address to multicast MAC address.\r
155//\r
156#define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C\r
157\r
158//\r
159// Read or change non-volatile storage on the NIC.\r
160//\r
161#define PXE_OPCODE_NVDATA 0x000D\r
162\r
163//\r
164// Get & clear interrupt status.\r
165//\r
166#define PXE_OPCODE_GET_STATUS 0x000E\r
167\r
168//\r
169// Fill media header in packet for transmit.\r
170//\r
171#define PXE_OPCODE_FILL_HEADER 0x000F\r
172\r
173//\r
174// Transmit packet(s).\r
175//\r
176#define PXE_OPCODE_TRANSMIT 0x0010\r
177\r
178//\r
179// Receive packet.\r
180//\r
181#define PXE_OPCODE_RECEIVE 0x0011\r
182\r
183//\r
184// Last valid PXE UNDI OpCode number.\r
185//\r
186#define PXE_OPCODE_LAST_VALID 0x0011\r
187\r
188typedef PXE_UINT16 PXE_OPFLAGS;\r
189\r
190#define PXE_OPFLAGS_NOT_USED 0x0000\r
191\r
192//\r
193// //////////////////////////////////////\r
194// UNDI Get State\r
195//\r
196// No OpFlags\r
197\r
198////////////////////////////////////////\r
199// UNDI Start\r
200//\r
201// No OpFlags\r
202\r
203////////////////////////////////////////\r
204// UNDI Stop\r
205//\r
206// No OpFlags\r
207\r
208////////////////////////////////////////\r
209// UNDI Get Init Info\r
210//\r
211// No Opflags\r
212\r
213////////////////////////////////////////\r
214// UNDI Get Config Info\r
215//\r
216// No Opflags\r
217\r
218////////////////////////////////////////\r
219// UNDI Initialize\r
220//\r
221#define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001\r
222#define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000\r
223#define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001\r
224\r
225//\r
226// //////////////////////////////////////\r
227// UNDI Reset\r
228//\r
229#define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001\r
230#define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002\r
231\r
232//\r
233// //////////////////////////////////////\r
234// UNDI Shutdown\r
235//\r
236// No OpFlags\r
237\r
238////////////////////////////////////////\r
239// UNDI Interrupt Enables\r
240//\r
241//\r
242// Select whether to enable or disable external interrupt signals.\r
243// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.\r
244//\r
245#define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000\r
246#define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000\r
247#define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000\r
248#define PXE_OPFLAGS_INTERRUPT_READ 0x0000\r
249\r
250//\r
251// Enable receive interrupts. An external interrupt will be generated\r
252// after a complete non-error packet has been received.\r
253//\r
254#define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001\r
255\r
256//\r
257// Enable transmit interrupts. An external interrupt will be generated\r
258// after a complete non-error packet has been transmitted.\r
259//\r
260#define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002\r
261\r
262//\r
263// Enable command interrupts. An external interrupt will be generated\r
264// when command execution stops.\r
265//\r
266#define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004\r
267\r
268//\r
269// Generate software interrupt. Setting this bit generates an external\r
270// interrupt, if it is supported by the hardware.\r
271//\r
272#define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008\r
273\r
274//\r
275// //////////////////////////////////////\r
276// UNDI Receive Filters\r
277//\r
278//\r
279// Select whether to enable or disable receive filters.\r
280// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.\r
281//\r
282#define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000\r
283#define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000\r
284#define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000\r
285#define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000\r
286\r
287//\r
288// To reset the contents of the multicast MAC address filter list,\r
289// set this OpFlag:\r
290//\r
291#define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000\r
292\r
293//\r
294// Enable unicast packet receiving. Packets sent to the current station\r
295// MAC address will be received.\r
296//\r
297#define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r
298\r
299//\r
300// Enable broadcast packet receiving. Packets sent to the broadcast\r
301// MAC address will be received.\r
302//\r
303#define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r
304\r
305//\r
306// Enable filtered multicast packet receiving. Packets sent to any\r
307// of the multicast MAC addresses in the multicast MAC address filter\r
308// list will be received. If the filter list is empty, no multicast\r
309//\r
310#define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r
311\r
312//\r
313// Enable promiscuous packet receiving. All packets will be received.\r
314//\r
315#define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r
316\r
317//\r
318// Enable promiscuous multicast packet receiving. All multicast\r
319// packets will be received.\r
320//\r
321#define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r
322\r
323//\r
324// //////////////////////////////////////\r
325// UNDI Station Address\r
326//\r
327#define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000\r
328#define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000\r
329#define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001\r
330\r
331//\r
332// //////////////////////////////////////\r
333// UNDI Statistics\r
334//\r
335#define PXE_OPFLAGS_STATISTICS_READ 0x0000\r
336#define PXE_OPFLAGS_STATISTICS_RESET 0x0001\r
337\r
338//\r
339// //////////////////////////////////////\r
340// UNDI MCast IP to MAC\r
341//\r
342//\r
343// Identify the type of IP address in the CPB.\r
344//\r
345#define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003\r
346#define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000\r
347#define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001\r
348\r
349//\r
350// //////////////////////////////////////\r
351// UNDI NvData\r
352//\r
353//\r
354// Select the type of non-volatile data operation.\r
355//\r
356#define PXE_OPFLAGS_NVDATA_OPMASK 0x0001\r
357#define PXE_OPFLAGS_NVDATA_READ 0x0000\r
358#define PXE_OPFLAGS_NVDATA_WRITE 0x0001\r
359\r
360//\r
361// //////////////////////////////////////\r
362// UNDI Get Status\r
363//\r
364//\r
365// Return current interrupt status. This will also clear any interrupts\r
366// that are currently set. This can be used in a polling routine. The\r
367// interrupt flags are still set and cleared even when the interrupts\r
368// are disabled.\r
369//\r
370#define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001\r
371\r
372//\r
373// Return list of transmitted buffers for recycling. Transmit buffers\r
374// must not be changed or unallocated until they have recycled. After\r
375// issuing a transmit command, wait for a transmit complete interrupt.\r
376// When a transmit complete interrupt is received, read the transmitted\r
377// buffers. Do not plan on getting one buffer per interrupt. Some\r
378// NICs and UNDIs may transmit multiple buffers per interrupt.\r
379//\r
380#define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002\r
381\r
382//\r
383// //////////////////////////////////////\r
384// UNDI Fill Header\r
385//\r
386#define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001\r
387#define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001\r
388#define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000\r
389\r
390//\r
391// //////////////////////////////////////\r
392// UNDI Transmit\r
393//\r
394//\r
395// S/W UNDI only. Return after the packet has been transmitted. A\r
396// transmit complete interrupt will still be generated and the transmit\r
397// buffer will have to be recycled.\r
398//\r
399#define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001\r
400#define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001\r
401#define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000\r
402\r
403//\r
404//\r
405//\r
406#define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002\r
407#define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002\r
408#define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000\r
409\r
410//\r
411// //////////////////////////////////////\r
412// UNDI Receive\r
413//\r
414// No OpFlags\r
415//\r
416typedef PXE_UINT16 PXE_STATFLAGS;\r
417\r
418#define PXE_STATFLAGS_INITIALIZE 0x0000\r
419\r
420//\r
421// //////////////////////////////////////\r
422// Common StatFlags that can be returned by all commands.\r
423//\r
424//\r
425// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be\r
426// implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs\r
427// that support command queuing.\r
428//\r
429#define PXE_STATFLAGS_STATUS_MASK 0xC000\r
430#define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000\r
431#define PXE_STATFLAGS_COMMAND_FAILED 0x8000\r
432#define PXE_STATFLAGS_COMMAND_QUEUED 0x4000\r
433\r
434//\r
435// //////////////////////////////////////\r
436// UNDI Get State\r
437//\r
438#define PXE_STATFLAGS_GET_STATE_MASK 0x0003\r
439#define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002\r
440#define PXE_STATFLAGS_GET_STATE_STARTED 0x0001\r
441#define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000\r
442\r
443//\r
444// //////////////////////////////////////\r
445// UNDI Start\r
446//\r
447// No additional StatFlags\r
448\r
449////////////////////////////////////////\r
450// UNDI Get Init Info\r
451//\r
452#define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001\r
453#define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000\r
454#define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001\r
455\r
456//\r
457// //////////////////////////////////////\r
458// UNDI Initialize\r
459//\r
460#define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001\r
461\r
462//\r
463// //////////////////////////////////////\r
464// UNDI Reset\r
465//\r
466#define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001\r
467\r
468//\r
469// //////////////////////////////////////\r
470// UNDI Shutdown\r
471//\r
472// No additional StatFlags\r
473\r
474////////////////////////////////////////\r
475// UNDI Interrupt Enables\r
476//\r
477//\r
478// If set, receive interrupts are enabled.\r
479//\r
480#define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001\r
481\r
482//\r
483// If set, transmit interrupts are enabled.\r
484//\r
485#define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002\r
486\r
487//\r
488// If set, command interrupts are enabled.\r
489//\r
490#define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004\r
491\r
492//\r
493// //////////////////////////////////////\r
494// UNDI Receive Filters\r
495//\r
496//\r
497// If set, unicast packets will be received.\r
498//\r
499#define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r
500\r
501//\r
502// If set, broadcast packets will be received.\r
503//\r
504#define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r
505\r
506//\r
507// If set, multicast packets that match up with the multicast address\r
508// filter list will be received.\r
509//\r
510#define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r
511\r
512//\r
513// If set, all packets will be received.\r
514//\r
515#define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r
516\r
517//\r
518// If set, all multicast packets will be received.\r
519//\r
520#define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r
521\r
522//\r
523// //////////////////////////////////////\r
524// UNDI Station Address\r
525//\r
526// No additional StatFlags\r
527\r
528////////////////////////////////////////\r
529// UNDI Statistics\r
530//\r
531// No additional StatFlags\r
532\r
533////////////////////////////////////////\r
534// UNDI MCast IP to MAC\r
535//\r
536// No additional StatFlags\r
537\r
538////////////////////////////////////////\r
539// UNDI NvData\r
540//\r
541// No additional StatFlags\r
542\r
543\r
544////////////////////////////////////////\r
545// UNDI Get Status\r
546//\r
547//\r
548// Use to determine if an interrupt has occurred.\r
549//\r
550#define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F\r
551#define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000\r
552\r
553//\r
554// If set, at least one receive interrupt occurred.\r
555//\r
556#define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001\r
557\r
558//\r
559// If set, at least one transmit interrupt occurred.\r
560//\r
561#define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002\r
562\r
563//\r
564// If set, at least one command interrupt occurred.\r
565//\r
566#define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004\r
567\r
568//\r
569// If set, at least one software interrupt occurred.\r
570//\r
571#define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008\r
572\r
573//\r
574// This flag is set if the transmitted buffer queue is empty. This flag\r
575// will be set if all transmitted buffer addresses get written into the DB.\r
576//\r
577#define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010\r
578\r
579//\r
580// This flag is set if no transmitted buffer addresses were written\r
581// into the DB. (This could be because DBsize was too small.)\r
582//\r
583#define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020\r
584\r
585//\r
586// //////////////////////////////////////\r
587// UNDI Fill Header\r
588//\r
589// No additional StatFlags\r
590\r
591////////////////////////////////////////\r
592// UNDI Transmit\r
593//\r
594// No additional StatFlags.\r
595\r
596////////////////////////////////////////\r
597// UNDI Receive\r
598//\r
599// No additional StatFlags.\r
600//\r
601typedef PXE_UINT16 PXE_STATCODE;\r
602\r
603#define PXE_STATCODE_INITIALIZE 0x0000\r
604\r
605//\r
606// //////////////////////////////////////\r
607// Common StatCodes returned by all UNDI commands, UNDI protocol functions\r
608// and BC protocol functions.\r
609//\r
610#define PXE_STATCODE_SUCCESS 0x0000\r
611\r
612#define PXE_STATCODE_INVALID_CDB 0x0001\r
613#define PXE_STATCODE_INVALID_CPB 0x0002\r
614#define PXE_STATCODE_BUSY 0x0003\r
615#define PXE_STATCODE_QUEUE_FULL 0x0004\r
616#define PXE_STATCODE_ALREADY_STARTED 0x0005\r
617#define PXE_STATCODE_NOT_STARTED 0x0006\r
618#define PXE_STATCODE_NOT_SHUTDOWN 0x0007\r
619#define PXE_STATCODE_ALREADY_INITIALIZED 0x0008\r
620#define PXE_STATCODE_NOT_INITIALIZED 0x0009\r
621#define PXE_STATCODE_DEVICE_FAILURE 0x000A\r
622#define PXE_STATCODE_NVDATA_FAILURE 0x000B\r
623#define PXE_STATCODE_UNSUPPORTED 0x000C\r
624#define PXE_STATCODE_BUFFER_FULL 0x000D\r
625#define PXE_STATCODE_INVALID_PARAMETER 0x000E\r
626#define PXE_STATCODE_INVALID_UNDI 0x000F\r
627#define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010\r
628#define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011\r
629#define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012\r
630#define PXE_STATCODE_NO_DATA 0x0013\r
631\r
632typedef PXE_UINT16 PXE_IFNUM;\r
633\r
634//\r
635// This interface number must be passed to the S/W UNDI Start command.\r
636//\r
637#define PXE_IFNUM_START 0x0000\r
638\r
639//\r
640// This interface number is returned by the S/W UNDI Get State and\r
641// Start commands if information in the CDB, CPB or DB is invalid.\r
642//\r
643#define PXE_IFNUM_INVALID 0x0000\r
644\r
645typedef PXE_UINT16 PXE_CONTROL;\r
646\r
647//\r
648// Setting this flag directs the UNDI to queue this command for later\r
649// execution if the UNDI is busy and it supports command queuing.\r
650// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error\r
651// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL\r
652// error is returned.\r
653//\r
654#define PXE_CONTROL_QUEUE_IF_BUSY 0x0002\r
655\r
656//\r
657// These two bit values are used to determine if there are more UNDI\r
658// CDB structures following this one. If the link bit is set, there\r
659// must be a CDB structure following this one. Execution will start\r
660// on the next CDB structure as soon as this one completes successfully.\r
661// If an error is generated by this command, execution will stop.\r
662//\r
663#define PXE_CONTROL_LINK 0x0001\r
664#define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000\r
665\r
666typedef PXE_UINT8 PXE_FRAME_TYPE;\r
667\r
668#define PXE_FRAME_TYPE_NONE 0x00\r
669#define PXE_FRAME_TYPE_UNICAST 0x01\r
670#define PXE_FRAME_TYPE_BROADCAST 0x02\r
671#define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03\r
672#define PXE_FRAME_TYPE_PROMISCUOUS 0x04\r
673#define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05\r
674\r
675#define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST \r
676\r
677typedef PXE_UINT32 PXE_IPV4;\r
678\r
679typedef PXE_UINT32 PXE_IPV6[4];\r
680#define PXE_MAC_LENGTH 32\r
681\r
682typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];\r
683\r
684typedef PXE_UINT8 PXE_IFTYPE;\r
685typedef UINT16 PXE_MEDIA_PROTOCOL;\r
686\r
687//\r
688// This information is from the ARP section of RFC 1700.\r
689//\r
690// 1 Ethernet (10Mb) [JBP]\r
691// 2 Experimental Ethernet (3Mb) [JBP]\r
692// 3 Amateur Radio AX.25 [PXK]\r
693// 4 Proteon ProNET Token Ring [JBP]\r
694// 5 Chaos [GXP]\r
695// 6 IEEE 802 Networks [JBP]\r
696// 7 ARCNET [JBP]\r
697// 8 Hyperchannel [JBP]\r
698// 9 Lanstar [TU]\r
699// 10 Autonet Short Address [MXB1]\r
700// 11 LocalTalk [JKR1]\r
701// 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]\r
702// 13 Ultra link [RXD2]\r
703// 14 SMDS [GXC1]\r
704// 15 Frame Relay [AGM]\r
705// 16 Asynchronous Transmission Mode (ATM) [JXB2]\r
706// 17 HDLC [JBP]\r
707// 18 Fibre Channel [Yakov Rekhter]\r
708// 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]\r
709// 20 Serial Line [JBP]\r
710// 21 Asynchronous Transmission Mode (ATM) [MXB1]\r
711//\r
712// * Other names and brands may be claimed as the property of others.\r
713//\r
714#define PXE_IFTYPE_ETHERNET 0x01\r
715#define PXE_IFTYPE_TOKENRING 0x04\r
716#define PXE_IFTYPE_FIBRE_CHANNEL 0x12\r
717\r
718typedef struct s_pxe_hw_undi {\r
719 PXE_UINT32 Signature; // PXE_ROMID_SIGNATURE\r
720 PXE_UINT8 Len; // sizeof(PXE_HW_UNDI)\r
721 PXE_UINT8 Fudge; // makes 8-bit cksum equal zero\r
722 PXE_UINT8 Rev; // PXE_ROMID_REV\r
723 PXE_UINT8 IFcnt; // physical connector count\r
724 PXE_UINT8 MajorVer; // PXE_ROMID_MAJORVER\r
725 PXE_UINT8 MinorVer; // PXE_ROMID_MINORVER\r
726 PXE_UINT16 reserved; // zero, not used\r
727 PXE_UINT32 Implementation; // implementation flags\r
728 // reserved // vendor use\r
729 // UINT32 Status; // status port\r
730 // UINT32 Command; // command port\r
731 // UINT64 CDBaddr; // CDB address port\r
732 //\r
733} PXE_HW_UNDI;\r
734\r
735//\r
736// Status port bit definitions\r
737//\r
738//\r
739// UNDI operation state\r
740//\r
741#define PXE_HWSTAT_STATE_MASK 0xC0000000\r
742#define PXE_HWSTAT_BUSY 0xC0000000\r
743#define PXE_HWSTAT_INITIALIZED 0x80000000\r
744#define PXE_HWSTAT_STARTED 0x40000000\r
745#define PXE_HWSTAT_STOPPED 0x00000000\r
746\r
747//\r
748// If set, last command failed\r
749//\r
750#define PXE_HWSTAT_COMMAND_FAILED 0x20000000\r
751\r
752//\r
753// If set, identifies enabled receive filters\r
754//\r
755#define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000\r
756#define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800\r
757#define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400\r
758#define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200\r
759#define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100\r
760\r
761//\r
762// If set, identifies enabled external interrupts\r
763//\r
764#define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080\r
765#define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040\r
766#define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020\r
767#define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010\r
768\r
769//\r
770// If set, identifies pending interrupts\r
771//\r
772#define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008\r
773#define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004\r
774#define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002\r
775#define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001\r
776\r
777//\r
778// Command port definitions\r
779//\r
780//\r
781// If set, CDB identified in CDBaddr port is given to UNDI.\r
782// If not set, other bits in this word will be processed.\r
783//\r
784#define PXE_HWCMD_ISSUE_COMMAND 0x80000000\r
785#define PXE_HWCMD_INTS_AND_FILTS 0x00000000\r
786\r
787//\r
788// Use these to enable/disable receive filters.\r
789//\r
790#define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000\r
791#define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800\r
792#define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400\r
793#define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200\r
794#define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100\r
795\r
796//\r
797// Use these to enable/disable external interrupts\r
798//\r
799#define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080\r
800#define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040\r
801#define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020\r
802#define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010\r
803\r
804//\r
805// Use these to clear pending external interrupts\r
806//\r
807#define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008\r
808#define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004\r
809#define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002\r
810#define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001\r
811\r
812typedef struct s_pxe_sw_undi {\r
813 PXE_UINT32 Signature; // PXE_ROMID_SIGNATURE\r
814 PXE_UINT8 Len; // sizeof(PXE_SW_UNDI)\r
815 PXE_UINT8 Fudge; // makes 8-bit cksum zero\r
816 PXE_UINT8 Rev; // PXE_ROMID_REV\r
817 PXE_UINT8 IFcnt; // physical connector count\r
818 PXE_UINT8 MajorVer; // PXE_ROMID_MAJORVER\r
819 PXE_UINT8 MinorVer; // PXE_ROMID_MINORVER\r
820 PXE_UINT16 reserved1; // zero, not used\r
821 PXE_UINT32 Implementation; // Implementation flags\r
822 PXE_UINT64 EntryPoint; // API entry point\r
823 PXE_UINT8 reserved2[3]; // zero, not used\r
824 PXE_UINT8 BusCnt; // number of bustypes supported\r
825 PXE_UINT32 BusType[1]; // list of supported bustypes\r
826} PXE_SW_UNDI;\r
827\r
828typedef union u_pxe_undi {\r
829 PXE_HW_UNDI hw;\r
830 PXE_SW_UNDI sw;\r
831} PXE_UNDI;\r
832\r
833//\r
834// Signature of !PXE structure\r
835//\r
836#define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r
837\r
838//\r
839// !PXE structure format revision\r
840//\r
841#define PXE_ROMID_REV 0x02\r
842\r
843//\r
844// UNDI command interface revision. These are the values that get sent\r
845// in option 94 (Client Network Interface Identifier) in the DHCP Discover\r
846// and PXE Boot Server Request packets.\r
847//\r
848#define PXE_ROMID_MAJORVER 0x03\r
849#define PXE_ROMID_MINORVER 0x01\r
850\r
851//\r
852// Implementation flags\r
853//\r
854#define PXE_ROMID_IMP_HW_UNDI 0x80000000\r
855#define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000\r
856#define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000\r
857#define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000\r
858#define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000\r
859#define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000\r
860#define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000\r
861#define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00\r
862#define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00\r
863#define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800\r
864#define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400\r
865#define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000\r
866#define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200\r
867#define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100\r
868#define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080\r
869#define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040\r
870#define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020\r
871#define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010\r
872#define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008\r
873#define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004\r
874#define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002\r
875#define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001\r
876\r
877typedef struct s_pxe_cdb {\r
878 PXE_OPCODE OpCode;\r
879 PXE_OPFLAGS OpFlags;\r
880 PXE_UINT16 CPBsize;\r
881 PXE_UINT16 DBsize;\r
882 PXE_UINT64 CPBaddr;\r
883 PXE_UINT64 DBaddr;\r
884 PXE_STATCODE StatCode;\r
885 PXE_STATFLAGS StatFlags;\r
886 PXE_UINT16 IFnum;\r
887 PXE_CONTROL Control;\r
888} PXE_CDB;\r
889\r
890typedef union u_pxe_ip_addr {\r
891 PXE_IPV6 IPv6;\r
892 PXE_IPV4 IPv4;\r
893} PXE_IP_ADDR;\r
894\r
895typedef union pxe_device {\r
896 //\r
897 // PCI and PC Card NICs are both identified using bus, device\r
898 // and function numbers. For PC Card, this may require PC\r
899 // Card services to be loaded in the BIOS or preboot\r
900 // environment.\r
901 //\r
902 struct {\r
903 //\r
904 // See S/W UNDI ROMID structure definition for PCI and\r
905 // PCC BusType definitions.\r
906 //\r
907 PXE_UINT32 BusType;\r
908\r
909 //\r
910 // Bus, device & function numbers that locate this device.\r
911 //\r
912 PXE_UINT16 Bus;\r
913 PXE_UINT8 Device;\r
914 PXE_UINT8 Function;\r
915 }\r
916 PCI, PCC;\r
917\r
918 //\r
919 // %%TBD - More information is needed about enumerating\r
920 // USB and 1394 devices.\r
921 //\r
922 struct {\r
923 PXE_UINT32 BusType;\r
924 PXE_UINT32 tdb;\r
925 }\r
926 USB, _1394;\r
927} PXE_DEVICE;\r
928\r
929//\r
930// cpb and db definitions\r
931//\r
932#define MAX_PCI_CONFIG_LEN 64 // # of dwords\r
933#define MAX_EEPROM_LEN 128 // #of dwords\r
934#define MAX_XMIT_BUFFERS 32 // recycling Q length for xmit_done\r
935#define MAX_MCAST_ADDRESS_CNT 8\r
936\r
937typedef struct s_pxe_cpb_start_30 {\r
938 //\r
939 // PXE_VOID Delay(UINTN microseconds);\r
940 //\r
941 // UNDI will never request a delay smaller than 10 microseconds\r
942 // and will always request delays in increments of 10 microseconds.\r
943 // The Delay() CallBack routine must delay between n and n + 10\r
944 // microseconds before returning control to the UNDI.\r
945 //\r
946 // This field cannot be set to zero.\r
947 //\r
948 UINT64 Delay;\r
949\r
950 //\r
951 // PXE_VOID Block(UINT32 enable);\r
952 //\r
953 // UNDI may need to block multi-threaded/multi-processor access to\r
954 // critical code sections when programming or accessing the network\r
955 // device. To this end, a blocking service is needed by the UNDI.\r
956 // When UNDI needs a block, it will call Block() passing a non-zero\r
957 // value. When UNDI no longer needs a block, it will call Block()\r
958 // with a zero value. When called, if the Block() is already enabled,\r
959 // do not return control to the UNDI until the previous Block() is\r
960 // disabled.\r
961 //\r
962 // This field cannot be set to zero.\r
963 //\r
964 UINT64 Block;\r
965\r
966 //\r
967 // PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);\r
968 //\r
969 // UNDI will pass the virtual address of a buffer and the virtual\r
970 // address of a 64-bit physical buffer. Convert the virtual address\r
971 // to a physical address and write the result to the physical address\r
972 // buffer. If virtual and physical addresses are the same, just\r
973 // copy the virtual address to the physical address buffer.\r
974 //\r
975 // This field can be set to zero if virtual and physical addresses\r
976 // are equal.\r
977 //\r
978 UINT64 Virt2Phys;\r
979 //\r
980 // PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,\r
981 // UINT64 buf_addr);\r
982 //\r
983 // UNDI will read or write the device io space using this call back\r
984 // function. It passes the number of bytes as the len parameter and it\r
985 // will be either 1,2,4 or 8.\r
986 //\r
987 // This field can not be set to zero.\r
988 //\r
989 UINT64 Mem_IO;\r
990} PXE_CPB_START_30;\r
991\r
992typedef struct s_pxe_cpb_start_31 {\r
993 //\r
994 // PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);\r
995 //\r
996 // UNDI will never request a delay smaller than 10 microseconds\r
997 // and will always request delays in increments of 10 microseconds.\r
998 // The Delay() CallBack routine must delay between n and n + 10\r
999 // microseconds before returning control to the UNDI.\r
1000 //\r
1001 // This field cannot be set to zero.\r
1002 //\r
1003 UINT64 Delay;\r
1004\r
1005 //\r
1006 // PXE_VOID Block(UINT64 unq_id, UINT32 enable);\r
1007 //\r
1008 // UNDI may need to block multi-threaded/multi-processor access to\r
1009 // critical code sections when programming or accessing the network\r
1010 // device. To this end, a blocking service is needed by the UNDI.\r
1011 // When UNDI needs a block, it will call Block() passing a non-zero\r
1012 // value. When UNDI no longer needs a block, it will call Block()\r
1013 // with a zero value. When called, if the Block() is already enabled,\r
1014 // do not return control to the UNDI until the previous Block() is\r
1015 // disabled.\r
1016 //\r
1017 // This field cannot be set to zero.\r
1018 //\r
1019 UINT64 Block;\r
1020\r
1021 //\r
1022 // PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);\r
1023 //\r
1024 // UNDI will pass the virtual address of a buffer and the virtual\r
1025 // address of a 64-bit physical buffer. Convert the virtual address\r
1026 // to a physical address and write the result to the physical address\r
1027 // buffer. If virtual and physical addresses are the same, just\r
1028 // copy the virtual address to the physical address buffer.\r
1029 //\r
1030 // This field can be set to zero if virtual and physical addresses\r
1031 // are equal.\r
1032 //\r
1033 UINT64 Virt2Phys;\r
1034 //\r
1035 // PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,\r
1036 // UINT64 buf_addr);\r
1037 //\r
1038 // UNDI will read or write the device io space using this call back\r
1039 // function. It passes the number of bytes as the len parameter and it\r
1040 // will be either 1,2,4 or 8.\r
1041 //\r
1042 // This field can not be set to zero.\r
1043 //\r
1044 UINT64 Mem_IO;\r
1045 //\r
1046 // PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
1047 // UINT32 Direction, UINT64 mapped_addr);\r
1048 //\r
1049 // UNDI will pass the virtual address of a buffer, direction of the data\r
1050 // flow from/to the mapped buffer (the constants are defined below)\r
1051 // and a place holder (pointer) for the mapped address.\r
1052 // This call will Map the given address to a physical DMA address and write\r
1053 // the result to the mapped_addr pointer. If there is no need to\r
1054 // map the given address to a lower address (i.e. the given address is\r
1055 // associated with a physical address that is already compatible to be\r
1056 // used with the DMA, it converts the given virtual address to it's\r
1057 // physical address and write that in the mapped address pointer.\r
1058 //\r
1059 // This field can be set to zero if there is no mapping service available\r
1060 //\r
1061 UINT64 Map_Mem;\r
1062\r
1063 //\r
1064 // PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
1065 // UINT32 Direction, UINT64 mapped_addr);\r
1066 //\r
1067 // UNDI will pass the virtual and mapped addresses of a buffer\r
1068 // This call will un map the given address\r
1069 //\r
1070 // This field can be set to zero if there is no unmapping service available\r
1071 //\r
1072 UINT64 UnMap_Mem;\r
1073\r
1074 //\r
1075 // PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,\r
1076 // UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r
1077 //\r
1078 // UNDI will pass the virtual and mapped addresses of a buffer\r
1079 // This call will synchronize the contents of both the virtual and mapped\r
1080 // buffers for the given Direction.\r
1081 //\r
1082 // This field can be set to zero if there is no service available\r
1083 //\r
1084 UINT64 Sync_Mem;\r
1085\r
1086 //\r
1087 // protocol driver can provide anything for this Unique_ID, UNDI remembers\r
1088 // that as just a 64bit value assocaited to the interface specified by\r
1089 // the ifnum and gives it back as a parameter to all the call-back routines\r
1090 // when calling for that interface!\r
1091 //\r
1092 UINT64 Unique_ID;\r
1093 //\r
1094} PXE_CPB_START_31;\r
1095\r
1096#define TO_AND_FROM_DEVICE 0\r
1097#define FROM_DEVICE 1\r
1098#define TO_DEVICE 2\r
1099\r
1100#define PXE_DELAY_MILLISECOND 1000\r
1101#define PXE_DELAY_SECOND 1000000\r
1102#define PXE_IO_READ 0\r
1103#define PXE_IO_WRITE 1\r
1104#define PXE_MEM_READ 2\r
1105#define PXE_MEM_WRITE 4\r
1106\r
1107typedef struct s_pxe_db_get_init_info {\r
1108 //\r
1109 // Minimum length of locked memory buffer that must be given to\r
1110 // the Initialize command. Giving UNDI more memory will generally\r
1111 // give better performance.\r
1112 //\r
1113 // If MemoryRequired is zero, the UNDI does not need and will not\r
1114 // use system memory to receive and transmit packets.\r
1115 //\r
1116 PXE_UINT32 MemoryRequired;\r
1117\r
1118 //\r
1119 // Maximum frame data length for Tx/Rx excluding the media header.\r
1120 //\r
1121 PXE_UINT32 FrameDataLen;\r
1122\r
1123 //\r
1124 // Supported link speeds are in units of mega bits. Common ethernet\r
1125 // values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero\r
1126 // filled.\r
1127 //\r
1128 PXE_UINT32 LinkSpeeds[4];\r
1129\r
1130 //\r
1131 // Number of non-volatile storage items.\r
1132 //\r
1133 PXE_UINT32 NvCount;\r
1134\r
1135 //\r
1136 // Width of non-volatile storage item in bytes. 0, 1, 2 or 4\r
1137 //\r
1138 PXE_UINT16 NvWidth;\r
1139\r
1140 //\r
1141 // Media header length. This is the typical media header length for\r
1142 // this UNDI. This information is needed when allocating receive\r
1143 // and transmit buffers.\r
1144 //\r
1145 PXE_UINT16 MediaHeaderLen;\r
1146\r
1147 //\r
1148 // Number of bytes in the NIC hardware (MAC) address.\r
1149 //\r
1150 PXE_UINT16 HWaddrLen;\r
1151\r
1152 //\r
1153 // Maximum number of multicast MAC addresses in the multicast\r
1154 // MAC address filter list.\r
1155 //\r
1156 PXE_UINT16 MCastFilterCnt;\r
1157\r
1158 //\r
1159 // Default number and size of transmit and receive buffers that will\r
1160 // be allocated by the UNDI. If MemoryRequired is non-zero, this\r
1161 // allocation will come out of the memory buffer given to the Initialize\r
1162 // command. If MemoryRequired is zero, this allocation will come out of\r
1163 // memory on the NIC.\r
1164 //\r
1165 PXE_UINT16 TxBufCnt;\r
1166 PXE_UINT16 TxBufSize;\r
1167 PXE_UINT16 RxBufCnt;\r
1168 PXE_UINT16 RxBufSize;\r
1169\r
1170 //\r
1171 // Hardware interface types defined in the Assigned Numbers RFC\r
1172 // and used in DHCP and ARP packets.\r
1173 // See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.\r
1174 //\r
1175 PXE_UINT8 IFtype;\r
1176\r
1177 //\r
1178 // Supported duplex. See PXE_DUPLEX_xxxxx #defines below.\r
1179 //\r
1180 PXE_UINT8 SupportedDuplexModes;\r
1181\r
1182 //\r
1183 // Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.\r
1184 //\r
1185 PXE_UINT8 SupportedLoopBackModes;\r
1186} PXE_DB_GET_INIT_INFO;\r
1187\r
1188#define PXE_MAX_TXRX_UNIT_ETHER 1500\r
1189\r
1190#define PXE_HWADDR_LEN_ETHER 0x0006\r
1191#define PXE_MAC_HEADER_LEN_ETHER 0x000E\r
1192\r
1193#define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1\r
1194#define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2\r
1195\r
1196#define PXE_LOOPBACK_INTERNAL_SUPPORTED 1\r
1197#define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2\r
1198\r
1199typedef struct s_pxe_pci_config_info {\r
1200 //\r
1201 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r
1202 // For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.\r
1203 //\r
1204 UINT32 BusType;\r
1205\r
1206 //\r
1207 // This identifies the PCI network device that this UNDI interface\r
1208 // is bound to.\r
1209 //\r
1210 UINT16 Bus;\r
1211 UINT8 Device;\r
1212 UINT8 Function;\r
1213\r
1214 //\r
1215 // This is a copy of the PCI configuration space for this\r
1216 // network device.\r
1217 //\r
1218 union {\r
1219 UINT8 Byte[256];\r
1220 UINT16 Word[128];\r
1221 UINT32 Dword[64];\r
1222 } Config;\r
1223} PXE_PCI_CONFIG_INFO;\r
1224\r
1225typedef struct s_pxe_pcc_config_info {\r
1226 //\r
1227 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r
1228 // For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.\r
1229 //\r
1230 PXE_UINT32 BusType;\r
1231\r
1232 //\r
1233 // This identifies the PCC network device that this UNDI interface\r
1234 // is bound to.\r
1235 //\r
1236 PXE_UINT16 Bus;\r
1237 PXE_UINT8 Device;\r
1238 PXE_UINT8 Function;\r
1239\r
1240 //\r
1241 // This is a copy of the PCC configuration space for this\r
1242 // network device.\r
1243 //\r
1244 union {\r
1245 PXE_UINT8 Byte[256];\r
1246 PXE_UINT16 Word[128];\r
1247 PXE_UINT32 Dword[64];\r
1248 } Config;\r
1249} PXE_PCC_CONFIG_INFO;\r
1250\r
1251typedef union u_pxe_db_get_config_info {\r
1252 PXE_PCI_CONFIG_INFO pci;\r
1253 PXE_PCC_CONFIG_INFO pcc;\r
1254} PXE_DB_GET_CONFIG_INFO;\r
1255\r
1256typedef struct s_pxe_cpb_initialize {\r
1257 //\r
1258 // Address of first (lowest) byte of the memory buffer. This buffer must\r
1259 // be in contiguous physical memory and cannot be swapped out. The UNDI\r
1260 // will be using this for transmit and receive buffering.\r
1261 //\r
1262 PXE_UINT64 MemoryAddr;\r
1263\r
1264 //\r
1265 // MemoryLength must be greater than or equal to MemoryRequired\r
1266 // returned by the Get Init Info command.\r
1267 //\r
1268 PXE_UINT32 MemoryLength;\r
1269\r
1270 //\r
1271 // Desired link speed in Mbit/sec. Common ethernet values are 10, 100\r
1272 // and 1000. Setting a value of zero will auto-detect and/or use the\r
1273 // default link speed (operation depends on UNDI/NIC functionality).\r
1274 //\r
1275 PXE_UINT32 LinkSpeed;\r
1276\r
1277 //\r
1278 // Suggested number and size of receive and transmit buffers to\r
1279 // allocate. If MemoryAddr and MemoryLength are non-zero, this\r
1280 // allocation comes out of the supplied memory buffer. If MemoryAddr\r
1281 // and MemoryLength are zero, this allocation comes out of memory\r
1282 // on the NIC.\r
1283 //\r
1284 // If these fields are set to zero, the UNDI will allocate buffer\r
1285 // counts and sizes as it sees fit.\r
1286 //\r
1287 PXE_UINT16 TxBufCnt;\r
1288 PXE_UINT16 TxBufSize;\r
1289 PXE_UINT16 RxBufCnt;\r
1290 PXE_UINT16 RxBufSize;\r
1291\r
1292 //\r
1293 // The following configuration parameters are optional and must be zero\r
1294 // to use the default values.\r
1295 //\r
1296 PXE_UINT8 DuplexMode;\r
1297\r
1298 PXE_UINT8 LoopBackMode;\r
1299} PXE_CPB_INITIALIZE;\r
1300\r
1301#define PXE_DUPLEX_DEFAULT 0x00\r
1302#define PXE_FORCE_FULL_DUPLEX 0x01\r
1303#define PXE_ENABLE_FULL_DUPLEX 0x02\r
1304#define PXE_FORCE_HALF_DUPLEX 0x04\r
1305#define PXE_DISABLE_FULL_DUPLEX 0x08\r
1306\r
1307#define LOOPBACK_NORMAL 0\r
1308#define LOOPBACK_INTERNAL 1\r
1309#define LOOPBACK_EXTERNAL 2\r
1310\r
1311typedef struct s_pxe_db_initialize {\r
1312 //\r
1313 // Actual amount of memory used from the supplied memory buffer. This\r
1314 // may be less that the amount of memory suppllied and may be zero if\r
1315 // the UNDI and network device do not use external memory buffers.\r
1316 //\r
1317 // Memory used by the UNDI and network device is allocated from the\r
1318 // lowest memory buffer address.\r
1319 //\r
1320 PXE_UINT32 MemoryUsed;\r
1321\r
1322 //\r
1323 // Actual number and size of receive and transmit buffers that were\r
1324 // allocated.\r
1325 //\r
1326 PXE_UINT16 TxBufCnt;\r
1327 PXE_UINT16 TxBufSize;\r
1328 PXE_UINT16 RxBufCnt;\r
1329 PXE_UINT16 RxBufSize;\r
1330} PXE_DB_INITIALIZE;\r
1331\r
1332typedef struct s_pxe_cpb_receive_filters {\r
1333 //\r
1334 // List of multicast MAC addresses. This list, if present, will\r
1335 // replace the existing multicast MAC address filter list.\r
1336 //\r
1337 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r
1338} PXE_CPB_RECEIVE_FILTERS;\r
1339\r
1340typedef struct s_pxe_db_receive_filters {\r
1341 //\r
1342 // Filtered multicast MAC address list.\r
1343 //\r
1344 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r
1345} PXE_DB_RECEIVE_FILTERS;\r
1346\r
1347typedef struct s_pxe_cpb_station_address {\r
1348 //\r
1349 // If supplied and supported, the current station MAC address\r
1350 // will be changed.\r
1351 //\r
1352 PXE_MAC_ADDR StationAddr;\r
1353} PXE_CPB_STATION_ADDRESS;\r
1354\r
1355typedef struct s_pxe_dpb_station_address {\r
1356 //\r
1357 // Current station MAC address.\r
1358 //\r
1359 PXE_MAC_ADDR StationAddr;\r
1360\r
1361 //\r
1362 // Station broadcast MAC address.\r
1363 //\r
1364 PXE_MAC_ADDR BroadcastAddr;\r
1365\r
1366 //\r
1367 // Permanent station MAC address.\r
1368 //\r
1369 PXE_MAC_ADDR PermanentAddr;\r
1370} PXE_DB_STATION_ADDRESS;\r
1371\r
1372typedef struct s_pxe_db_statistics {\r
1373 //\r
1374 // Bit field identifying what statistic data is collected by the\r
1375 // UNDI/NIC.\r
1376 // If bit 0x00 is set, Data[0x00] is collected.\r
1377 // If bit 0x01 is set, Data[0x01] is collected.\r
1378 // If bit 0x20 is set, Data[0x20] is collected.\r
1379 // If bit 0x21 is set, Data[0x21] is collected.\r
1380 // Etc.\r
1381 //\r
1382 PXE_UINT64 Supported;\r
1383\r
1384 //\r
1385 // Statistic data.\r
1386 //\r
1387 PXE_UINT64 Data[64];\r
1388} PXE_DB_STATISTICS;\r
1389\r
1390//\r
1391// Total number of frames received. Includes frames with errors and\r
1392// dropped frames.\r
1393//\r
1394#define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00\r
1395\r
1396//\r
1397// Number of valid frames received and copied into receive buffers.\r
1398//\r
1399#define PXE_STATISTICS_RX_GOOD_FRAMES 0x01\r
1400\r
1401//\r
1402// Number of frames below the minimum length for the media.\r
1403// This would be <64 for ethernet.\r
1404//\r
1405#define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02\r
1406\r
1407//\r
1408// Number of frames longer than the maxminum length for the\r
1409// media. This would be >1500 for ethernet.\r
1410//\r
1411#define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03\r
1412\r
1413//\r
1414// Valid frames that were dropped because receive buffers were full.\r
1415//\r
1416#define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04\r
1417\r
1418//\r
1419// Number of valid unicast frames received and not dropped.\r
1420//\r
1421#define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05\r
1422\r
1423//\r
1424// Number of valid broadcast frames received and not dropped.\r
1425//\r
1426#define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06\r
1427\r
1428//\r
1429// Number of valid mutlicast frames received and not dropped.\r
1430//\r
1431#define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07\r
1432\r
1433//\r
1434// Number of frames w/ CRC or alignment errors.\r
1435//\r
1436#define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08\r
1437\r
1438//\r
1439// Total number of bytes received. Includes frames with errors\r
1440// and dropped frames.\r
1441//\r
1442#define PXE_STATISTICS_RX_TOTAL_BYTES 0x09\r
1443\r
1444//\r
1445// Transmit statistics.\r
1446//\r
1447#define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A\r
1448#define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B\r
1449#define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C\r
1450#define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D\r
1451#define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E\r
1452#define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F\r
1453#define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10\r
1454#define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11\r
1455#define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12\r
1456#define PXE_STATISTICS_TX_TOTAL_BYTES 0x13\r
1457\r
1458//\r
1459// Number of collisions detection on this subnet.\r
1460//\r
1461#define PXE_STATISTICS_COLLISIONS 0x14\r
1462\r
1463//\r
1464// Number of frames destined for unsupported protocol.\r
1465//\r
1466#define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15\r
1467\r
1468typedef struct s_pxe_cpb_mcast_ip_to_mac {\r
1469 //\r
1470 // Multicast IP address to be converted to multicast MAC address.\r
1471 //\r
1472 PXE_IP_ADDR IP;\r
1473} PXE_CPB_MCAST_IP_TO_MAC;\r
1474\r
1475typedef struct s_pxe_db_mcast_ip_to_mac {\r
1476 //\r
1477 // Multicast MAC address.\r
1478 //\r
1479 PXE_MAC_ADDR MAC;\r
1480} PXE_DB_MCAST_IP_TO_MAC;\r
1481\r
1482typedef struct s_pxe_cpb_nvdata_sparse {\r
1483 //\r
1484 // NvData item list. Only items in this list will be updated.\r
1485 //\r
1486 struct {\r
1487 //\r
1488 // Non-volatile storage address to be changed.\r
1489 //\r
1490 PXE_UINT32 Addr;\r
1491\r
1492 //\r
1493 // Data item to write into above storage address.\r
1494 //\r
1495 union {\r
1496 PXE_UINT8 Byte;\r
1497 PXE_UINT16 Word;\r
1498 PXE_UINT32 Dword;\r
1499 } Data;\r
1500 } Item[MAX_EEPROM_LEN];\r
1501}\r
1502PXE_CPB_NVDATA_SPARSE;\r
1503\r
1504//\r
1505// When using bulk update, the size of the CPB structure must be\r
1506// the same size as the non-volatile NIC storage.\r
1507//\r
1508typedef union u_pxe_cpb_nvdata_bulk {\r
1509 //\r
1510 // Array of byte-wide data items.\r
1511 //\r
1512 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r
1513\r
1514 //\r
1515 // Array of word-wide data items.\r
1516 //\r
1517 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r
1518\r
1519 //\r
1520 // Array of dword-wide data items.\r
1521 //\r
1522 PXE_UINT32 Dword[MAX_EEPROM_LEN];\r
1523} PXE_CPB_NVDATA_BULK;\r
1524\r
1525typedef struct s_pxe_db_nvdata {\r
1526 //\r
1527 // Arrays of data items from non-volatile storage.\r
1528 //\r
1529 union {\r
1530 //\r
1531 // Array of byte-wide data items.\r
1532 //\r
1533 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r
1534\r
1535 //\r
1536 // Array of word-wide data items.\r
1537 //\r
1538 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r
1539\r
1540 //\r
1541 // Array of dword-wide data items.\r
1542 //\r
1543 PXE_UINT32 Dword[MAX_EEPROM_LEN];\r
1544 } Data;\r
1545} PXE_DB_NVDATA;\r
1546\r
1547typedef struct s_pxe_db_get_status {\r
1548 //\r
1549 // Length of next receive frame (header + data). If this is zero,\r
1550 // there is no next receive frame available.\r
1551 //\r
1552 PXE_UINT32 RxFrameLen;\r
1553\r
1554 //\r
1555 // Reserved, set to zero.\r
1556 //\r
1557 PXE_UINT32 reserved;\r
1558\r
1559 //\r
1560 // Addresses of transmitted buffers that need to be recycled.\r
1561 //\r
1562 PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];\r
1563} PXE_DB_GET_STATUS;\r
1564\r
1565typedef struct s_pxe_cpb_fill_header {\r
1566 //\r
1567 // Source and destination MAC addresses. These will be copied into\r
1568 // the media header without doing byte swapping.\r
1569 //\r
1570 PXE_MAC_ADDR SrcAddr;\r
1571 PXE_MAC_ADDR DestAddr;\r
1572\r
1573 //\r
1574 // Address of first byte of media header. The first byte of packet data\r
1575 // follows the last byte of the media header.\r
1576 //\r
1577 PXE_UINT64 MediaHeader;\r
1578\r
1579 //\r
1580 // Length of packet data in bytes (not including the media header).\r
1581 //\r
1582 PXE_UINT32 PacketLen;\r
1583\r
1584 //\r
1585 // Protocol type. This will be copied into the media header without\r
1586 // doing byte swapping. Protocol type numbers can be obtained from\r
1587 // the Assigned Numbers RFC 1700.\r
1588 //\r
1589 PXE_UINT16 Protocol;\r
1590\r
1591 //\r
1592 // Length of the media header in bytes.\r
1593 //\r
1594 PXE_UINT16 MediaHeaderLen;\r
1595} PXE_CPB_FILL_HEADER;\r
1596\r
1597#define PXE_PROTOCOL_ETHERNET_IP 0x0800\r
1598#define PXE_PROTOCOL_ETHERNET_ARP 0x0806\r
1599#define MAX_XMIT_FRAGMENTS 16\r
1600\r
1601typedef struct s_pxe_cpb_fill_header_fragmented {\r
1602 //\r
1603 // Source and destination MAC addresses. These will be copied into\r
1604 // the media header without doing byte swapping.\r
1605 //\r
1606 PXE_MAC_ADDR SrcAddr;\r
1607 PXE_MAC_ADDR DestAddr;\r
1608\r
1609 //\r
1610 // Length of packet data in bytes (not including the media header).\r
1611 //\r
1612 PXE_UINT32 PacketLen;\r
1613\r
1614 //\r
1615 // Protocol type. This will be copied into the media header without\r
1616 // doing byte swapping. Protocol type numbers can be obtained from\r
1617 // the Assigned Numbers RFC 1700.\r
1618 //\r
1619 PXE_MEDIA_PROTOCOL Protocol;\r
1620\r
1621 //\r
1622 // Length of the media header in bytes.\r
1623 //\r
1624 PXE_UINT16 MediaHeaderLen;\r
1625\r
1626 //\r
1627 // Number of packet fragment descriptors.\r
1628 //\r
1629 PXE_UINT16 FragCnt;\r
1630\r
1631 //\r
1632 // Reserved, must be set to zero.\r
1633 //\r
1634 PXE_UINT16 reserved;\r
1635\r
1636 //\r
1637 // Array of packet fragment descriptors. The first byte of the media\r
1638 // header is the first byte of the first fragment.\r
1639 //\r
1640 struct {\r
1641 //\r
1642 // Address of this packet fragment.\r
1643 //\r
1644 PXE_UINT64 FragAddr;\r
1645\r
1646 //\r
1647 // Length of this packet fragment.\r
1648 //\r
1649 PXE_UINT32 FragLen;\r
1650\r
1651 //\r
1652 // Reserved, must be set to zero.\r
1653 //\r
1654 PXE_UINT32 reserved;\r
1655 } FragDesc[MAX_XMIT_FRAGMENTS];\r
1656}\r
1657PXE_CPB_FILL_HEADER_FRAGMENTED;\r
1658\r
1659typedef struct s_pxe_cpb_transmit {\r
1660 //\r
1661 // Address of first byte of frame buffer. This is also the first byte\r
1662 // of the media header.\r
1663 //\r
1664 PXE_UINT64 FrameAddr;\r
1665\r
1666 //\r
1667 // Length of the data portion of the frame buffer in bytes. Do not\r
1668 // include the length of the media header.\r
1669 //\r
1670 PXE_UINT32 DataLen;\r
1671\r
1672 //\r
1673 // Length of the media header in bytes.\r
1674 //\r
1675 PXE_UINT16 MediaheaderLen;\r
1676\r
1677 //\r
1678 // Reserved, must be zero.\r
1679 //\r
1680 PXE_UINT16 reserved;\r
1681} PXE_CPB_TRANSMIT;\r
1682\r
1683typedef struct s_pxe_cpb_transmit_fragments {\r
1684 //\r
1685 // Length of packet data in bytes (not including the media header).\r
1686 //\r
1687 PXE_UINT32 FrameLen;\r
1688\r
1689 //\r
1690 // Length of the media header in bytes.\r
1691 //\r
1692 PXE_UINT16 MediaheaderLen;\r
1693\r
1694 //\r
1695 // Number of packet fragment descriptors.\r
1696 //\r
1697 PXE_UINT16 FragCnt;\r
1698\r
1699 //\r
1700 // Array of frame fragment descriptors. The first byte of the first\r
1701 // fragment is also the first byte of the media header.\r
1702 //\r
1703 struct {\r
1704 //\r
1705 // Address of this frame fragment.\r
1706 //\r
1707 PXE_UINT64 FragAddr;\r
1708\r
1709 //\r
1710 // Length of this frame fragment.\r
1711 //\r
1712 PXE_UINT32 FragLen;\r
1713\r
1714 //\r
1715 // Reserved, must be set to zero.\r
1716 //\r
1717 PXE_UINT32 reserved;\r
1718 } FragDesc[MAX_XMIT_FRAGMENTS];\r
1719}\r
1720PXE_CPB_TRANSMIT_FRAGMENTS;\r
1721\r
1722typedef struct s_pxe_cpb_receive {\r
1723 //\r
1724 // Address of first byte of receive buffer. This is also the first byte\r
1725 // of the frame header.\r
1726 //\r
1727 PXE_UINT64 BufferAddr;\r
1728\r
1729 //\r
1730 // Length of receive buffer. This must be large enough to hold the\r
1731 // received frame (media header + data). If the length of smaller than\r
1732 // the received frame, data will be lost.\r
1733 //\r
1734 PXE_UINT32 BufferLen;\r
1735\r
1736 //\r
1737 // Reserved, must be set to zero.\r
1738 //\r
1739 PXE_UINT32 reserved;\r
1740} PXE_CPB_RECEIVE;\r
1741\r
1742typedef struct s_pxe_db_receive {\r
1743 //\r
1744 // Source and destination MAC addresses from media header.\r
1745 //\r
1746 PXE_MAC_ADDR SrcAddr;\r
1747 PXE_MAC_ADDR DestAddr;\r
1748\r
1749 //\r
1750 // Length of received frame. May be larger than receive buffer size.\r
1751 // The receive buffer will not be overwritten. This is how to tell\r
1752 // if data was lost because the receive buffer was too small.\r
1753 //\r
1754 PXE_UINT32 FrameLen;\r
1755\r
1756 //\r
1757 // Protocol type from media header.\r
1758 //\r
1759 PXE_MEDIA_PROTOCOL Protocol;\r
1760\r
1761 //\r
1762 // Length of media header in received frame.\r
1763 //\r
1764 PXE_UINT16 MediaHeaderLen;\r
1765\r
1766 //\r
1767 // Type of receive frame.\r
1768 //\r
1769 PXE_FRAME_TYPE Type;\r
1770\r
1771 //\r
1772 // Reserved, must be zero.\r
1773 //\r
1774 PXE_UINT8 reserved[7];\r
1775\r
1776} PXE_DB_RECEIVE;\r
1777\r
1778//\r
1779// Packet definitions\r
1780//\r
1781typedef struct {\r
1782 UINT8 BootpOpcode;\r
1783 UINT8 BootpHwType;\r
1784 UINT8 BootpHwAddrLen;\r
1785 UINT8 BootpGateHops;\r
1786 UINT32 BootpIdent;\r
1787 UINT16 BootpSeconds;\r
1788 UINT16 BootpFlags;\r
1789 UINT8 BootpCiAddr[4];\r
1790 UINT8 BootpYiAddr[4];\r
1791 UINT8 BootpSiAddr[4];\r
1792 UINT8 BootpGiAddr[4];\r
1793 UINT8 BootpHwAddr[16];\r
1794 UINT8 BootpSrvName[64];\r
1795 UINT8 BootpBootFile[128];\r
1796 UINT32 DhcpMagik;\r
1797 UINT8 DhcpOptions[56];\r
1798} EFI_PXE_BASE_CODE_DHCPV4_PACKET;\r
1799\r
1800typedef union {\r
1801 UINT8 Raw[1472];\r
1802 EFI_PXE_BASE_CODE_DHCPV4_PACKET Dhcpv4;\r
1803\r
1804 //\r
1805 // EFI_PXE_BASE_CODE_DHCPV6_PACKET Dhcpv6;\r
1806 //\r
1807} EFI_PXE_BASE_CODE_PACKET;\r
1808\r
1809\r
1810\r
1811#pragma pack()\r
1812\r
1813#endif\r