Omap35xxPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / Omap35xxPkg / Library / OmapDmaLib / OmapDmaLib.c

/** @file\r
  Abstractions for simple OMAP DMA channel.\r
\r
\r
  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Base.h>\r
#include <Library/DebugLib.h>\r
#include <Library/OmapDmaLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Omap3530/Omap3530.h>\r
\r
\r
/**\r
  Configure OMAP DMA Channel\r
\r
  @param  Channel               DMA Channel to configure\r
  @param  Dma4                  Pointer to structure used to initialize DMA registers for the Channel\r
\r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_INVALID_PARAMETER Channel is not valid\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EnableDmaChannel (\r
  IN  UINTN       Channel,\r
  IN  OMAP_DMA4   *DMA4\r
  )\r
{\r
  UINT32  RegVal;\r
\r
\r
  if (Channel > DMA4_MAX_CHANNEL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  /* 1) Configure the transfer parameters in the logical DMA registers */\r
  /*-------------------------------------------------------------------*/\r
\r
  /* a) Set the data type CSDP[1:0], the Read/Write Port access type\r
        CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],\r
        write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */\r
\r
  // Read CSDP\r
  RegVal = MmioRead32 (DMA4_CSDP (Channel));\r
\r
  // Build reg\r
  RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );\r
  RegVal = ((RegVal & ~(0x3 <<  7)) | (DMA4->ReadPortAccessType << 7));\r
  RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));\r
  RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));\r
  RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));\r
  RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));\r
  RegVal = ((RegVal & ~(0x1 <<  6)) | (DMA4->SourcePacked << 6));\r
  RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));\r
  // Write CSDP\r
  MmioWrite32 (DMA4_CSDP (Channel), RegVal);\r
\r
  /* b) Set the number of element per frame CEN[23:0]*/\r
  MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);\r
\r
  /* c) Set the number of frame per block CFN[15:0]*/\r
  MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);\r
\r
  /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/\r
  MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);\r
  MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);\r
\r
  /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],\r
        read/write priority CCR[6]/CCR[26]\r
        I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to\r
        LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber\r
  */\r
\r
  // Read CCR\r
  RegVal = MmioRead32 (DMA4_CCR (Channel));\r
\r
  // Build reg\r
  RegVal  = ((RegVal &  ~0x1f)            | DMA4->ReadRequestNumber);\r
  RegVal  = ((RegVal &  ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);\r
  RegVal  = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12));\r
  RegVal  = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14));\r
  RegVal  = ((RegVal & ~(0x1 <<  6)) | (DMA4->ReadPriority << 6));\r
  RegVal  = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26));\r
\r
  // Write CCR\r
  MmioWrite32 (DMA4_CCR (Channel), RegVal);\r
\r
  /* f)- Set the source element index CSEI[15:0]*/\r
  MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);\r
\r
  /* - Set the source frame index CSFI[15:0]*/\r
  MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);\r
\r
\r
  /* - Set the destination element index CDEI[15:0]*/\r
  MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);\r
\r
  /* - Set the destination frame index CDFI[31:0]*/\r
  MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
\r
  MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
\r
  // Enable all the status bits since we are polling\r
  MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);\r
  MmioWrite32 (DMA4_CSR (Channel),  DMA4_CSR_RESET);\r
\r
  /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */\r
  /*--------------------------------------------------------------*/\r
  //write enable bit\r
  MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Turn of DMA channel configured by EnableDma().\r
\r
  @param  Channel               DMA Channel to configure\r
  @param  SuccesMask            Bits in DMA4_CSR register indicate EFI_SUCCESS\r
  @param  ErrorMask             Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR\r
\r
  @retval EFI_SUCCESS           DMA hardware disabled\r
  @retval EFI_INVALID_PARAMETER Channel is not valid\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DisableDmaChannel (\r
  IN  UINTN       Channel,\r
  IN  UINT32      SuccessMask,\r
  IN  UINT32      ErrorMask\r
  )\r
{\r
  EFI_STATUS  Status = EFI_SUCCESS;\r
  UINT32      Reg;\r
\r
\r
  if (Channel > DMA4_MAX_CHANNEL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  do {\r
    Reg = MmioRead32 (DMA4_CSR(Channel));\r
    if ((Reg & ErrorMask) != 0) {\r
      Status = EFI_DEVICE_ERROR;\r
      DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));\r
      break;\r
    }\r
  } while ((Reg & SuccessMask) != SuccessMask);\r
\r
\r
  // Disable all status bits and clear them\r
  MmioWrite32 (DMA4_CICR (Channel), 0);\r
  MmioWrite32 (DMA4_CSR (Channel),  DMA4_CSR_RESET);\r
\r
  MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));\r
  return Status;\r
}\r
\r
\r
\r