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SecurityPkg: Add definition of EFI_CC_EVENT_HOB_GUID
[mirror_edk2.git] / OvmfPkg / OvmfPkg.dec
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7b202cb0 1## @file\r
49ba9447 2# EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
3#\r
e557442e 4# Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>\r
10fa47e5 5# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
e557442e 6# Copyright (c) 2014, Pluribus Networks, Inc.\r
49ba9447 7#\r
b26f0cf9 8# SPDX-License-Identifier: BSD-2-Clause-Patent\r
49ba9447 9#\r
7b202cb0 10##\r
49ba9447 11\r
12[Defines]\r
46293a42 13 DEC_SPECIFICATION = 0x00010005\r
49ba9447 14 PACKAGE_NAME = OvmfPkg\r
15 PACKAGE_GUID = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5\r
16 PACKAGE_VERSION = 0.1\r
17\r
50944545 18[Includes]\r
19 Include\r
eb7cad3f 20 Csm/Include\r
50944545 21\r
28b29a70 22[LibraryClasses]\r
e557442e
LE		 23 ## @libraryclass Access bhyve's firmware control interface.\r
24 BhyveFwCtlLib|Include/Library/BhyveFwCtlLib.h\r
0cb48007
DM		 25\r
26 ## @libraryclass Verify blobs read from the VMM\r
27 BlobVerifierLib|Include/Library/BlobVerifierLib.h\r
e557442e 28\r
f6c6c020 29 ## @libraryclass Loads and boots a Linux kernel image\r
30 #\r
31 LoadLinuxLib|Include/Library/LoadLinuxLib.h\r
32\r
7cfc48fe
LE		 33 ## @libraryclass Declares helper functions for Secure Encrypted\r
34 # Virtualization (SEV) guests.\r
35 MemEncryptSevLib|Include/Library/MemEncryptSevLib.h\r
36\r
5aa80186
MX		 37 ## @libraryclass Declares helper functions for TDX guests.\r
38 #\r
39 MemEncryptTdxLib|Include/Library/MemEncryptTdxLib.h\r
40\r
28b29a70 41 ## @libraryclass Save and restore variables using a file\r
42 #\r
43 NvVarsFileLib|Include/Library/NvVarsFileLib.h\r
44\r
392a3146
LE		 45 ## @libraryclass Provides services to work with PCI capabilities in PCI\r
46 # config space.\r
47 PciCapLib|Include/Library/PciCapLib.h\r
48\r
02b9a834
LE		 49 ## @libraryclass Layered on top of PciCapLib, allows clients to plug an\r
50 # EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config\r
51 # space access.\r
52 PciCapPciIoLib|Include/Library/PciCapPciIoLib.h\r
53\r
6a744d40
LE		 54 ## @libraryclass Layered on top of PciCapLib, allows clients to plug a\r
55 # PciSegmentLib backend into PciCapLib, for config space\r
56 # access.\r
57 PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h\r
58\r
7a6172f8
JC		 59 ## @libraryclass Provide common utility functions to PciHostBridgeLib\r
60 # instances in ArmVirtPkg and OvmfPkg.\r
61 PciHostBridgeUtilityLib|Include/Library/PciHostBridgeUtilityLib.h\r
62\r
77874cee
LE		 63 ## @libraryclass Register a status code handler for printing the Boot\r
64 # Manager's LoadImage() and StartImage() preparations, and\r
65 # return codes, to the UEFI console.\r
66 PlatformBmPrintScLib|Include/Library/PlatformBmPrintScLib.h\r
67\r
7cfc48fe
LE		 68 ## @libraryclass Customize FVB2 protocol member functions for a platform.\r
69 PlatformFvbLib|Include/Library/PlatformFvbLib.h\r
70\r
f1ec65ba 71 ## @libraryclass Access QEMU's firmware configuration interface\r
72 #\r
73 QemuFwCfgLib|Include/Library/QemuFwCfgLib.h\r
74\r
f70b071e
LE		 75 ## @libraryclass S3 support for QEMU fw_cfg\r
76 #\r
77 QemuFwCfgS3Lib|Include/Library/QemuFwCfgS3Lib.h\r
78\r
611c7f11
LE		 79 ## @libraryclass Parse the contents of named fw_cfg files as simple\r
80 # (scalar) data types.\r
81 QemuFwCfgSimpleParserLib|Include/Library/QemuFwCfgSimpleParserLib.h\r
82\r
cca7475b
LE		 83 ## @libraryclass Rewrite the BootOrder NvVar based on QEMU's "bootorder"\r
84 # fw_cfg file.\r
85 #\r
86 QemuBootOrderLib|Include/Library/QemuBootOrderLib.h\r
87\r
28de1a55
AB		 88 ## @libraryclass Load a kernel image and command line passed to QEMU via\r
89 # the command line\r
90 #\r
91 QemuLoadImageLib|Include/Library/QemuLoadImageLib.h\r
92\r
28b29a70 93 ## @libraryclass Serialize (and deserialize) variables\r
94 #\r
95 SerializeVariablesLib|Include/Library/SerializeVariablesLib.h\r
96\r
7cfc48fe
LE		 97 ## @libraryclass Declares utility functions for virtio device drivers.\r
98 VirtioLib|Include/Library/VirtioLib.h\r
99\r
100 ## @libraryclass Install Virtio Device Protocol instances on virtio-mmio\r
101 # transports.\r
102 VirtioMmioDeviceLib|Include/Library/VirtioMmioDeviceLib.h\r
103\r
cd8ff8fd
AB		 104 ## @libraryclass Invoke Xen hypercalls\r
105 #\r
106 XenHypercallLib|Include/Library/XenHypercallLib.h\r
107\r
0169352e
AB		 108 ## @libraryclass Manage XenBus device path and I/O handles\r
109 #\r
110 XenIoMmioLib|Include/Library/XenIoMmioLib.h\r
111\r
f496443e
AP		 112 ## @libraryclass Get information about Xen\r
113 #\r
114 XenPlatformLib|Include/Library/XenPlatformLib.h\r
115\r
6a608255
MX		 116 ## @libraryclass TdxMailboxLib\r
117 #\r
118 TdxMailboxLib|Include/Library/TdxMailboxLib.h\r
119\r
57bcfc3b
MX		 120 ## @libraryclass PlatformInitLib\r
121 #\r
122 PlatformInitLib|Include/Library/PlatformInitLib.h\r
123\r
4fe26784
MX		 124 ## @libraryclass PeilessStartupLib\r
125 #\r
126 PeilessStartupLib|Include/Library/PeilessStartupLib.h\r
127\r
7b202cb0 128[Guids]\r
1dc875a7
AB		 129 gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r
130 gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r
131 gOvmfPkKek1AppPrefixGuid = {0x4e32566d, 0x8e9e, 0x4f52, {0x81, 0xd3, 0x5b, 0xb9, 0x71, 0x5f, 0x97, 0x27}}\r
132 gOvmfPlatformConfigGuid = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}\r
133 gVirtioMmioTransportGuid = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}\r
134 gQemuRamfbGuid = {0x557423a1, 0x63ab, 0x406c, {0xbe, 0x7e, 0x91, 0xcd, 0xbc, 0x08, 0xc4, 0x57}}\r
135 gXenBusRootDeviceGuid = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}\r
136 gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}\r
137 gMicrosoftVendorGuid = {0x77fa9abd, 0x0359, 0x4d32, {0xbd, 0x60, 0x28, 0xf4, 0xe7, 0x8f, 0x78, 0x4b}}\r
138 gEfiLegacyBiosGuid = {0x2E3044AC, 0x879F, 0x490F, {0x97, 0x60, 0xBB, 0xDF, 0xAF, 0x69, 0x5F, 0x50}}\r
139 gEfiLegacyDevOrderVariableGuid = {0xa56074db, 0x65fe, 0x45f7, {0xbd, 0x21, 0x2d, 0x2b, 0xdd, 0x8e, 0x96, 0x52}}\r
1dc875a7 140 gQemuKernelLoaderFsMediaGuid = {0x1428f772, 0xb64a, 0x441e, {0xb8, 0xc3, 0x9e, 0xbd, 0xd7, 0xf8, 0x93, 0xc7}}\r
b261a30c 141 gGrubFileGuid = {0xb5ae312c, 0xbc8a, 0x43b1, {0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}}\r
96201ae7 142 gConfidentialComputingSecretGuid = {0xadf956ad, 0xe98c, 0x484c, {0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}}\r
67484aed 143 gConfidentialComputingSevSnpBlobGuid = {0x067b1f5f, 0xcf26, 0x44c5, {0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}}\r
cf17156d 144 gUefiOvmfPkgPlatformInfoGuid = {0xdec9b486, 0x1f16, 0x47c7, {0x8f, 0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}}\r
49ba9447 145\r
6b3d196a
AB		 146[Ppis]\r
147 # PPI whose presence in the PPI database signals that the TPM base address\r
148 # has been discovered and recorded\r
1dc875a7 149 gOvmfTpmDiscoveredPpiGuid = {0xb9a61ad0, 0x2802, 0x41f3, {0xb5, 0x13, 0x96, 0x51, 0xce, 0x6b, 0xd5, 0x75}}\r
6b3d196a 150\r
a3f12cd4
TL		 151 # This PPI signals that accessing the MMIO range of the TPM is possible in\r
152 # the PEI phase, regardless of memory encryption\r
153 gOvmfTpmMmioAccessiblePpiGuid = {0x35c84ff2, 0x7bfe, 0x453d, {0x84, 0x5f, 0x68, 0x3a, 0x49, 0x2c, 0xf7, 0xb7}}\r
154\r
ad629b5c
MX		 155 gEfiPeiMpInitLibMpDepPpiGuid = {0x138f9cf4, 0xf0e7, 0x4721, { 0x8f, 0x49, 0xf5, 0xff, 0xec, 0xf4, 0x2d, 0x40}}\r
156 gEfiPeiMpInitLibUpDepPpiGuid = {0xb590774, 0xbc67, 0x49f4, { 0xa7, 0xdb, 0xe8, 0x2e, 0x89, 0xe6, 0xb5, 0xd6}}\r
157\r
b0f51446 158[Protocols]\r
1dc875a7
AB		 159 gVirtioDeviceProtocolGuid = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}\r
160 gXenBusProtocolGuid = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}\r
161 gXenIoProtocolGuid = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}\r
162 gIoMmuAbsentProtocolGuid = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}\r
163 gEfiLegacy8259ProtocolGuid = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}}\r
164 gEfiFirmwareVolumeProtocolGuid = {0x389F751F, 0x1838, 0x4388, {0x83, 0x90, 0xcd, 0x81, 0x54, 0xbd, 0x27, 0xf8}}\r
165 gEfiIsaAcpiProtocolGuid = {0x64a892dc, 0x5561, 0x4536, {0x92, 0xc7, 0x79, 0x9b, 0xfc, 0x18, 0x33, 0x55}}\r
166 gEfiIsaIoProtocolGuid = {0x7ee2bd44, 0x3da0, 0x11d4, {0x9a, 0x38, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}\r
167 gEfiLegacyBiosProtocolGuid = {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}}\r
168 gEfiLegacyBiosPlatformProtocolGuid = {0x783658a3, 0x4172, 0x4421, {0xa2, 0x99, 0xe0, 0x09, 0x07, 0x9c, 0x0c, 0xb4}}\r
169 gEfiLegacyInterruptProtocolGuid = {0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}}\r
170 gEfiVgaMiniPortProtocolGuid = {0xc7735a2f, 0x88f5, 0x4882, {0xae, 0x63, 0xfa, 0xac, 0x8c, 0x8b, 0x86, 0xb3}}\r
171 gOvmfLoadedX86LinuxKernelProtocolGuid = {0xa3edc05d, 0xb618, 0x4ff6, {0x95, 0x52, 0x76, 0xd7, 0x88, 0x63, 0x43, 0xc8}}\r
fae5c146 172 gQemuAcpiTableNotifyProtocolGuid = {0x928939b2, 0x4235, 0x462f, {0x95, 0x80, 0xf6, 0xa2, 0xb2, 0xc2, 0x1a, 0x4f}}\r
ad629b5c
MX		 173 gEfiMpInitLibMpDepProtocolGuid = {0xbb00a5ca, 0x8ce, 0x462f, {0xa5, 0x37, 0x43, 0xc7, 0x4a, 0x82, 0x5c, 0xa4}}\r
174 gEfiMpInitLibUpDepProtocolGuid = {0xa9e7cef1, 0x5682, 0x42cc, {0xb1, 0x23, 0x99, 0x30, 0x97, 0x3f, 0x4a, 0x9f}}\r
b0f51446 175\r
61069836 176[PcdsFixedAtBuild]\r
b36f701d
JJ		 177 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0\r
178 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1\r
179 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15\r
180 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16\r
61069836 181\r
b90aefa9 182 ## This flag is used to control the destination port for PlatformDebugLibIoPort\r
183 gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4\r
184\r
37078a63 185 ## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and\r
186 # LUNs are retrieved from the host during virtio-scsi setup.\r
187 # MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun\r
188 # possible devices. This can take extremely long, for example with\r
189 # MaxTarget=255 and MaxLun=16383. The *inclusive* constants below limit\r
190 # MaxTarget and MaxLun, independently, should the host report higher values,\r
191 # so that scanning the number of devices given by their product is still\r
192 # acceptably fast.\r
193 gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6\r
194 gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7\r
195\r
7efce2e5
LA		 196 ## Sets the *inclusive* number of targets and LUNs that PvScsi exposes for\r
197 # scan by ScsiBusDxe.\r
198 # As specified above for VirtioScsi, ScsiBusDxe scans all MaxTarget * MaxLun\r
199 # possible devices, which can take extremely long. Thus, the below constants\r
200 # are used so that scanning the number of devices given by their product\r
201 # is still acceptably fast.\r
202 gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiMaxTargetLimit|64|UINT8|0x36\r
203 gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiMaxLunLimit|0|UINT8|0x37\r
204\r
c4c15b87
LA		 205 ## After PvScsiDxe sends a SCSI request to the device, it waits for\r
206 # the request completion in a polling loop.\r
207 # This constant defines how many micro-seconds to wait between each\r
208 # polling loop iteration.\r
209 gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiWaitForCmpStallInUsecs|5|UINT32|0x38\r
210\r
093cceaf
NL		 211 ## Set the *inclusive* number of targets that MptScsi exposes for scan\r
212 # by ScsiBusDxe.\r
213 gUefiOvmfPkgTokenSpaceGuid.PcdMptScsiMaxTargetLimit|7|UINT8|0x39\r
214\r
505812ae 215 ## Microseconds to stall between polling for MptScsi request result\r
d9269d69 216 gUefiOvmfPkgTokenSpaceGuid.PcdMptScsiStallPerPollUsec|5|UINT32|0x3a\r
505812ae 217\r
12d99b8f
GL		 218 ## Set the *inclusive* number of targets and LUNs that LsiScsi exposes for\r
219 # scan by ScsiBusDxe.\r
220 gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiMaxTargetLimit|7|UINT8|0x3b\r
221 gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiMaxLunLimit|0|UINT8|0x3c\r
222\r
31830b07
GL		 223 ## Microseconds to stall between polling for LsiScsi request result\r
224 gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiStallPerPollUsec|5|UINT32|0x3d\r
225\r
501e08fc
JJ		 226 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8\r
227 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9\r
228 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa\r
229 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb\r
230 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc\r
231 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd\r
232 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe\r
233 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf\r
b382ede3
JJ		 234 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11\r
235 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12\r
7cb6b0e0
JJ		 236 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13\r
237 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14\r
6a7cba79
LE		 238 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18\r
239 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19\r
ad43bc6b 240 gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a\r
9beac0d8 241 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f\r
501e08fc 242\r
460ffed2
HW		 243 ## Pcd8259LegacyModeMask defines the default mask value for platform. This\r
244 # value is determined.\r
245 # 1) If platform only support pure UEFI, value should be set to 0xFFFF or\r
246 # 0xFFFE; Because only clock interrupt is allowed in legacy mode in pure\r
247 # UEFI platform.\r
248 # 2) If platform install CSM and use thunk module:\r
249 # a) If thunk call provided by CSM binary requires some legacy interrupt\r
250 # support, the corresponding bit should be opened as 0.\r
251 # For example, if keyboard interfaces provided CSM binary use legacy\r
252 # keyboard interrupt in 8259 bit 1, then the value should be set to\r
253 # 0xFFFC.\r
254 # b) If all thunk call provied by CSM binary do not require legacy\r
255 # interrupt support, value should be set to 0xFFFF or 0xFFFE.\r
256 #\r
257 # The default value of legacy mode mask could be changed by\r
258 # EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it\r
259 # except some special cases such as when initializing the CSM binary, it\r
260 # should be set to 0xFFFF to mask all legacy interrupt. Please restore the\r
261 # original legacy mask value if changing is made for these special case.\r
262 gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x3\r
263\r
264 ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy\r
265 # mode's interrrupt controller.\r
266 # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r
267 gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x5\r
268\r
51e55d81
HW		 269 ## Indicates if BiosVideo driver will switch to 80x25 Text VGA Mode when\r
270 # exiting boot service.\r
271 # TRUE - Switch to Text VGA Mode.\r
272 # FALSE - Does not switch to Text VGA Mode.\r
273 gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoSetTextVgaModeEnable|FALSE|BOOLEAN|0x28\r
274\r
275 ## Indicates if BiosVideo driver will check for VESA BIOS Extension service\r
276 # support.\r
277 # TRUE - Check for VESA BIOS Extension service.\r
278 # FALSE - Does not check for VESA BIOS Extension service.\r
279 gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE|BOOLEAN|0x29\r
280\r
281 ## Indicates if BiosVideo driver will check for VGA service support.\r
282 # NOTE: If both PcdBiosVideoCheckVbeEnable and PcdBiosVideoCheckVgaEnable\r
283 # are set to FALSE, that means Graphics Output protocol will not be\r
284 # installed, the VGA miniport protocol will be installed instead.\r
285 # TRUE - Check for VGA service.<BR>\r
286 # FALSE - Does not check for VGA service.<BR>\r
287 gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE|BOOLEAN|0x2a\r
288\r
289 ## Indicates if memory space for legacy region will be set as cacheable.\r
290 # TRUE - Set cachebility for legacy region.\r
291 # FALSE - Does not set cachebility for legacy region.\r
292 gUefiOvmfPkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|TRUE|BOOLEAN|0x2b\r
293\r
294 ## Specify memory size with bytes to reserve EBDA below 640K for OPROM.\r
295 # The value should be a multiple of 4KB.\r
296 gUefiOvmfPkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x2c\r
297\r
298 ## Specify memory base address for OPROM to find free memory.\r
299 # Some OPROMs do not use EBDA or PMM to allocate memory for its usage,\r
300 # instead they find the memory filled with zero from 0x20000.\r
301 # The value should be a multiple of 4KB.\r
302 # The range should be below the EBDA reserved range from\r
303 # (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to\r
304 # CONVENTIONAL_MEMORY_TOP.\r
305 gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemoryBase|0x60000|UINT32|0x2d\r
306\r
307 ## Specify memory size with bytes for OPROM to find free memory.\r
308 # The value should be a multiple of 4KB. And the range should be below the\r
309 # EBDA reserved range from\r
310 # (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to\r
311 # CONVENTIONAL_MEMORY_TOP.\r
312 gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemorySize|0x28000|UINT32|0x2e\r
313\r
314 ## Specify the end of address below 1MB for the OPROM.\r
315 # The last shadowed OpROM should not exceed this address.\r
316 gUefiOvmfPkgTokenSpaceGuid.PcdEndOpromShadowAddress|0xdffff|UINT32|0x2f\r
317\r
318 ## Specify the low PMM (Post Memory Manager) size with bytes below 1MB.\r
319 # The value should be a multiple of 4KB.\r
320 # @Prompt Low PMM (Post Memory Manager) Size\r
321 gUefiOvmfPkgTokenSpaceGuid.PcdLowPmmMemorySize|0x10000|UINT32|0x30\r
322\r
323 ## Specify the high PMM (Post Memory Manager) size with bytes above 1MB.\r
324 # The value should be a multiple of 4KB.\r
325 gUefiOvmfPkgTokenSpaceGuid.PcdHighPmmMemorySize|0x400000|UINT32|0x31\r
326\r
93314ae5
AP		 327 gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr|0x0|UINT32|0x17\r
328 gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize|0x0|UINT32|0x32\r
329\r
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AP		 330 ## Number of page frames to use for storing grant table entries.\r
331 gUefiOvmfPkgTokenSpaceGuid.PcdXenGrantFrames|4|UINT32|0x33\r
332\r
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TL		 333 ## Specify the extra page table needed to mark the GHCB as unencrypted.\r
334 # The value should be a multiple of 4KB for each.\r
335 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|0x0|UINT32|0x3e\r
336 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize|0x0|UINT32|0x3f\r
337\r
338 ## The base address of the SEC GHCB page used by SEV-ES.\r
339 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|0|UINT32|0x40\r
340 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize|0|UINT32|0x41\r
5667dc43
TL		 341 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase|0|UINT32|0x44\r
342 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize|0|UINT32|0x45\r
6995a1b7 343\r
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JB		 344 ## The base address and size of the SEV Launch Secret Area provisioned\r
345 # after remote attestation. If this is set in the .fdf, the platform\r
346 # is responsible for protecting the area from DXE phase overwrites.\r
347 gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase|0x0|UINT32|0x42\r
348 gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretSize|0x0|UINT32|0x43\r
349\r
0deeab36
JB		 350 ## The base address and size of a hash table confirming allowed\r
351 # parameters to be passed in via the Qemu firmware configuration\r
352 # device\r
353 gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableBase|0x0|UINT32|0x47\r
354 gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableSize|0x0|UINT32|0x48\r
355\r
80e67af9
BS		 356 ## The base address and size of the work area used during the SEC\r
357 # phase by the SEV and TDX supports.\r
358 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase|0|UINT32|0x49\r
359 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize|0|UINT32|0x50\r
360\r
361 ## The work area contains a fixed size header in the Include/WorkArea.h.\r
362 # The size of this header is used early boot, and is provided through\r
363 # a fixed PCD. It need to be kept in sync with any changes to the\r
364 # header definition.\r
79019c7a 365 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader|4|UINT32|0x51\r
80e67af9 366\r
c9ec74a1
MX		 367 ## The base address and size of the TDX Cfv base and size.\r
368 gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase|0|UINT32|0x52\r
369 gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset|0|UINT32|0x53\r
370 gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize|0|UINT32|0x54\r
371\r
372 ## The base address and size of the TDX Bfv base and size.\r
373 gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase|0|UINT32|0x55\r
374 gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset|0|UINT32|0x56\r
375 gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize|0|UINT32|0x57\r
80e67af9 376\r
707c71a0
BS		 377 ## The base address and size of the SEV-SNP Secrets Area that contains\r
378 # the VM platform communication key used to send and recieve the\r
379 # messages to the PSP. If this is set in the .fdf, the platform\r
380 # is responsible to reserve this area from DXE phase overwrites.\r
381 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsBase|0|UINT32|0x58\r
382 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsSize|0|UINT32|0x59\r
383\r
cca9cd3d
BS		 384 ## The base address and size of a CPUID Area that contains the hypervisor\r
385 # provided CPUID results. In the case of SEV-SNP, the CPUID results are\r
386 # filtered by the SEV-SNP firmware. If this is set in the .fdf, the\r
387 # platform is responsible to reserve this area from DXE phase overwrites.\r
388 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase|0|UINT32|0x60\r
389 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize|0|UINT32|0x61\r
390\r
202fb22b
BS		 391 ## The range of memory that is validated by the SEC phase.\r
392 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedStart|0|UINT32|0x62\r
393 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedEnd|0|UINT32|0x63\r
b22ac35b
MX		 394\r
395 ## The Tdx accept page size. 0x1000(4k),0x200000(2M)\r
396 gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize|0x200000|UINT32|0x65\r
202fb22b 397\r
70c66df5 398[PcdsDynamic, PcdsDynamicEx]\r
85c0b5ee 399 gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2\r
9d35ac26 400 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10\r
d55004da 401 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b\r
6fbef93e 402 gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21\r
49ba9447 403\r
c4df7fd0
LE		 404 ## The IO port aperture shared by all PCI root bridges.\r
405 #\r
406 gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22\r
407 gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23\r
408\r
03845e90
LE		 409 ## The 32-bit MMIO aperture shared by all PCI root bridges.\r
410 #\r
411 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24\r
412 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25\r
413\r
7e5b1b67
LE		 414 ## The 64-bit MMIO aperture shared by all PCI root bridges.\r
415 #\r
416 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26\r
417 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27\r
418\r
966dbaf4 419 ## The following setting controls how many megabytes we configure as TSEG on\r
d04b72c6
LE		 420 # Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults\r
421 # cause undefined behavior. During boot, the PCD is updated by PlatformPei\r
422 # to reflect the extended TSEG size, if one is advertized by QEMU.\r
966dbaf4 423 #\r
d04b72c6 424 # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).\r
966dbaf4
LE		 425 gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20\r
426\r
d74d56fc
LE		 427 ## Set to TRUE by PlatformPei if the Q35 board supports the "SMRAM at default\r
428 # SMBASE" feature.\r
429 #\r
430 # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).\r
431 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE|BOOLEAN|0x34\r
432\r
8ade9d42
AA		 433 ## This PCD adds a communication channel between OVMF's SmmCpuFeaturesLib\r
434 # instance in PiSmmCpuDxeSmm, and CpuHotplugSmm.\r
435 gUefiOvmfPkgTokenSpaceGuid.PcdCpuHotEjectDataAddress|0|UINT64|0x46\r
436\r
929804b1
GH		 437 ## This PCD tracks where PcdVideo{Horizontal,Vertical}Resolution\r
438 # values are coming from.\r
439 # 0 - unset (defaults from platform dsc)\r
440 # 1 - set from PlatformConfig\r
441 # 2 - set by GOP Driver.\r
442 gUefiOvmfPkgTokenSpaceGuid.PcdVideoResolutionSource|0|UINT8|0x64\r
443\r
e05061c5 444[PcdsFeatureFlag]\r
2f9c55cc 445 gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c\r
43336916 446 gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d\r
1f695483
LE		 447\r
448 ## This feature flag enables SMM/SMRAM support. Note that it also requires\r
449 # such support from the underlying QEMU instance; if that support is not\r
450 # present, the firmware will reject continuing after a certain point.\r
451 #\r
452 # The flag also acts as a general "security switch"; when TRUE, many\r
453 # components will change behavior, with the goal of preventing a malicious\r
454 # runtime OS from tampering with firmware structures (special memory ranges\r
455 # used by OVMF, the varstore pflash chip, LockBox etc).\r
456 gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e\r
50f911d2
LE		 457\r
458 ## Informs modules (including pre-DXE-phase modules) whether the platform\r
459 # firmware contains a CSM (Compatibility Support Module).\r
460 #\r
461 gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable|FALSE|BOOLEAN|0x35\r
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