OvmfPkg/PlatformPei: debug log "etc/reserved-memory-end" from fw_cfg
[mirror_edk2.git] / OvmfPkg / PlatformPei / MemDetect.c
CommitLineData
49ba9447 1/**@file\r
2 Memory Detection for Virtual Machines.\r
3\r
035ce3b3 4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
56d7640a 5 This program and the accompanying materials\r
49ba9447 6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13Module Name:\r
14\r
15 MemDetect.c\r
16\r
17**/\r
18\r
19//\r
20// The package level header files this module uses\r
21//\r
1fceaddb 22#include <IndustryStandard/E820.h>\r
d5e06444 23#include <IndustryStandard/Q35MchIch9.h>\r
49ba9447 24#include <PiPei.h>\r
25\r
26//\r
27// The Library classes this module consumes\r
28//\r
d5e06444 29#include <Library/BaseLib.h>\r
6a7cba79 30#include <Library/BaseMemoryLib.h>\r
49ba9447 31#include <Library/DebugLib.h>\r
32#include <Library/HobLib.h>\r
33#include <Library/IoLib.h>\r
c1c2669c 34#include <Library/PcdLib.h>\r
d5e06444 35#include <Library/PciLib.h>\r
49ba9447 36#include <Library/PeimEntryPoint.h>\r
37#include <Library/ResourcePublicationLib.h>\r
e8e5cd4a 38#include <Library/MtrrLib.h>\r
7e5b1b67 39#include <Library/QemuFwCfgLib.h>\r
49ba9447 40\r
41#include "Platform.h"\r
42#include "Cmos.h"\r
43\r
bc89fe48
LE
44UINT8 mPhysMemAddressWidth;\r
45\r
45d87081
LE
46STATIC UINT32 mS3AcpiReservedMemoryBase;\r
47STATIC UINT32 mS3AcpiReservedMemorySize;\r
48\r
23bfb5c0
LE
49STATIC UINT16 mQ35TsegMbytes;\r
50\r
51VOID\r
52Q35TsegMbytesInitialization (\r
53 VOID\r
54 )\r
55{\r
d5e06444
LE
56 UINT16 ExtendedTsegMbytes;\r
57 RETURN_STATUS PcdStatus;\r
58\r
59 if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
60 DEBUG ((\r
61 DEBUG_ERROR,\r
62 "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
63 "only DID=0x%04x (Q35) is supported\n",\r
64 __FUNCTION__,\r
65 mHostBridgeDevId,\r
66 INTEL_Q35_MCH_DEVICE_ID\r
67 ));\r
68 ASSERT (FALSE);\r
69 CpuDeadLoop ();\r
70 }\r
71\r
72 //\r
73 // Check if QEMU offers an extended TSEG.\r
74 //\r
75 // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r
76 // register, and reading back the register.\r
77 //\r
78 // On a QEMU machine type that does not offer an extended TSEG, the initial\r
79 // write overwrites whatever value a malicious guest OS may have placed in\r
80 // the (unimplemented) register, before entering S3 or rebooting.\r
81 // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r
82 //\r
83 // On a QEMU machine type that offers an extended TSEG, the initial write\r
84 // triggers an update to the register. Subsequently, the value read back\r
85 // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r
86 // number of megabytes.\r
87 //\r
88 PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r
89 ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r
90 if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r
91 mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
92 return;\r
93 }\r
94\r
95 DEBUG ((\r
96 DEBUG_INFO,\r
97 "%a: QEMU offers an extended TSEG (%d MB)\n",\r
98 __FUNCTION__,\r
99 ExtendedTsegMbytes\r
100 ));\r
101 PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r
102 ASSERT_RETURN_ERROR (PcdStatus);\r
103 mQ35TsegMbytes = ExtendedTsegMbytes;\r
23bfb5c0
LE
104}\r
105\r
106\r
1fceaddb
LE
107/**\r
108 Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside\r
109 of the 32-bit address range.\r
110\r
111 Find the highest exclusive >=4GB RAM address, or produce memory resource\r
112 descriptor HOBs for RAM entries that start at or above 4GB.\r
113\r
114 @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()\r
115 produces memory resource descriptor HOBs for RAM\r
116 entries that start at or above 4GB.\r
117\r
118 Otherwise, MaxAddress holds the highest exclusive\r
119 >=4GB RAM address on output. If QEMU's fw_cfg E820\r
120 RAM map contains no RAM entry that starts outside of\r
121 the 32-bit address range, then MaxAddress is exactly\r
122 4GB on output.\r
123\r
124 @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.\r
125\r
126 @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a\r
127 whole multiple of sizeof(EFI_E820_ENTRY64). No\r
128 RAM entry was processed.\r
129\r
130 @return Error codes from QemuFwCfgFindFile(). No RAM\r
131 entry was processed.\r
132**/\r
133STATIC\r
134EFI_STATUS\r
135ScanOrAdd64BitE820Ram (\r
136 OUT UINT64 *MaxAddress OPTIONAL\r
137 )\r
138{\r
139 EFI_STATUS Status;\r
140 FIRMWARE_CONFIG_ITEM FwCfgItem;\r
141 UINTN FwCfgSize;\r
142 EFI_E820_ENTRY64 E820Entry;\r
143 UINTN Processed;\r
144\r
145 Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);\r
146 if (EFI_ERROR (Status)) {\r
147 return Status;\r
148 }\r
149 if (FwCfgSize % sizeof E820Entry != 0) {\r
150 return EFI_PROTOCOL_ERROR;\r
151 }\r
152\r
153 if (MaxAddress != NULL) {\r
154 *MaxAddress = BASE_4GB;\r
155 }\r
156\r
157 QemuFwCfgSelectItem (FwCfgItem);\r
158 for (Processed = 0; Processed < FwCfgSize; Processed += sizeof E820Entry) {\r
159 QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry);\r
160 DEBUG ((\r
161 DEBUG_VERBOSE,\r
162 "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",\r
163 __FUNCTION__,\r
164 E820Entry.BaseAddr,\r
165 E820Entry.Length,\r
166 E820Entry.Type\r
167 ));\r
168 if (E820Entry.Type == EfiAcpiAddressRangeMemory &&\r
169 E820Entry.BaseAddr >= BASE_4GB) {\r
170 if (MaxAddress == NULL) {\r
171 UINT64 Base;\r
172 UINT64 End;\r
173\r
174 //\r
175 // Round up the start address, and round down the end address.\r
176 //\r
177 Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);\r
178 End = (E820Entry.BaseAddr + E820Entry.Length) &\r
179 ~(UINT64)EFI_PAGE_MASK;\r
180 if (Base < End) {\r
181 AddMemoryRangeHob (Base, End);\r
182 DEBUG ((\r
183 DEBUG_VERBOSE,\r
184 "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",\r
185 __FUNCTION__,\r
186 Base,\r
187 End\r
188 ));\r
189 }\r
190 } else {\r
191 UINT64 Candidate;\r
192\r
193 Candidate = E820Entry.BaseAddr + E820Entry.Length;\r
194 if (Candidate > *MaxAddress) {\r
195 *MaxAddress = Candidate;\r
196 DEBUG ((\r
197 DEBUG_VERBOSE,\r
198 "%a: MaxAddress=0x%Lx\n",\r
199 __FUNCTION__,\r
200 *MaxAddress\r
201 ));\r
202 }\r
203 }\r
204 }\r
205 }\r
206 return EFI_SUCCESS;\r
207}\r
208\r
209\r
4b455f7b 210UINT32\r
c0e10976 211GetSystemMemorySizeBelow4gb (\r
4b455f7b 212 VOID\r
49ba9447 213 )\r
214{\r
215 UINT8 Cmos0x34;\r
216 UINT8 Cmos0x35;\r
217\r
218 //\r
219 // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r
220 // * CMOS(0x35) is the high byte\r
221 // * CMOS(0x34) is the low byte\r
222 // * The size is specified in 64kb chunks\r
223 // * Since this is memory above 16MB, the 16MB must be added\r
224 // into the calculation to get the total memory size.\r
225 //\r
226\r
227 Cmos0x34 = (UINT8) CmosRead8 (0x34);\r
228 Cmos0x35 = (UINT8) CmosRead8 (0x35);\r
229\r
c4046161 230 return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
49ba9447 231}\r
232\r
233\r
c0e10976 234STATIC\r
235UINT64\r
236GetSystemMemorySizeAbove4gb (\r
237 )\r
238{\r
239 UINT32 Size;\r
240 UINTN CmosIndex;\r
241\r
242 //\r
243 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r
244 // * CMOS(0x5d) is the most significant size byte\r
245 // * CMOS(0x5c) is the middle size byte\r
246 // * CMOS(0x5b) is the least significant size byte\r
247 // * The size is specified in 64kb chunks\r
248 //\r
249\r
250 Size = 0;\r
251 for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r
252 Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r
253 }\r
254\r
255 return LShiftU64 (Size, 16);\r
256}\r
257\r
bc89fe48 258\r
d5371680
LE
259/**\r
260 Return the highest address that DXE could possibly use, plus one.\r
261**/\r
262STATIC\r
263UINT64\r
264GetFirstNonAddress (\r
265 VOID\r
266 )\r
267{\r
268 UINT64 FirstNonAddress;\r
7e5b1b67
LE
269 UINT64 Pci64Base, Pci64Size;\r
270 CHAR8 MbString[7 + 1];\r
271 EFI_STATUS Status;\r
272 FIRMWARE_CONFIG_ITEM FwCfgItem;\r
273 UINTN FwCfgSize;\r
274 UINT64 HotPlugMemoryEnd;\r
32e083c7 275 RETURN_STATUS PcdStatus;\r
d5371680 276\r
1fceaddb
LE
277 //\r
278 // set FirstNonAddress to suppress incorrect compiler/analyzer warnings\r
279 //\r
280 FirstNonAddress = 0;\r
281\r
282 //\r
283 // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM\r
284 // address from it. This can express an address >= 4GB+1TB.\r
285 //\r
286 // Otherwise, get the flat size of the memory above 4GB from the CMOS (which\r
287 // can only express a size smaller than 1TB), and add it to 4GB.\r
288 //\r
289 Status = ScanOrAdd64BitE820Ram (&FirstNonAddress);\r
290 if (EFI_ERROR (Status)) {\r
291 FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r
292 }\r
7e5b1b67
LE
293\r
294 //\r
295 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r
296 // resources to 32-bit anyway. See DegradeResource() in\r
297 // "PciResourceSupport.c".\r
298 //\r
299#ifdef MDE_CPU_IA32\r
300 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
301 return FirstNonAddress;\r
302 }\r
303#endif\r
304\r
305 //\r
306 // Otherwise, in order to calculate the highest address plus one, we must\r
307 // consider the 64-bit PCI host aperture too. Fetch the default size.\r
308 //\r
309 Pci64Size = PcdGet64 (PcdPciMmio64Size);\r
310\r
311 //\r
312 // See if the user specified the number of megabytes for the 64-bit PCI host\r
313 // aperture. The number of non-NUL characters in MbString allows for\r
314 // 9,999,999 MB, which is approximately 10 TB.\r
315 //\r
316 // As signaled by the "X-" prefix, this knob is experimental, and might go\r
317 // away at any time.\r
318 //\r
319 Status = QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem,\r
320 &FwCfgSize);\r
321 if (!EFI_ERROR (Status)) {\r
322 if (FwCfgSize >= sizeof MbString) {\r
323 DEBUG ((EFI_D_WARN,\r
324 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r
325 __FUNCTION__));\r
326 } else {\r
327 QemuFwCfgSelectItem (FwCfgItem);\r
328 QemuFwCfgReadBytes (FwCfgSize, MbString);\r
329 MbString[FwCfgSize] = '\0';\r
330 Pci64Size = LShiftU64 (AsciiStrDecimalToUint64 (MbString), 20);\r
331 }\r
332 }\r
333\r
334 if (Pci64Size == 0) {\r
335 if (mBootMode != BOOT_ON_S3_RESUME) {\r
336 DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n",\r
337 __FUNCTION__));\r
32e083c7
LE
338 PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
339 ASSERT_RETURN_ERROR (PcdStatus);\r
7e5b1b67
LE
340 }\r
341\r
342 //\r
343 // There's nothing more to do; the amount of memory above 4GB fully\r
344 // determines the highest address plus one. The memory hotplug area (see\r
345 // below) plays no role for the firmware in this case.\r
346 //\r
347 return FirstNonAddress;\r
348 }\r
349\r
350 //\r
351 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an\r
352 // absolute, exclusive end address for the memory hotplug area. This area\r
353 // starts right at the end of the memory above 4GB. The 64-bit PCI host\r
354 // aperture must be placed above it.\r
355 //\r
356 Status = QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem,\r
357 &FwCfgSize);\r
358 if (!EFI_ERROR (Status) && FwCfgSize == sizeof HotPlugMemoryEnd) {\r
359 QemuFwCfgSelectItem (FwCfgItem);\r
360 QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);\r
c27c0003
LE
361 DEBUG ((DEBUG_VERBOSE, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__,\r
362 HotPlugMemoryEnd));\r
7e5b1b67
LE
363\r
364 ASSERT (HotPlugMemoryEnd >= FirstNonAddress);\r
365 FirstNonAddress = HotPlugMemoryEnd;\r
366 }\r
367\r
368 //\r
369 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r
370 // that the host can map it with 1GB hugepages. Follow suit.\r
371 //\r
372 Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r
373 Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);\r
374\r
375 //\r
376 // The 64-bit PCI host aperture should also be "naturally" aligned. The\r
377 // alignment is determined by rounding the size of the aperture down to the\r
378 // next smaller or equal power of two. That is, align the aperture by the\r
379 // largest BAR size that can fit into it.\r
380 //\r
381 Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));\r
382\r
383 if (mBootMode != BOOT_ON_S3_RESUME) {\r
384 //\r
385 // The core PciHostBridgeDxe driver will automatically add this range to\r
386 // the GCD memory space map through our PciHostBridgeLib instance; here we\r
387 // only need to set the PCDs.\r
388 //\r
32e083c7
LE
389 PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);\r
390 ASSERT_RETURN_ERROR (PcdStatus);\r
391 PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r
392 ASSERT_RETURN_ERROR (PcdStatus);\r
393\r
7e5b1b67
LE
394 DEBUG ((EFI_D_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
395 __FUNCTION__, Pci64Base, Pci64Size));\r
396 }\r
397\r
398 //\r
399 // The useful address space ends with the 64-bit PCI host aperture.\r
400 //\r
401 FirstNonAddress = Pci64Base + Pci64Size;\r
d5371680
LE
402 return FirstNonAddress;\r
403}\r
404\r
405\r
bc89fe48
LE
406/**\r
407 Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r
408**/\r
409VOID\r
410AddressWidthInitialization (\r
411 VOID\r
412 )\r
413{\r
414 UINT64 FirstNonAddress;\r
415\r
416 //\r
417 // As guest-physical memory size grows, the permanent PEI RAM requirements\r
418 // are dominated by the identity-mapping page tables built by the DXE IPL.\r
419 // The DXL IPL keys off of the physical address bits advertized in the CPU\r
420 // HOB. To conserve memory, we calculate the minimum address width here.\r
421 //\r
d5371680 422 FirstNonAddress = GetFirstNonAddress ();\r
bc89fe48
LE
423 mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r
424\r
425 //\r
426 // If FirstNonAddress is not an integral power of two, then we need an\r
427 // additional bit.\r
428 //\r
429 if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r
430 ++mPhysMemAddressWidth;\r
431 }\r
432\r
433 //\r
434 // The minimum address width is 36 (covers up to and excluding 64 GB, which\r
435 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r
436 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r
437 // can simply assert that here, since 48 bits are good enough for 256 TB.\r
438 //\r
439 if (mPhysMemAddressWidth <= 36) {\r
440 mPhysMemAddressWidth = 36;\r
441 }\r
442 ASSERT (mPhysMemAddressWidth <= 48);\r
443}\r
444\r
445\r
446/**\r
447 Calculate the cap for the permanent PEI memory.\r
448**/\r
449STATIC\r
450UINT32\r
451GetPeiMemoryCap (\r
452 VOID\r
453 )\r
454{\r
455 BOOLEAN Page1GSupport;\r
456 UINT32 RegEax;\r
457 UINT32 RegEdx;\r
458 UINT32 Pml4Entries;\r
459 UINT32 PdpEntries;\r
460 UINTN TotalPages;\r
461\r
462 //\r
463 // If DXE is 32-bit, then just return the traditional 64 MB cap.\r
464 //\r
465#ifdef MDE_CPU_IA32\r
466 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
467 return SIZE_64MB;\r
468 }\r
469#endif\r
470\r
471 //\r
472 // Dependent on physical address width, PEI memory allocations can be\r
473 // dominated by the page tables built for 64-bit DXE. So we key the cap off\r
474 // of those. The code below is based on CreateIdentityMappingPageTables() in\r
475 // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r
476 //\r
477 Page1GSupport = FALSE;\r
478 if (PcdGetBool (PcdUse1GPageTable)) {\r
479 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
480 if (RegEax >= 0x80000001) {\r
481 AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
482 if ((RegEdx & BIT26) != 0) {\r
483 Page1GSupport = TRUE;\r
484 }\r
485 }\r
486 }\r
487\r
488 if (mPhysMemAddressWidth <= 39) {\r
489 Pml4Entries = 1;\r
490 PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
491 ASSERT (PdpEntries <= 0x200);\r
492 } else {\r
493 Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r
494 ASSERT (Pml4Entries <= 0x200);\r
495 PdpEntries = 512;\r
496 }\r
497\r
498 TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
499 (PdpEntries + 1) * Pml4Entries + 1;\r
500 ASSERT (TotalPages <= 0x40201);\r
501\r
502 //\r
503 // Add 64 MB for miscellaneous allocations. Note that for\r
504 // mPhysMemAddressWidth values close to 36, the cap will actually be\r
505 // dominated by this increment.\r
506 //\r
507 return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
508}\r
509\r
510\r
36658fff
WL
511/**\r
512 Publish PEI core memory\r
513\r
514 @return EFI_SUCCESS The PEIM initialized successfully.\r
515\r
516**/\r
517EFI_STATUS\r
518PublishPeiMemory (\r
519 VOID\r
520 )\r
521{\r
522 EFI_STATUS Status;\r
523 EFI_PHYSICAL_ADDRESS MemoryBase;\r
524 UINT64 MemorySize;\r
fc3f005a 525 UINT32 LowerMemorySize;\r
bc89fe48 526 UINT32 PeiMemoryCap;\r
36658fff 527\r
45d87081
LE
528 LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
529 if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
530 //\r
531 // TSEG is chipped from the end of low RAM\r
532 //\r
23bfb5c0 533 LowerMemorySize -= mQ35TsegMbytes * SIZE_1MB;\r
45d87081
LE
534 }\r
535\r
536 //\r
537 // If S3 is supported, then the S3 permanent PEI memory is placed next,\r
538 // downwards. Its size is primarily dictated by CpuMpPei. The formula below\r
539 // is an approximation.\r
540 //\r
541 if (mS3Supported) {\r
542 mS3AcpiReservedMemorySize = SIZE_512KB +\r
45a70db3 543 mMaxCpuCount *\r
45d87081
LE
544 PcdGet32 (PcdCpuApStackSize);\r
545 mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;\r
546 LowerMemorySize = mS3AcpiReservedMemoryBase;\r
547 }\r
548\r
8e54500f 549 if (mBootMode == BOOT_ON_S3_RESUME) {\r
45d87081
LE
550 MemoryBase = mS3AcpiReservedMemoryBase;\r
551 MemorySize = mS3AcpiReservedMemorySize;\r
8e54500f 552 } else {\r
bc89fe48
LE
553 PeiMemoryCap = GetPeiMemoryCap ();\r
554 DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
555 __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r
556\r
8e54500f
JJ
557 //\r
558 // Determine the range of memory to use during PEI\r
559 //\r
efb0f16e
LE
560 // Technically we could lay the permanent PEI RAM over SEC's temporary\r
561 // decompression and scratch buffer even if "secure S3" is needed, since\r
562 // their lifetimes don't overlap. However, PeiFvInitialization() will cover\r
563 // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory\r
564 // allocation HOB, and other allocations served from the permanent PEI RAM\r
565 // shouldn't overlap with that HOB.\r
566 //\r
567 MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r
568 PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
569 PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
8e54500f 570 MemorySize = LowerMemorySize - MemoryBase;\r
bc89fe48
LE
571 if (MemorySize > PeiMemoryCap) {\r
572 MemoryBase = LowerMemorySize - PeiMemoryCap;\r
573 MemorySize = PeiMemoryCap;\r
8e54500f 574 }\r
36658fff
WL
575 }\r
576\r
577 //\r
578 // Publish this memory to the PEI Core\r
579 //\r
580 Status = PublishSystemMemory(MemoryBase, MemorySize);\r
581 ASSERT_EFI_ERROR (Status);\r
582\r
583 return Status;\r
584}\r
585\r
c0e10976 586\r
49ba9447 587/**\r
c034906e 588 Peform Memory Detection for QEMU / KVM\r
49ba9447 589\r
590**/\r
c034906e
JJ
591STATIC\r
592VOID\r
593QemuInitializeRam (\r
594 VOID\r
49ba9447 595 )\r
596{\r
c0e10976 597 UINT64 LowerMemorySize;\r
598 UINT64 UpperMemorySize;\r
79d274b8
LE
599 MTRR_SETTINGS MtrrSettings;\r
600 EFI_STATUS Status;\r
49ba9447 601\r
c034906e 602 DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));\r
49ba9447 603\r
604 //\r
605 // Determine total memory size available\r
606 //\r
c0e10976 607 LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
608 UpperMemorySize = GetSystemMemorySizeAbove4gb ();\r
49ba9447 609\r
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610 if (mBootMode == BOOT_ON_S3_RESUME) {\r
611 //\r
612 // Create the following memory HOB as an exception on the S3 boot path.\r
613 //\r
614 // Normally we'd create memory HOBs only on the normal boot path. However,\r
615 // CpuMpPei specifically needs such a low-memory HOB on the S3 path as\r
616 // well, for "borrowing" a subset of it temporarily, for the AP startup\r
617 // vector.\r
618 //\r
619 // CpuMpPei saves the original contents of the borrowed area in permanent\r
620 // PEI RAM, in a backup buffer allocated with the normal PEI services.\r
621 // CpuMpPei restores the original contents ("returns" the borrowed area) at\r
622 // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before\r
8c0b0b34 623 // transferring control to the OS's wakeup vector in the FACS.\r
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LE
624 //\r
625 // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to\r
626 // restore the original contents. Furthermore, we expect all such PEIMs\r
627 // (CpuMpPei included) to claim the borrowed areas by producing memory\r
628 // allocation HOBs, and to honor preexistent memory allocation HOBs when\r
629 // looking for an area to borrow.\r
630 //\r
631 AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
632 } else {\r
bd386eaf
JJ
633 //\r
634 // Create memory HOBs\r
635 //\r
bd386eaf 636 AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
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LE
637\r
638 if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
639 UINT32 TsegSize;\r
640\r
23bfb5c0 641 TsegSize = mQ35TsegMbytes * SIZE_1MB;\r
b09c1c6f
LE
642 AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r
643 AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,\r
644 TRUE);\r
645 } else {\r
646 AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
647 }\r
648\r
1fceaddb
LE
649 //\r
650 // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM\r
651 // entries. Otherwise, create a single memory HOB with the flat >=4GB\r
652 // memory size read from the CMOS.\r
653 //\r
654 Status = ScanOrAdd64BitE820Ram (NULL);\r
655 if (EFI_ERROR (Status) && UpperMemorySize != 0) {\r
035ce3b3 656 AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r
cfc80e2e 657 }\r
bd386eaf 658 }\r
49ba9447 659\r
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LE
660 //\r
661 // We'd like to keep the following ranges uncached:\r
662 // - [640 KB, 1 MB)\r
663 // - [LowerMemorySize, 4 GB)\r
664 //\r
665 // Everything else should be WB. Unfortunately, programming the inverse (ie.\r
666 // keeping the default UC, and configuring the complement set of the above as\r
667 // WB) is not reliable in general, because the end of the upper RAM can have\r
668 // practically any alignment, and we may not have enough variable MTRRs to\r
669 // cover it exactly.\r
670 //\r
671 if (IsMtrrSupported ()) {\r
672 MtrrGetAllMtrrs (&MtrrSettings);\r
673\r
674 //\r
675 // MTRRs disabled, fixed MTRRs disabled, default type is uncached\r
676 //\r
677 ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);\r
678 ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);\r
679 ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);\r
680\r
681 //\r
682 // flip default type to writeback\r
683 //\r
684 SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);\r
685 ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);\r
686 MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;\r
687 MtrrSetAllMtrrs (&MtrrSettings);\r
e8e5cd4a 688\r
79d274b8
LE
689 //\r
690 // Set memory range from 640KB to 1MB to uncacheable\r
691 //\r
692 Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,\r
693 BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);\r
694 ASSERT_EFI_ERROR (Status);\r
e8e5cd4a 695\r
79d274b8
LE
696 //\r
697 // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as\r
698 // uncacheable\r
699 //\r
700 Status = MtrrSetMemoryAttribute (LowerMemorySize,\r
701 SIZE_4GB - LowerMemorySize, CacheUncacheable);\r
702 ASSERT_EFI_ERROR (Status);\r
c0e10976 703 }\r
49ba9447 704}\r
705\r
c034906e
JJ
706/**\r
707 Publish system RAM and reserve memory regions\r
708\r
709**/\r
710VOID\r
711InitializeRamRegions (\r
712 VOID\r
713 )\r
714{\r
2818c158
JJ
715 if (!mXen) {\r
716 QemuInitializeRam ();\r
717 } else {\r
2818c158
JJ
718 XenPublishRamRegions ();\r
719 }\r
8e54500f
JJ
720\r
721 if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {\r
722 //\r
723 // This is the memory range that will be used for PEI on S3 resume\r
724 //\r
725 BuildMemoryAllocationHob (\r
45d87081
LE
726 mS3AcpiReservedMemoryBase,\r
727 mS3AcpiReservedMemorySize,\r
8e54500f
JJ
728 EfiACPIMemoryNVS\r
729 );\r
e249f906
LE
730\r
731 //\r
732 // Cover the initial RAM area used as stack and temporary PEI heap.\r
733 //\r
734 // This is reserved as ACPI NVS so it can be used on S3 resume.\r
735 //\r
736 BuildMemoryAllocationHob (\r
737 PcdGet32 (PcdOvmfSecPeiTempRamBase),\r
738 PcdGet32 (PcdOvmfSecPeiTempRamSize),\r
739 EfiACPIMemoryNVS\r
740 );\r
78a38b73 741\r
ad43bc6b
LE
742 //\r
743 // SEC stores its table of GUIDed section handlers here.\r
744 //\r
745 BuildMemoryAllocationHob (\r
746 PcdGet64 (PcdGuidedExtractHandlerTableAddress),\r
747 PcdGet32 (PcdGuidedExtractHandlerTableSize),\r
748 EfiACPIMemoryNVS\r
749 );\r
750\r
78a38b73
LE
751#ifdef MDE_CPU_X64\r
752 //\r
753 // Reserve the initial page tables built by the reset vector code.\r
754 //\r
755 // Since this memory range will be used by the Reset Vector on S3\r
756 // resume, it must be reserved as ACPI NVS.\r
757 //\r
758 BuildMemoryAllocationHob (\r
759 (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),\r
760 (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),\r
761 EfiACPIMemoryNVS\r
762 );\r
763#endif\r
0e8a31f5 764 }\r
6a7cba79 765\r
0e8a31f5 766 if (mBootMode != BOOT_ON_S3_RESUME) {\r
1a7edbbc
LE
767 if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
768 //\r
769 // Reserve the lock box storage area\r
770 //\r
771 // Since this memory range will be used on S3 resume, it must be\r
772 // reserved as ACPI NVS.\r
773 //\r
774 // If S3 is unsupported, then various drivers might still write to the\r
775 // LockBox area. We ought to prevent DXE from serving allocation requests\r
776 // such that they would overlap the LockBox storage.\r
777 //\r
778 ZeroMem (\r
779 (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
780 (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r
781 );\r
782 BuildMemoryAllocationHob (\r
783 (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
784 (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r
785 mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r
786 );\r
787 }\r
b09c1c6f
LE
788\r
789 if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
790 UINT32 TsegSize;\r
791\r
792 //\r
793 // Make sure the TSEG area that we reported as a reserved memory resource\r
794 // cannot be used for reserved memory allocations.\r
795 //\r
23bfb5c0 796 TsegSize = mQ35TsegMbytes * SIZE_1MB;\r
b09c1c6f
LE
797 BuildMemoryAllocationHob (\r
798 GetSystemMemorySizeBelow4gb() - TsegSize,\r
799 TsegSize,\r
800 EfiReservedMemoryType\r
801 );\r
802 }\r
8e54500f 803 }\r
c034906e 804}\r