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1 | /** @file\r |
| 2 | Generic definitions for registers in the Intel Ich devices.\r |
| 3 | \r |
| 4 | These definitions should work for any version of Ich.\r |
| 5 | \r |
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6 | Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>\r |
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7 | This program and the accompanying materials\r |
| 8 | are licensed and made available under the terms and conditions of the BSD License\r |
| 9 | which accompanies this distribution. The full text of the license may be found at\r |
| 10 | http://opensource.org/licenses/bsd-license.php\r |
| 11 | \r |
| 12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 14 | \r |
| 15 | **/\r |
| 16 | \r |
| 17 | #ifndef _GENERIC_ICH_H_\r |
| 18 | #define _GENERIC_ICH_H_\r |
| 19 | \r |
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20 | /** GenericIchDefs Generic ICH Definitions.\r |
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21 | \r |
| 22 | Definitions beginning with "R_" are registers.\r |
| 23 | Definitions beginning with "B_" are bits within registers.\r |
| 24 | Definitions beginning with "V_" are meaningful values of bits within the registers.\r |
| 25 | **/\r |
| 26 | ///@{\r |
| 27 | \r |
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28 | /// IchPciAddressing PCI Bus Address for ICH.\r |
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29 | ///@{\r |
| 30 | #define PCI_BUS_NUMBER_ICH 0x00 ///< ICH is on PCI Bus 0.\r |
| 31 | #define PCI_DEVICE_NUMBER_ICH_LPC 31 ///< ICH is Device 31.\r |
| 32 | #define PCI_FUNCTION_NUMBER_ICH_LPC 0 ///< ICH is Function 0.\r |
| 33 | ///@}\r |
| 34 | \r |
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35 | /// IchAcpiCntr Control for the ICH's ACPI Counter.\r |
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36 | ///@{\r |
| 37 | #define R_ICH_LPC_ACPI_BASE 0x40\r |
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38 | #define B_ICH_LPC_ACPI_BASE_BAR 0x0000FF80\r |
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39 | #define R_ICH_LPC_ACPI_CNT 0x44\r |
| 40 | #define B_ICH_LPC_ACPI_CNT_ACPI_EN 0x80\r |
| 41 | ///@}\r |
| 42 | \r |
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43 | /// IchAcpiTimer The ICH's ACPI Timer.\r |
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44 | ///@{\r |
| 45 | #define R_ACPI_PM1_TMR 0x08\r |
| 46 | #define V_ACPI_TMR_FREQUENCY 3579545\r |
| 47 | #define V_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow.\r |
| 48 | ///@}\r |
| 49 | \r |
| 50 | /// Macro to generate the PCI address of any given ICH Register.\r |
| 51 | #define PCI_ICH_LPC_ADDRESS(Register) \\r |
| 52 | ((UINTN)(PCI_LIB_ADDRESS (PCI_BUS_NUMBER_ICH, PCI_DEVICE_NUMBER_ICH_LPC, PCI_FUNCTION_NUMBER_ICH_LPC, Register)))\r |
| 53 | \r |
| 54 | ///@}\r |
| 55 | #endif // _GENERIC_ICH_H_\r |
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