projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| b303605e MK |
1 | /** @file\r |
| 2 | CPU power management control methods\r | |
| 3 | \r | |
| 4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 5 | \r | |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | DefinitionBlock (\r | |
| 17 | "CPUPM.aml",\r | |
| 18 | "SSDT",\r | |
| 19 | 0x01,\r | |
| 20 | "SsgPmm",\r | |
| 21 | "CpuPm",\r | |
| 22 | 0x0010\r | |
| 23 | )\r | |
| 24 | {\r | |
| 25 | External(\_PR.CPU0, DeviceObj)\r | |
| 26 | External(CFGD, FieldUnitObj)\r | |
| 27 | \r | |
| 28 | Scope(\)\r | |
| 29 | {\r | |
| 30 | // Config DWord, modified during POST\r | |
| 31 | // Bit definitions are the same as PPMFlags:\r | |
| 32 | // CFGD[0] = PPM_GV3 = GV3\r | |
| 33 | // CFGD[1] = PPM_TURBO = Turbo Mode\r | |
| 34 | // CFGD[2] = PPM_SUPER_LFM = N/2 Ratio\r | |
| 35 | // CFGD[4] = PPM_C1 = C1 Capable, Enabled\r | |
| 36 | // CFGD[5] = PPM_C2 = C2 Capable, Enabled\r | |
| 37 | // CFGD[6] = PPM_C3 = C3 Capable, Enabled\r | |
| 38 | // CFGD[7] = PPM_C4 = C4 Capable, Enabled\r | |
| 39 | // CFGD[8] = PPM_C5 = C5/Deep C4 Capable, Enabled\r | |
| 40 | // CFGD[9] = PPM_C6 = C6 Capable, Enabled\r | |
| 41 | // CFGD[10] = PPM_C1E = C1E Enabled\r | |
| 42 | // CFGD[11] = PPM_C2E = C2E Enabled\r | |
| 43 | // CFGD[12] = PPM_C3E = C3E Enabled\r | |
| 44 | // CFGD[13] = PPM_C4E = C4E Enabled\r | |
| 45 | // CFGD[14] = PPM_HARD_C4E = Hard C4E Capable, Enabled\r | |
| 46 | // CFGD[16] = PPM_TM1 = Thermal Monitor 1\r | |
| 47 | // CFGD[17] = PPM_TM2 = Thermal Monitor 2\r | |
| 48 | // CFGD[19] = PPM_PHOT = Bi-directional ProcHot\r | |
| 49 | // CFGD[21] = PPM_MWAIT_EXT = MWAIT extensions supported\r | |
| 50 | // CFGD[24] = PPM_CMP = CMP supported, Enabled\r | |
| 51 | // CFGD[28] = PPM_TSTATE = CPU T states supported\r | |
| 52 | //\r | |
| 53 | // Name(CFGD, 0x80000000)\r | |
| 54 | // External Defined in GNVS\r | |
| 55 | \r | |
| 56 | Name(PDC0,0x80000000) // CPU0 _PDC Flags.\r | |
| 57 | \r | |
| 58 | // We load it in AcpiPlatform\r | |
| 59 | //Name(SSDT,Package()\r | |
| 60 | //{\r | |
| 61 | // "CPU0IST ", 0x80000000, 0x80000000,\r | |
| 62 | // "CPU1IST ", 0x80000000, 0x80000000,\r | |
| 63 | // "CPU0CST ", 0x80000000, 0x80000000,\r | |
| 64 | // "CPU1CST ", 0x80000000, 0x80000000,\r | |
| 65 | //})\r | |
| 66 | }\r | |
| 67 | Scope(\_PR.CPU0)\r | |
| 68 | {\r | |
| 69 | Method(_PDC, 1)\r | |
| 70 | {\r | |
| 71 | //\r | |
| 72 | // Store result of PDC.\r | |
| 73 | //\r | |
| 74 | CreateDWordField(Arg0,8,CAP0) // Point to 3rd DWORD.\r | |
| 75 | Store(CAP0,PDC0) // Store It in PDC0.\r | |
| 76 | }\r | |
| 77 | }\r | |
| 78 | \r | |
| 79 | }\r |