[mirror_edk2.git] / QuarkPlatformPkg / Include / PlatformBoards.h

/** @file\r
Board config definitions for each of the boards supported by this platform\r
package.\r
\r
Copyright (c) 2013 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
**/\r
#include "Platform.h"\r
\r
#ifndef __PLATFORM_BOARDS_H__\r
#define __PLATFORM_BOARDS_H__\r
\r
//\r
// Constant definition\r
//\r
\r
//\r
// Default resume well TPM reset.\r
//\r
#define PLATFORM_RESUMEWELL_TPM_RST_GPIO                5\r
\r
//\r
// Basic Configs for GPIO table definitions.\r
//\r
#define NULL_LEGACY_GPIO_INITIALIZER                    {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}\r
#define ALL_INPUT_LEGACY_GPIO_INITIALIZER               {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}\r
#define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER         ALL_INPUT_LEGACY_GPIO_INITIALIZER\r
#define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER        {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00}\r
#define KIPS_BAY_LEGACY_GPIO_INITIALIZER                {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00}\r
#define CROSS_HILL_LEGACY_GPIO_INITIALIZER              {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}\r
#define CLANTON_HILL_LEGACY_GPIO_INITIALIZER            {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}\r
#define GALILEO_LEGACY_GPIO_INITIALIZER                 {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}\r
#define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER            {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}\r
\r
#define NULL_GPIO_CONTROLLER_INITIALIZER                {0,0,0,0,0,0,0,0}\r
#define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER           NULL_GPIO_CONTROLLER_INITIALIZER\r
#define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER     NULL_GPIO_CONTROLLER_INITIALIZER\r
#define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER    NULL_GPIO_CONTROLLER_INITIALIZER\r
#define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER            {0x05,0x05,0,0,0,0,0,0}\r
#define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER          {0x0D,0x2D,0,0,0,0,0,0}\r
#define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER        {0x01,0x39,0,0,0,0,0,0}\r
#define GALILEO_GPIO_CONTROLLER_INITIALIZER             {0x05,0x15,0,0,0,0,0,0}\r
#define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER        {0x05,0x05,0,0,0,0,0,0}\r
\r
//\r
// Legacy Gpio to be used to assert / deassert PCI express PERST# signal\r
// on Galileo Gen 2 platform.\r
//\r
#define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO       0\r
\r
//\r
// Io expander slave address.\r
//\r
\r
//\r
// On Galileo value of Jumper J2 determines slave address of io expander.\r
//\r
#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO     5\r
#define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR              0x20\r
#define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR              0x21\r
\r
//\r
// Three IO Expmanders at fixed addresses on Galileo Gen2.\r
//\r
#define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR             0x25\r
#define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR             0x26\r
#define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR             0x27\r
\r
//\r
// Led GPIOs for flash update / recovery.\r
//\r
#define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO        1\r
#define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO   5\r
\r
//\r
// Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.\r
//\r
typedef struct {\r
  UINT32  CoreWellEnable;               ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.\r
  UINT32  CoreWellIoSelect;             ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.\r
  UINT32  CoreWellLvlForInputOrOutput;  ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.\r
  UINT32  CoreWellTriggerPositiveEdge;  ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.\r
  UINT32  CoreWellTriggerNegativeEdge;  ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.\r
  UINT32  CoreWellGPEEnable;            ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.\r
  UINT32  CoreWellSMIEnable;            ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.\r
  UINT32  CoreWellTriggerStatus;        ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.\r
  UINT32  CoreWellNMIEnable;            ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.\r
  UINT32  ResumeWellEnable;             ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.\r
  UINT32  ResumeWellIoSelect;           ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.\r
  UINT32  ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.\r
  UINT32  ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.\r
  UINT32  ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.\r
  UINT32  ResumeWellGPEEnable;          ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.\r
  UINT32  ResumeWellSMIEnable;          ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.\r
  UINT32  ResumeWellTriggerStatus;      ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.\r
  UINT32  ResumeWellNMIEnable;          ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.\r
} BOARD_LEGACY_GPIO_CONFIG;\r
\r
//\r
// GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION.\r
//\r
typedef struct {\r
  UINT32  PortADR;                      ///< Value for IOH REG GPIO_SWPORTA_DR.\r
  UINT32  PortADir;                     ///< Value for IOH REG GPIO_SWPORTA_DDR.\r
  UINT32  IntEn;                        ///< Value for IOH REG GPIO_INTEN.\r
  UINT32  IntMask;                      ///< Value for IOH REG GPIO_INTMASK.\r
  UINT32  IntType;                      ///< Value for IOH REG GPIO_INTTYPE_LEVEL.\r
  UINT32  IntPolarity;                  ///< Value for IOH REG GPIO_INT_POLARITY.\r
  UINT32  Debounce;                     ///< Value for IOH REG GPIO_DEBOUNCE.\r
  UINT32  LsSync;                       ///< Value for IOH REG GPIO_LS_SYNC.\r
} BOARD_GPIO_CONTROLLER_CONFIG;\r
\r
///\r
/// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported\r
/// by this platform package.\r
/// Table indexed with EFI_PLATFORM_TYPE enum value.\r
///\r
#define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \\r
  /* EFI_PLATFORM_TYPE - TypeUnknown*/\\r
  NULL_LEGACY_GPIO_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r
  QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r
  CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - KipsBay*/\\r
  KIPS_BAY_LEGACY_GPIO_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - CrossHill*/\\r
  CROSS_HILL_LEGACY_GPIO_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - ClantonHill*/\\r
  CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - Galileo*/\\r
  GALILEO_LEGACY_GPIO_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\\r
  NULL_LEGACY_GPIO_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - GalileoGen2*/\\r
  GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\\r
\r
///\r
/// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board\r
/// supported by this platform package.\r
/// Table indexed with EFI_PLATFORM_TYPE enum value.\r
///\r
#define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \\r
  /* EFI_PLATFORM_TYPE - TypeUnknown*/\\r
  NULL_GPIO_CONTROLLER_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r
  QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r
  CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - KipsBay*/\\r
  KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - CrossHill*/\\r
  CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - ClantonHill*/\\r
  CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - Galileo*/\\r
  GALILEO_GPIO_CONTROLLER_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\\r
  NULL_GPIO_CONTROLLER_INITIALIZER,\\r
  /* EFI_PLATFORM_TYPE - GalileoGen2*/\\r
  GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\\r
\r
#endif\r
Commit	Line	Data
b303605e MK	1	/** @file\r
	2	Board config definitions for each of the boards supported by this platform\r
	3	package.\r
	4	\r
	5	Copyright (c) 2013 Intel Corporation.\r
	6	\r
	7	This program and the accompanying materials\r
	8	are licensed and made available under the terms and conditions of the BSD License\r
	9	which accompanies this distribution. The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	\r
	16	**/\r
	17	#include "Platform.h"\r
	18	\r
	19	#ifndef __PLATFORM_BOARDS_H__\r
	20	#define __PLATFORM_BOARDS_H__\r
	21	\r
	22	//\r
	23	// Constant definition\r
	24	//\r
	25	\r
	26	//\r
	27	// Default resume well TPM reset.\r
	28	//\r
	29	#define PLATFORM_RESUMEWELL_TPM_RST_GPIO 5\r
	30	\r
	31	//\r
	32	// Basic Configs for GPIO table definitions.\r
	33	//\r
	34	#define NULL_LEGACY_GPIO_INITIALIZER {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}\r
	35	#define ALL_INPUT_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}\r
	36	#define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER ALL_INPUT_LEGACY_GPIO_INITIALIZER\r
	37	#define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00}\r
	38	#define KIPS_BAY_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00}\r
	39	#define CROSS_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}\r
	40	#define CLANTON_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}\r
	41	#define GALILEO_LEGACY_GPIO_INITIALIZER {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}\r
	42	#define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}\r
	43	\r
	44	#define NULL_GPIO_CONTROLLER_INITIALIZER {0,0,0,0,0,0,0,0}\r
	45	#define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r
	46	#define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r
	47	#define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r
	48	#define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}\r
	49	#define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER {0x0D,0x2D,0,0,0,0,0,0}\r
	50	#define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER {0x01,0x39,0,0,0,0,0,0}\r
	51	#define GALILEO_GPIO_CONTROLLER_INITIALIZER {0x05,0x15,0,0,0,0,0,0}\r
	52	#define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}\r
	53	\r
	54	//\r
	55	// Legacy Gpio to be used to assert / deassert PCI express PERST# signal\r
	56	// on Galileo Gen 2 platform.\r
	57	//\r
	58	#define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO 0\r
	59	\r
	60	//\r
	61	// Io expander slave address.\r
	62	//\r
	63	\r
	64	//\r
65	// On Galileo value of Jumper J2 determines slave address of io expander.\r
66	//\r
67	#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5\r
68	#define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR 0x20\r
69	#define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR 0x21\r
70	\r
71	//\r
72	// Three IO Expmanders at fixed addresses on Galileo Gen2.\r
73	//\r
74	#define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25\r
75	#define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26\r
76	#define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27\r
77	\r
78	//\r
79	// Led GPIOs for flash update / recovery.\r
80	//\r
81	#define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO 1\r
82	#define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5\r
83	\r
84	//\r
85	// Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.\r
86	//\r
87	typedef struct {\r
88	UINT32 CoreWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.\r
89	UINT32 CoreWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.\r
90	UINT32 CoreWellLvlForInputOrOutput; ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.\r
91	UINT32 CoreWellTriggerPositiveEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.\r
92	UINT32 CoreWellTriggerNegativeEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.\r
93	UINT32 CoreWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.\r
94	UINT32 CoreWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.\r
95	UINT32 CoreWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.\r
96	UINT32 CoreWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.\r
97	UINT32 ResumeWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.\r
98	UINT32 ResumeWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.\r
99	UINT32 ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.\r
100	UINT32 ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.\r
101	UINT32 ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.\r
102	UINT32 ResumeWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.\r
103	UINT32 ResumeWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.\r
104	UINT32 ResumeWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.\r
105	UINT32 ResumeWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.\r
106	} BOARD_LEGACY_GPIO_CONFIG;\r
107	\r
108	//\r
109	// GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION.\r
110	//\r
111	typedef struct {\r
112	UINT32 PortADR; ///< Value for IOH REG GPIO_SWPORTA_DR.\r
113	UINT32 PortADir; ///< Value for IOH REG GPIO_SWPORTA_DDR.\r
114	UINT32 IntEn; ///< Value for IOH REG GPIO_INTEN.\r
115	UINT32 IntMask; ///< Value for IOH REG GPIO_INTMASK.\r
116	UINT32 IntType; ///< Value for IOH REG GPIO_INTTYPE_LEVEL.\r
117	UINT32 IntPolarity; ///< Value for IOH REG GPIO_INT_POLARITY.\r
118	UINT32 Debounce; ///< Value for IOH REG GPIO_DEBOUNCE.\r
119	UINT32 LsSync; ///< Value for IOH REG GPIO_LS_SYNC.\r
120	} BOARD_GPIO_CONTROLLER_CONFIG;\r
121	\r
122	///\r
123	/// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported\r
124	/// by this platform package.\r
125	/// Table indexed with EFI_PLATFORM_TYPE enum value.\r
126	///\r
127	#define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \\r
128	/* EFI_PLATFORM_TYPE - TypeUnknown*/\\r
129	NULL_LEGACY_GPIO_INITIALIZER,\\r
130	/* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r
131	QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\\r
132	/* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r
133	CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\\r
134	/* EFI_PLATFORM_TYPE - KipsBay*/\\r
135	KIPS_BAY_LEGACY_GPIO_INITIALIZER,\\r
136	/* EFI_PLATFORM_TYPE - CrossHill*/\\r
137	CROSS_HILL_LEGACY_GPIO_INITIALIZER,\\r
138	/* EFI_PLATFORM_TYPE - ClantonHill*/\\r
139	CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\\r
140	/* EFI_PLATFORM_TYPE - Galileo*/\\r
141	GALILEO_LEGACY_GPIO_INITIALIZER,\\r
142	/* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\\r
143	NULL_LEGACY_GPIO_INITIALIZER,\\r
144	/* EFI_PLATFORM_TYPE - GalileoGen2*/\\r
145	GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\\r
146	\r
147	///\r
148	/// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board\r
149	/// supported by this platform package.\r
150	/// Table indexed with EFI_PLATFORM_TYPE enum value.\r
151	///\r
152	#define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \\r
153	/* EFI_PLATFORM_TYPE - TypeUnknown*/\\r
154	NULL_GPIO_CONTROLLER_INITIALIZER,\\r
155	/* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r
156	QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\\r
157	/* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r
158	CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\\r
159	/* EFI_PLATFORM_TYPE - KipsBay*/\\r
160	KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\\r
161	/* EFI_PLATFORM_TYPE - CrossHill*/\\r
162	CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\\r
163	/* EFI_PLATFORM_TYPE - ClantonHill*/\\r
164	CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\\r
165	/* EFI_PLATFORM_TYPE - Galileo*/\\r
166	GALILEO_GPIO_CONTROLLER_INITIALIZER,\\r
167	/* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\\r
168	NULL_GPIO_CONTROLLER_INITIALIZER,\\r
169	/* EFI_PLATFORM_TYPE - GalileoGen2*/\\r
170	GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\\r
171	\r
172	#endif\r