[mirror_edk2.git] / SecurityPkg / Tcg / Tcg2Smm / Tpm.asl

/** @file\r
  The TPM2 definition block in ACPI table for TCG2 physical presence  \r
  and MemoryClear.\r
\r
Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>\r
(c)Copyright 2016 HP Development Company, L.P.<BR>\r
Copyright (c) 2017, Microsoft Corporation.  All rights reserved. <BR>\r
This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution.  The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
DefinitionBlock (\r
  "Tpm.aml",\r
  "SSDT",\r
  2,\r
  "INTEL ",\r
  "Tpm2Tabl",\r
  0x1000\r
  )\r
{\r
  Scope (\_SB)\r
  {\r
    Device (TPM)\r
    {\r
      //\r
      // TCG2\r
      //\r
\r
      //\r
      //  TAG for patching TPM2.0 _HID\r
      //\r
      Name (_HID, "NNNN0000")\r
\r
      Name (_CID, "MSFT0101")\r
\r
      //\r
      // Readable name of this device, don't know if this way is correct yet\r
      //\r
      Name (_STR, Unicode ("TPM 2.0 Device"))\r
\r
      //\r
      // Operational region for Smi port access\r
      //\r
      OperationRegion (SMIP, SystemIO, 0xB2, 1)\r
      Field (SMIP, ByteAcc, NoLock, Preserve)\r
      { \r
          IOB2, 8\r
      }\r
\r
      //\r
      // Operational region for TPM access\r
      //\r
      OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)\r
      Field (TPMR, AnyAcc, NoLock, Preserve)\r
      {\r
        ACC0, 8,  // TPM_ACCESS_0\r
        Offset(0x8),\r
        INTE, 32, // TPM_INT_ENABLE_0\r
        INTV, 8,  // TPM_INT_VECTOR_0\r
        Offset(0x10),\r
        INTS, 32, // TPM_INT_STATUS_0\r
        INTF, 32, // TPM_INTF_CAPABILITY_0\r
        STS0, 32, // TPM_STS_0\r
        Offset(0x24),\r
        FIFO, 32, // TPM_DATA_FIFO_0\r
        Offset(0x30),\r
        TID0, 32, // TPM_INTERFACE_ID_0\r
                  // ignore the rest\r
      }\r
\r
      //\r
      // Operational region for TPM support, TPM Physical Presence and TPM Memory Clear\r
      // Region Offset 0xFFFF0000 and Length 0xF0 will be fixed in C code.\r
      //\r
      OperationRegion (TNVS, SystemMemory, 0xFFFF0000, 0xF0)\r
      Field (TNVS, AnyAcc, NoLock, Preserve)\r
      {\r
        PPIN,   8,  //   Software SMI for Physical Presence Interface\r
        PPIP,   32, //   Used for save physical presence paramter\r
        PPRP,   32, //   Physical Presence request operation response\r
        PPRQ,   32, //   Physical Presence request operation\r
        PPRM,   32, //   Physical Presence request operation parameter\r
        LPPR,   32, //   Last Physical Presence request operation\r
        FRET,   32, //   Physical Presence function return code\r
        MCIN,   8,  //   Software SMI for Memory Clear Interface\r
        MCIP,   32, //   Used for save the Mor paramter\r
        MORD,   32, //   Memory Overwrite Request Data\r
        MRET,   32, //   Memory Overwrite function return code\r
        UCRQ,   32  //   Phyical Presence request operation to Get User Confirmation Status \r
      }\r
\r
      Name(RESO, ResourceTemplate () {\r
        Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REGS)\r
        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) {12}\r
      })\r
\r
      //\r
      // Return the resource consumed by TPM device.\r
      //\r
      Method(_CRS,0,Serialized)\r
      {\r
        Return(RESO)\r
      }\r
\r
      //\r
      // Set resources consumed by the TPM device. This is used to\r
      // assign an interrupt number to the device. The input byte stream\r
      // has to be the same as returned by _CRS (according to ACPI spec).\r
      //\r
      Method(_SRS,1,Serialized)\r
      {\r
        //\r
        // Update resource descriptor\r
        // Use the field name to identify the offsets in the argument\r
        // buffer and RESO buffer.\r
        //\r
        CreateDWordField(Arg0, ^IRQ._INT, IRQ0)\r
        CreateDWordField(RESO, ^IRQ._INT, LIRQ)\r
        Store(IRQ0, LIRQ)\r
\r
        CreateBitField(Arg0, ^IRQ._HE, ITRG)\r
        CreateBitField(RESO, ^IRQ._HE, LTRG)\r
        Store(ITRG, LTRG)\r
\r
        CreateBitField(Arg0, ^IRQ._LL, ILVL)\r
        CreateBitField(RESO, ^IRQ._LL, LLVL)\r
        Store(ILVL, LLVL)\r
\r
        //\r
        // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest\r
        // nibble.\r
        // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active\r
        // 1111 - FIFO interface as defined in TIS1.3 is active\r
        //\r
        If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {\r
          //\r
          // If FIFO interface, interrupt vector register is\r
          // available. TCG PTP specification allows only\r
          // values 1..15 in this field. For other interrupts\r
          // the field should stay 0.\r
          //\r
          If (LLess (IRQ0, 16)) {\r
            Store (And(IRQ0, 0xF), INTV)\r
          }\r
          //\r
          // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4\r
          // contains settings for interrupt polarity.\r
          // The other bits of the byte enable individual interrupts.\r
          // They should be all be zero, but to avoid changing the\r
          // configuration, the other bits are be preserved.\r
          // 00 - high level\r
          // 01 - low level\r
          // 10 - rising edge\r
          // 11 - falling edge\r
          //\r
          // ACPI spec definitions:\r
          // _HE: '1' is Edge, '0' is Level\r
          // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)\r
          //\r
          If (LEqual (ITRG, 1)) {\r
            Or(INTE, 0x00000010, INTE)\r
          } Else {\r
            And(INTE, 0xFFFFFFEF, INTE)\r
          }\r
          if (LEqual (ILVL, 0)) {\r
            Or(INTE, 0x00000008, INTE)\r
          } Else {\r
            And(INTE, 0xFFFFFFF7, INTE)\r
          }\r
        }\r
      }\r
\r
      //\r
      // Possible resource settings.\r
      // The format of the data has to follow the same format as\r
      // _CRS (according to ACPI spec).\r
      //\r
      Name (_PRS, ResourceTemplate() {\r
        Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , SIRQ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}\r
      })\r
\r
      Method (PTS, 1, Serialized)\r
      {  \r
        //\r
        // Detect Sx state for MOR, only S4, S5 need to handle\r
        //\r
        If (LAnd (LLess (Arg0, 6), LGreater (Arg0, 3)))\r
        {   \r
          //\r
          // Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect.\r
          //\r
          If (LNot (And (MORD, 0x10)))\r
          {\r
            //\r
            // Triggle the SMI through ACPI _PTS method.\r
            //\r
            Store (0x02, MCIP)\r
              \r
            //\r
            // Triggle the SMI interrupt\r
            //\r
            Store (MCIN, IOB2)\r
          }\r
        }\r
        Return (0)\r
      }   \r
\r
      Method (_STA, 0)\r
      {\r
        if (LEqual (ACC0, 0xff))\r
        {\r
            Return (0)\r
        }\r
        Return (0x0f)\r
      }\r
\r
      //\r
      // TCG Hardware Information\r
      //\r
      Method (HINF, 3, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
      {\r
        //\r
        // Switch by function index\r
        //\r
        Switch (ToInteger(Arg1))\r
        {\r
          Case (0)\r
          {\r
            //\r
            // Standard query\r
            //\r
            Return (Buffer () {0x03})\r
          }\r
          Case (1)\r
          {\r
            //\r
            // Return failure if no TPM present\r
            //\r
            Name(TPMV, Package () {0x01, Package () {0x2, 0x0}})\r
            if (LEqual (_STA (), 0x00))\r
            {\r
              Return (Package () {0x00})\r
            }\r
\r
            //\r
            // Return TPM version\r
            //\r
            Return (TPMV)\r
          }\r
          Default {BreakPoint}\r
        }\r
        Return (Buffer () {0})\r
      }\r
\r
      Name(TPM2, Package (0x02){\r
        Zero, \r
        Zero\r
      })\r
\r
      Name(TPM3, Package (0x03){\r
        Zero, \r
        Zero,\r
        Zero\r
      })\r
\r
      //\r
      // TCG Physical Presence Interface\r
      //\r
      Method (TPPI, 3, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
      {        \r
        //\r
        // Switch by function index\r
        //\r
        Switch (ToInteger(Arg1))\r
        {\r
          Case (0)\r
          {\r
            //\r
            // Standard query, supports function 1-8\r
            //\r
            Return (Buffer () {0xFF, 0x01})\r
          }\r
          Case (1)\r
          {\r
            //\r
            // a) Get Physical Presence Interface Version\r
            //\r
            Return ("$PV")\r
          }\r
          Case (2)\r
          {\r
            //\r
            // b) Submit TPM Operation Request to Pre-OS Environment\r
            //\r
                  \r
            Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
            Store (0, PPRM)\r
            Store (0x02, PPIP)\r
              \r
            //\r
            // Triggle the SMI interrupt\r
            //\r
            Store (PPIN, IOB2)\r
            Return (FRET)\r
\r
\r
          }\r
          Case (3)\r
          {\r
            //\r
            // c) Get Pending TPM Operation Requested By the OS\r
            //\r
                  \r
            Store (PPRQ, Index (TPM2, 0x01))\r
            Return (TPM2)\r
          }\r
          Case (4)\r
          {\r
            //\r
            // d) Get Platform-Specific Action to Transition to Pre-OS Environment\r
            //\r
            Return (2)\r
          }\r
          Case (5)\r
          {\r
            //\r
            // e) Return TPM Operation Response to OS Environment\r
            //\r
            Store (0x05, PPIP)\r
                  \r
            //\r
            // Triggle the SMI interrupt\r
            //\r
            Store (PPIN, IOB2)\r
                  \r
            Store (LPPR, Index (TPM3, 0x01))\r
            Store (PPRP, Index (TPM3, 0x02))\r
\r
            Return (TPM3)\r
          }\r
          Case (6)\r
          {\r
\r
            //\r
            // f) Submit preferred user language (Not implemented)\r
            //\r
\r
            Return (3)\r
\r
          }\r
          Case (7)\r
          {\r
            //\r
            // g) Submit TPM Operation Request to Pre-OS Environment 2\r
            //\r
            Store (7, PPIP)\r
            Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
            Store (0, PPRM)\r
            If (LEqual (PPRQ, 23)) {\r
              Store (DerefOf (Index (Arg2, 0x01)), PPRM)\r
            }\r
                \r
            //\r
            // Triggle the SMI interrupt \r
            //\r
            Store (PPIN, IOB2)  \r
            Return (FRET)\r
          }\r
          Case (8)\r
          {\r
            //\r
            // e) Get User Confirmation Status for Operation\r
            //\r
            Store (8, PPIP)\r
            Store (DerefOf (Index (Arg2, 0x00)), UCRQ)\r
                  \r
            //\r
            // Triggle the SMI interrupt\r
            //\r
            Store (PPIN, IOB2)\r
                  \r
            Return (FRET)\r
          }\r
\r
          Default {BreakPoint}\r
        }\r
        Return (1)\r
      }\r
\r
      Method (TMCI, 3, Serialized, 0, IntObj, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
      {\r
        //\r
        // Switch by function index\r
        //\r
        Switch (ToInteger (Arg1))\r
        {\r
          Case (0)\r
          {\r
            //\r
            // Standard query, supports function 1-1\r
            //\r
            Return (Buffer () {0x03})\r
          }\r
          Case (1)\r
          {\r
            //\r
            // Save the Operation Value of the Request to MORD (reserved memory)\r
            //\r
            Store (DerefOf (Index (Arg2, 0x00)), MORD)\r
                  \r
            //\r
            // Triggle the SMI through ACPI _DSM method.\r
            //\r
            Store (0x01, MCIP)\r
                  \r
            //\r
            // Triggle the SMI interrupt\r
            //\r
            Store (MCIN, IOB2)\r
            Return (MRET)\r
          }\r
          Default {BreakPoint}\r
        }\r
        Return (1)        \r
      }\r
\r
      Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})\r
      {\r
\r
        //\r
        // TCG Hardware Information\r
        //\r
        If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))\r
        {\r
          Return (HINF (Arg1, Arg2, Arg3))\r
        }\r
\r
        //\r
        // TCG Physical Presence Interface\r
        //\r
        If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))\r
        {\r
          Return (TPPI (Arg1, Arg2, Arg3))\r
        }\r
\r
        //\r
        // TCG Memory Clear Interface\r
        //\r
        If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))\r
        {\r
          Return (TMCI (Arg1, Arg2, Arg3))\r
        }\r
\r
        Return (Buffer () {0})\r
      }\r
    }\r
  }\r
}\r
Commit	Line	Data
1abfa4ce JY	1	/** @file\r
	2	The TPM2 definition block in ACPI table for TCG2 physical presence \r
	3	and MemoryClear.\r
	4	\r
9a9fa14e	5	Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>\r
447f73db	6	(c)Copyright 2016 HP Development Company, L.P.<BR>\r
af9743ef	7	Copyright (c) 2017, Microsoft Corporation. All rights reserved. <BR>\r
1abfa4ce JY	8	This program and the accompanying materials \r
	9	are licensed and made available under the terms and conditions of the BSD License \r
	10	which accompanies this distribution. The full text of the license may be found at \r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	\r
	16	**/\r
	17	\r
	18	DefinitionBlock (\r
	19	"Tpm.aml",\r
	20	"SSDT",\r
	21	2,\r
	22	"INTEL ",\r
	23	"Tpm2Tabl",\r
	24	0x1000\r
	25	)\r
	26	{\r
	27	Scope (\_SB)\r
	28	{\r
	29	Device (TPM)\r
	30	{\r
	31	//\r
	32	// TCG2\r
	33	//\r
9a9fa14e	34	\r
73126ac2	35	//\r
9a9fa14e	36	// TAG for patching TPM2.0 _HID\r
73126ac2	37	//\r
9a9fa14e	38	Name (_HID, "NNNN0000")\r
73126ac2 ZC	39	\r
	40	Name (_CID, "MSFT0101")\r
	41	\r
1abfa4ce JY	42	//\r
	43	// Readable name of this device, don't know if this way is correct yet\r
	44	//\r
	45	Name (_STR, Unicode ("TPM 2.0 Device"))\r
	46	\r
1abfa4ce JY	47	//\r
	48	// Operational region for Smi port access\r
	49	//\r
	50	OperationRegion (SMIP, SystemIO, 0xB2, 1)\r
	51	Field (SMIP, ByteAcc, NoLock, Preserve)\r
	52	{ \r
	53	IOB2, 8\r
	54	}\r
	55	\r
	56	//\r
	57	// Operational region for TPM access\r
	58	//\r
	59	OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)\r
	60	Field (TPMR, AnyAcc, NoLock, Preserve)\r
	61	{\r
edf7647b ZC	62	ACC0, 8, // TPM_ACCESS_0\r
	63	Offset(0x8),\r
	64	INTE, 32, // TPM_INT_ENABLE_0\r
	65	INTV, 8, // TPM_INT_VECTOR_0\r
	66	Offset(0x10),\r
	67	INTS, 32, // TPM_INT_STATUS_0\r
	68	INTF, 32, // TPM_INTF_CAPABILITY_0\r
	69	STS0, 32, // TPM_STS_0\r
	70	Offset(0x24),\r
	71	FIFO, 32, // TPM_DATA_FIFO_0\r
	72	Offset(0x30),\r
	73	TID0, 32, // TPM_INTERFACE_ID_0\r
	74	// ignore the rest\r
1abfa4ce JY	75	}\r
	76	\r
	77	//\r
	78	// Operational region for TPM support, TPM Physical Presence and TPM Memory Clear\r
	79	// Region Offset 0xFFFF0000 and Length 0xF0 will be fixed in C code.\r
	80	//\r
	81	OperationRegion (TNVS, SystemMemory, 0xFFFF0000, 0xF0)\r
	82	Field (TNVS, AnyAcc, NoLock, Preserve)\r
	83	{\r
	84	PPIN, 8, // Software SMI for Physical Presence Interface\r
	85	PPIP, 32, // Used for save physical presence paramter\r
	86	PPRP, 32, // Physical Presence request operation response\r
	87	PPRQ, 32, // Physical Presence request operation\r
	88	PPRM, 32, // Physical Presence request operation parameter\r
	89	LPPR, 32, // Last Physical Presence request operation\r
	90	FRET, 32, // Physical Presence function return code\r
	91	MCIN, 8, // Software SMI for Memory Clear Interface\r
	92	MCIP, 32, // Used for save the Mor paramter\r
	93	MORD, 32, // Memory Overwrite Request Data\r
053f31e3 ZC	94	MRET, 32, // Memory Overwrite function return code\r
053f31e3 ZC	95	UCRQ, 32 // Phyical Presence request operation to Get User Confirmation Status \r
1abfa4ce JY	96	}\r
1abfa4ce JY	97	\r
edf7647b ZC	98	Name(RESO, ResourceTemplate () {\r
	99	Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REGS)\r
	100	Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) {12}\r
	101	})\r
	102	\r
	103	//\r
	104	// Return the resource consumed by TPM device.\r
	105	//\r
	106	Method(_CRS,0,Serialized)\r
	107	{\r
	108	Return(RESO)\r
	109	}\r
	110	\r
	111	//\r
	112	// Set resources consumed by the TPM device. This is used to\r
	113	// assign an interrupt number to the device. The input byte stream\r
	114	// has to be the same as returned by _CRS (according to ACPI spec).\r
	115	//\r
	116	Method(_SRS,1,Serialized)\r
	117	{\r
	118	//\r
	119	// Update resource descriptor\r
	120	// Use the field name to identify the offsets in the argument\r
	121	// buffer and RESO buffer.\r
	122	//\r
	123	CreateDWordField(Arg0, ^IRQ._INT, IRQ0)\r
	124	CreateDWordField(RESO, ^IRQ._INT, LIRQ)\r
	125	Store(IRQ0, LIRQ)\r
	126	\r
	127	CreateBitField(Arg0, ^IRQ._HE, ITRG)\r
	128	CreateBitField(RESO, ^IRQ._HE, LTRG)\r
	129	Store(ITRG, LTRG)\r
	130	\r
	131	CreateBitField(Arg0, ^IRQ._LL, ILVL)\r
	132	CreateBitField(RESO, ^IRQ._LL, LLVL)\r
	133	Store(ILVL, LLVL)\r
	134	\r
	135	//\r
	136	// Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest\r
	137	// nibble.\r
	138	// 0000 - FIFO interface as defined in PTP for TPM 2.0 is active\r
	139	// 1111 - FIFO interface as defined in TIS1.3 is active\r
	140	//\r
	141	If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {\r
	142	//\r
	143	// If FIFO interface, interrupt vector register is\r
	144	// available. TCG PTP specification allows only\r
	145	// values 1..15 in this field. For other interrupts\r
	146	// the field should stay 0.\r
	147	//\r
	148	If (LLess (IRQ0, 16)) {\r
	149	Store (And(IRQ0, 0xF), INTV)\r
	150	}\r
	151	//\r
	152	// Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4\r
	153	// contains settings for interrupt polarity.\r
	154	// The other bits of the byte enable individual interrupts.\r
	155	// They should be all be zero, but to avoid changing the\r
	156	// configuration, the other bits are be preserved.\r
	157	// 00 - high level\r
	158	// 01 - low level\r
	159	// 10 - rising edge\r
	160	// 11 - falling edge\r
	161	//\r
162	// ACPI spec definitions:\r
163	// _HE: '1' is Edge, '0' is Level\r
164	// _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)\r
165	//\r
166	If (LEqual (ITRG, 1)) {\r
167	Or(INTE, 0x00000010, INTE)\r
168	} Else {\r
169	And(INTE, 0xFFFFFFEF, INTE)\r
170	}\r
171	if (LEqual (ILVL, 0)) {\r
172	Or(INTE, 0x00000008, INTE)\r
173	} Else {\r
174	And(INTE, 0xFFFFFFF7, INTE)\r
175	}\r
176	}\r
177	}\r
178	\r
179	//\r
180	// Possible resource settings.\r
181	// The format of the data has to follow the same format as\r
182	// _CRS (according to ACPI spec).\r
183	//\r
184	Name (_PRS, ResourceTemplate() {\r
185	Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
186	Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , SIRQ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}\r
187	})\r
188	\r
1abfa4ce JY	189	Method (PTS, 1, Serialized)\r
	190	{ \r
	191	//\r
	192	// Detect Sx state for MOR, only S4, S5 need to handle\r
	193	//\r
	194	If (LAnd (LLess (Arg0, 6), LGreater (Arg0, 3)))\r
	195	{ \r
	196	//\r
	197	// Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect.\r
	198	//\r
	199	If (LNot (And (MORD, 0x10)))\r
	200	{\r
	201	//\r
	202	// Triggle the SMI through ACPI _PTS method.\r
	203	//\r
	204	Store (0x02, MCIP)\r
	205	\r
	206	//\r
	207	// Triggle the SMI interrupt\r
	208	//\r
	209	Store (MCIN, IOB2)\r
	210	}\r
	211	}\r
	212	Return (0)\r
	213	} \r
	214	\r
	215	Method (_STA, 0)\r
	216	{\r
	217	if (LEqual (ACC0, 0xff))\r
	218	{\r
	219	Return (0)\r
	220	}\r
	221	Return (0x0f)\r
	222	}\r
	223	\r
	224	//\r
	225	// TCG Hardware Information\r
	226	//\r
	227	Method (HINF, 3, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
	228	{\r
	229	//\r
	230	// Switch by function index\r
	231	//\r
	232	Switch (ToInteger(Arg1))\r
	233	{\r
	234	Case (0)\r
	235	{\r
	236	//\r
	237	// Standard query\r
	238	//\r
	239	Return (Buffer () {0x03})\r
	240	}\r
	241	Case (1)\r
	242	{\r
	243	//\r
	244	// Return failure if no TPM present\r
	245	//\r
	246	Name(TPMV, Package () {0x01, Package () {0x2, 0x0}})\r
	247	if (LEqual (_STA (), 0x00))\r
	248	{\r
	249	Return (Package () {0x00})\r
	250	}\r
	251	\r
	252	//\r
253	// Return TPM version\r
254	//\r
255	Return (TPMV)\r
256	}\r
257	Default {BreakPoint}\r
258	}\r
259	Return (Buffer () {0})\r
260	}\r
261	\r
262	Name(TPM2, Package (0x02){\r
263	Zero, \r
264	Zero\r
265	})\r
266	\r
267	Name(TPM3, Package (0x03){\r
268	Zero, \r
269	Zero,\r
270	Zero\r
271	})\r
272	\r
273	//\r
274	// TCG Physical Presence Interface\r
275	//\r
276	Method (TPPI, 3, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
277	{ \r
278	//\r
279	// Switch by function index\r
280	//\r
281	Switch (ToInteger(Arg1))\r
282	{\r
283	Case (0)\r
284	{\r
285	//\r
286	// Standard query, supports function 1-8\r
287	//\r
288	Return (Buffer () {0xFF, 0x01})\r
289	}\r
290	Case (1)\r
291	{\r
292	//\r
293	// a) Get Physical Presence Interface Version\r
294	//\r
cd643013	295	Return ("$PV")\r
1abfa4ce JY	296	}\r
	297	Case (2)\r
	298	{\r
	299	//\r
	300	// b) Submit TPM Operation Request to Pre-OS Environment\r
	301	//\r
	302	\r
	303	Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
edb0fda2	304	Store (0, PPRM)\r
1abfa4ce JY	305	Store (0x02, PPIP)\r
	306	\r
	307	//\r
	308	// Triggle the SMI interrupt\r
	309	//\r
	310	Store (PPIN, IOB2)\r
	311	Return (FRET)\r
	312	\r
	313	\r
	314	}\r
	315	Case (3)\r
	316	{\r
	317	//\r
	318	// c) Get Pending TPM Operation Requested By the OS\r
	319	//\r
	320	\r
	321	Store (PPRQ, Index (TPM2, 0x01))\r
	322	Return (TPM2)\r
	323	}\r
	324	Case (4)\r
	325	{\r
	326	//\r
	327	// d) Get Platform-Specific Action to Transition to Pre-OS Environment\r
	328	//\r
	329	Return (2)\r
	330	}\r
	331	Case (5)\r
	332	{\r
	333	//\r
	334	// e) Return TPM Operation Response to OS Environment\r
	335	//\r
	336	Store (0x05, PPIP)\r
	337	\r
	338	//\r
	339	// Triggle the SMI interrupt\r
	340	//\r
	341	Store (PPIN, IOB2)\r
	342	\r
	343	Store (LPPR, Index (TPM3, 0x01))\r
	344	Store (PPRP, Index (TPM3, 0x02))\r
	345	\r
	346	Return (TPM3)\r
	347	}\r
	348	Case (6)\r
	349	{\r
	350	\r
	351	//\r
	352	// f) Submit preferred user language (Not implemented)\r
	353	//\r
	354	\r
	355	Return (3)\r
	356	\r
	357	}\r
	358	Case (7)\r
	359	{\r
	360	//\r
	361	// g) Submit TPM Operation Request to Pre-OS Environment 2\r
	362	//\r
	363	Store (7, PPIP)\r
	364	Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
	365	Store (0, PPRM)\r
	366	If (LEqual (PPRQ, 23)) {\r
	367	Store (DerefOf (Index (Arg2, 0x01)), PPRM)\r
	368	}\r
369	\r
370	//\r
371	// Triggle the SMI interrupt \r
372	//\r
373	Store (PPIN, IOB2) \r
374	Return (FRET)\r
375	}\r
376	Case (8)\r
377	{\r
378	//\r
379	// e) Get User Confirmation Status for Operation\r
380	//\r
381	Store (8, PPIP)\r
053f31e3	382	Store (DerefOf (Index (Arg2, 0x00)), UCRQ)\r
1abfa4ce JY	383	\r
	384	//\r
	385	// Triggle the SMI interrupt\r
	386	//\r
	387	Store (PPIN, IOB2)\r
	388	\r
	389	Return (FRET)\r
	390	}\r
	391	\r
	392	Default {BreakPoint}\r
	393	}\r
	394	Return (1)\r
	395	}\r
	396	\r
	397	Method (TMCI, 3, Serialized, 0, IntObj, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
	398	{\r
	399	//\r
	400	// Switch by function index\r
	401	//\r
	402	Switch (ToInteger (Arg1))\r
	403	{\r
	404	Case (0)\r
	405	{\r
	406	//\r
	407	// Standard query, supports function 1-1\r
	408	//\r
	409	Return (Buffer () {0x03})\r
	410	}\r
	411	Case (1)\r
	412	{\r
	413	//\r
	414	// Save the Operation Value of the Request to MORD (reserved memory)\r
	415	//\r
	416	Store (DerefOf (Index (Arg2, 0x00)), MORD)\r
	417	\r
	418	//\r
	419	// Triggle the SMI through ACPI _DSM method.\r
	420	//\r
	421	Store (0x01, MCIP)\r
	422	\r
	423	//\r
	424	// Triggle the SMI interrupt\r
	425	//\r
	426	Store (MCIN, IOB2)\r
	427	Return (MRET)\r
	428	}\r
	429	Default {BreakPoint}\r
	430	}\r
	431	Return (1) \r
	432	}\r
	433	\r
	434	Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})\r
	435	{\r
	436	\r
	437	//\r
	438	// TCG Hardware Information\r
	439	//\r
	440	If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))\r
	441	{\r
	442	Return (HINF (Arg1, Arg2, Arg3))\r
	443	}\r
	444	\r
	445	//\r
	446	// TCG Physical Presence Interface\r
447	//\r
448	If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))\r
449	{\r
450	Return (TPPI (Arg1, Arg2, Arg3))\r
451	}\r
452	\r
453	//\r
454	// TCG Memory Clear Interface\r
455	//\r
456	If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))\r
457	{\r
458	Return (TMCI (Arg1, Arg2, Arg3))\r
459	}\r
460	\r
461	Return (Buffer () {0})\r
462	}\r
463	}\r
464	}\r
465	}\r